Page 1
MCM63P531
1
MOTOROLA FAST SRAM
Advance Information
32K x 32 Bit Pipelined BurstRAM
Synchronous Fast Static RAM
The MCM63P531 is a 1M bit synchronous fast static RAM designed to provide
a burstable, high performance, secondary cache for the 68K Family , PowerPC,
and Pentium microprocessors. It is organized as 32K words of 32 bits each,
fabricated using high performance silicon gate CMOS technology. This device
integrates input registers, an output register, a 2–bit address counter, and high
speed SRAM onto a single monolithic circuit for reduced parts count in cache
data RAM applications. Synchronous design allows precise cycle control with the
use of an external clock (K). CMOS circuitry reduces the overall power consumption of the integrated functions for greater reliability.
Addresses (SA), data inputs (DQx), and all control signals except output enable (G
) and Linear Burst Order (LBO) are clock (K) controlled through positive–
edge–triggered noninverting registers.
Bursts can be initiated with either ADSP
or ADSC input pins. Subsequent burst
addresses can be generated internally by the MCM63P531 (burst sequence operates in linear or interleaved mode dependent upon state of LBO
) and controlled
by the burst address advance (ADV
) input pin.
Write cycles are internally self–timed and are initiated by the rising edge of the
clock (K) input. This feature eliminates complex off–chip write pulse generation
and provides increased timing flexibility for incoming signals.
Synchronous byte write (SBx
), synchronous global write (SGW), and synchro-
nous write enable SW
are provided to allow writes to either individual bytes or to
all bytes. The four bytes are designated as “a”, “b”, “c”, and “d”. SBa
controls
DQa, SBb
controls DQb, etc. Individual bytes are written if the selected byte
writes SBx
are asserted with SW. All bytes are written if either SGW is asserted
or if all SBx
and SW are asserted.
For read cycles, pipelined SRAMs output data is temporarily stored by an
edge–triggered output register and then released to the output buffers at the next
rising edge of clock (K).
The MCM63P531 operates from a 3.3 V power supply , all inputs and outputs
are LVTTL compatible.
• MCM63P531–4.5 = 4.5 ns access / 10 ns cycle
MCM63P531–7 = 7 ns access / 13.3 ns cycle
MCM63P531–8 = 8 ns access / 15 ns cycle
MCM63P531–9 = 9 ns access / 16.6 ns cycle
• Single 3.3 V + 10%, – 5% Power Supply
• ADSP
, ADSC, and ADV Burst Control Pins
• Selectable Burst Sequencing Order (Linear/Interleaved)
• Internally Self–Timed Write Cycle
• Byte Write and Global Write Control
• Sleep Mode (ZZ)
• Intel PBSRAM 2.0 Compliant
• Single–Cycle Deselect Timing
• 100 Pin TQFP Package
BurstRAM is a trademark of Motorola, Inc.
PowerPC is a trademark of IBM Corp.
Pentium is a trademark of Intel Corp.
This document contains information on a new product. Motorola reserves the right to change or discontinue this product without notice.
Order this document
by MCM63P531/D
MOTOROLA
SEMICONDUCTOR TECHNICAL DATA
MCM63P531
TQ PACKAGE
TQFP
CASE 983A–01
6/21/96
Motorola, Inc. 1996
Page 2
MCM63P531
2
MOTOROLA FAST SRAM
FUNCTIONAL BLOCK DIAGRAM
WRITE
REGISTER
a
WRITE
REGISTER
b
ENABLE
REGISTER
BURST
COUNTER
ADSP
G
CLR
WRITE
REGISTER
c
WRITE
REGISTER
d
SBa
SBb
SBc
SBd
SE3
13
15
SGW
DATA–OUT
REGISTER
ENABLE
REGISTER
K2 K
ADDRESS
REGISTER
15
DATA–IN
REGISTER
32K x 32 ARRAY
SE2
LBO
ADV
K
ADSC
SA
SA1
SA0
SW
SE1
K
4
32
2
2
K2
DQa – DQd
32
Page 3
MCM63P531
3
MOTOROLA FAST SRAM
PIN ASSIGNMENTS
71
72
DQc
V
DD
NC
69
70
66
67
68
64
65
61
62
63
37 3834 35 36 42 4339 40 41 45 4644
60
59
58
57
56
55
54
53
52
51
31 3233
74
75
76
77
78
79
80
50494847
DQb
DQb
V
SS
DQb
DQb
DQb
DQb
V
SS
V
DD
DQb
DQb
V
DD
V
SS
V
SS
V
DD
DQc
DQc
DQc
DQc
DQc
DQc
DQc
NC
SASASE1
SBd
K
SBc
ADV
G
ADSC
ADSP
SA0
SASASA
SA
NCNCNC
NC
V
SS
LBO
SA1
V
DD
V
DD
NC
DQa
V
SS
DQa
DQa
DQa
DQa
V
SS
V
DD
DQa
DQa
V
SS
V
DD
NC
DQa
DQd
V
DD
V
SS
V
SS
V
DD
DQd
DQd
DQd
DQd
DQd
73
NC
94 9397 96 95 89 8892 91 90 86 8587100 99 98 81828384
10
9
12
11
15
14
13
17
16
20
19
18
21
22
23
24
25
26
27
28
29
30
7
6
5
4
3
2
1
8
SA
SA
SW
SE2
SBb
SBa
SE3
VSSV
DD
SGW
ZZ
NC
V
DD
V
SS
DQd
DQd
NC
NC
NC
SASASA
SA
SA
Page 4
MCM63P531
4
MOTOROLA FAST SRAM
PIN DESCRIPTIONS
Pin Locations Symbol
Type Description
85 ADSC Input Synchronous Address Status Controller: Initiates READ, WRITE, or
chip deselect cycle.
84 ADSP Input Synchronous Address Status Processor: Initiates READ, WRITE, or
chip deselect cycle (exception — chip deselect does not occur when
ADSP is asserted and SE1 is high).
83 ADV Input Synchronous Address Advance: Increments address count in
accordance with counter type selected (linear/interleaved).
(a) 52, 53, 56, 57, 58, 59, 62, 63
(b) 68, 69, 72, 73, 74, 75, 78, 79
(c) 2, 3, 6, 7, 8, 9, 12, 13
(d) 18, 19, 22, 23, 24, 25, 28, 29
DQx I/O Synchronous Data I/O: “x” refers to the byte being read or written
(byte a, b, c, d).
86 G Input Asynchronous Output Enable Input:
Low — enables output buffers (DQx pins).
High — DQx pins are high impedance.
89 K Input Clock: This signal registers the address, data in, and all control signals
except G
, LBO, and ZZ.
31 LBO Input Linear Burst Order Input: This pin must remain in steady state (this
signal not registered or latched). It must be tied high or low.
Low — linear burst counter (68K/PowerPC).
High — interleaved burst counter (486/i960/Pentium).
32, 33, 34, 35, 44, 45, 46,
47, 48, 81, 82, 99, 100
SA Input Synchronous Address Inputs: These inputs are registered and must
meet setup and hold times.
36, 37 SA1,SA0 Input Synchronous Address Inputs: These pins must be wired to the two
LSBs of the address bus for proper burst operation. These inputs are
registered and must meet setup and hold times.
93, 94, 95, 96
(a) (b) (c) (d)
SBx Input Synchronous Byte Write Inputs: “x” refers to the byte being written (byte
a, b, c, d). SGW
overrides SBx.
98 SE1 Input Synchronous Chip Enable: Active low to enable chip.
Negated high–blocks ADSP
or deselects chip when ADSC is asserted.
97 SE2 Input Synchronous Chip Enable: Active high for depth expansion.
92 SE3 Input Synchronous Chip Enable: Active low for depth expansion.
88 SGW Input Synchronous Global Write: This signal writes all bytes regardless of the
status of the SBx
and SW signals. If only byte write signals SBx are
being used, tie this pin high.
87 SW Input Synchronous Write: This signal writes only those bytes that have been
selected using the byte write SBx
pins. If only byte write signals SBx
are being used, tie this pin low.
64 ZZ Input Sleep Mode: This active high asynchronous signal places the RAM into
the lowest power mode. The ZZ pin disables the RAMs internal clock
when placed in this mode. When ZZ is negated, the RAM remains in
low power mode until it is commanded to READ or WRITE. Data
integrity is maintained upon returning to normal operation.
4, 11, 15, 20, 27, 41, 54,
61, 65, 70, 77, 91
V
DD
Supply Power Supply: 3.3 V + 10%, – 5%.
5, 10, 17, 21, 26, 40, 55,
60, 67, 71, 76, 90
V
SS
Supply Ground.
1, 14, 16, 30, 38, 39, 42, 43, 49,
50, 51, 66, 80
NC — No Connection: There is no connection to the chip.
Page 5
MCM63P531
5
MOTOROLA FAST SRAM
TRUTH TABLE (See Notes 1 through 5)
Next Cycle
Address
Used
SE1 SE2 SE3 ADSP ADSC ADV G
3
DQx Write 2,
4
Deselect None 1 X X X 0 X X High–Z X
Deselect None 0 X 1 0 X X X High–Z X
Deselect None 0 0 X 0 X X X High–Z X
Deselect None X X 1 1 0 X X High–Z X
Deselect None X 0 X 1 0 X X High–Z X
Begin Read External 0 1 0 0 X X X High–Z READ
5
Begin Read External 0 1 0 1 0 X X High–Z READ
5
Continue Read Next X X X 1 1 0 1 High–Z READ
Continue Read Next X X X 1 1 0 0 DQ READ
Continue Read Next 1 X X X 1 0 1 High–Z READ
Continue Read Next 1 X X X 1 0 0 DQ READ
Suspend Read Current X X X 1 1 1 1 High–Z READ
Suspend Read Current X X X 1 1 1 0 DQ READ
Suspend Read Current 1 X X X 1 1 1 High–Z READ
Suspend Read Current 1 X X X 1 1 0 DQ READ
Begin Write External 0 1 0 1 0 X X High–Z WRITE
Continue Write Next X X X 1 1 0 X High–Z WRITE
Continue Write Next 1 X X X 1 0 X High–Z WRITE
Suspend Write Current X X X 1 1 1 X High–Z WRITE
Suspend Write Current 1 X X X 1 1 X High–Z WRITE
NOTES: 1. X = Don’t Care. 1 = logic high. 0 = logic low.
2. Write is defined as either 1) any SBx
and SW low or 2) SGW is low.
3.G
is an asynchronous signal and is not sampled by the clock K. G drives the bus immediately (t
GLQX
) following G going low.
4.On write cycles that follow read cycles, G
must be negated prior to the start of the write cycle to ensure proper write data setup times.
G
must also remain negated at the completion of the write cycle to ensure proper write data hold times.
5.This READ assumes the RAM was previously deselected.
ASYNCHRONOUS TRUTH TABLE
Operation ZZ G I/O Status
Read L L Data Out (DQx)
Read L H High–Z
Write L X High–Z
Deselected L X High–Z
Sleep H X High–Z
LINEAR BURST ADDRESS TABLE (LBO = V
SS
)
1st Address (External)
2nd Address (Internal) 3rd Address (Internal) 4th Address (Internal)
X . . . X00 X . . . X01 X . . . X10 X . . . X11
X . . . X01 X . . . X10 X . . . X11 X . . . X00
X . . . X10 X . . . X11 X . . . X00 X . . . X01
X . . . X11 X . . . X00 X . . . X01 X . . . X10
INTERLEAVED BURST ADDRESS TABLE (LBO = V
DD
)
1st Address (External)
2nd Address (Internal) 3rd Address (Internal) 4th Address (Internal)
X . . . X00 X . . . X01 X . . . X10 X . . . X11
X . . . X01 X . . . X00 X . . . X11 X . . . X10
X . . . X10 X . . . X11 X . . . X00 X . . . X01
X . . . X11 X . . . X10 X . . . X01 X . . . X00
Page 6
MCM63P531
6
MOTOROLA FAST SRAM
WRITE TRUTH TABLE
Cycle Type SGW SW SBa SBb SBc SBd
Read H H X X X X
Read H L H H H H
Write Byte a H L L H H H
Write Byte b H L H L H H
Write Byte c H L H H L H
Write Byte d H L H H H L
Write All Bytes H L L L L L
Write All Bytes L X X X X X
DC ABSOLUTE MAXIMUM RATINGS (See Note 1)
Rating
Symbol Value Unit
Power Supply Voltage V
DD
– 0.5 to + 4.6 V
Voltage Relative to VSS for Any
Pin Except V
DD
Vin, V
out
– 0.5 to VDD + 0.5 V
Output Current (per I/O) I
out
± 20 mA
Package Power Dissipation (See Note 2) P
D
1.6 W
Temperature Under Bias T
bias
– 10 to 85 °C
Storage Temperature T
stg
– 55 to 125 °C
NOTES:
1. Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are
exceeded. Functional operation should be restricted to RECOMMENDED OPERATING CONDITIONS. Exposure to higher than recommended voltages for extended
periods of time could affect device reliability.
2. Power dissipation capability is dependent upon package characteristics and use
environment. See Package Thermal Characteristics.
PACKAGE THERMAL CHARACTERISTICS
Rating Symbol Max Unit Notes
Thermal Resistance — — — 1
Junction to Ambient (@ 200 lfm) Single Layer Board
Four Layer Board
R
θJA
40
25
°C/W 2
Junction to Board (Bottom) R
θJB
17 °C/W 3
Junction to Case (Top) R
θJC
9 °C/W 4
NOTES:
1. Junction temperature is a function of on–chip power dissipation, package thermal resistance, mounting site (board) temperature, ambient
temperature, air flow, board population, and board thermal resistance.
2. Per SEMI G38–87.
3. Indicates the average thermal resistance between the die and the printed circuit board.
4. Indicates the average thermal resistance between the die and the case top surface via the cold plate method (MIL SPEC–883 Method
1012.1).
This device contains circuitry to protect the
inputs against damage due to high static volt
ages or electric fields; however, it is advised
that normal precautions be taken to avoid
application of any voltage higher than maximum rated voltages to this high–impedance
circuit.
Page 7
MCM63P531
7
MOTOROLA FAST SRAM
DC OPERATING CONDITIONS AND CHARACTERISTICS
(VDD = 3.3 V +10%, – 5%, TJ = 20 to 110°C, Unless Otherwise Noted)
RECOMMENDED OPERATING CONDITIONS
(Voltages referenced to VSS = 0 V)
Parameter
Symbol Min Typ Max Unit
Supply Voltage V
DD
3.135 3.3 3.6 V
Operating Temperature T
J
20 — 110 °C
Input Low Voltage V
IL
– 0.5* — 0.8 V
Input High Voltage Address and Control Inputs V
IH
2.0** — VDD + 0.5 V
*VIL ≥ – 1 V for t ≤ t
KHKH
/2.
**VIH ≤ VDD + 1 V for t ≤ t
KHKH
/2.
DC CHARACTERISTICS AND SUPPLY CURRENTS
Parameter Symbol Min Typ Max Unit Notes
Input Leakage Current (0 V ≤ Vin ≤ VDD) I
lkg
(I) — — ± 1 µA
Output Leakage Current (0 V ≤ Vin ≤ VDD) I
lkg
(O) — — ± 1 µA
AC Supply Current (Device Selected,
MCM63P531–4.5 I
DDA
— — TBD mA 3, 4, 5
Cycle Time ≥ t
KHKH
min) I
OUT
= 0
MCM63P531–7
MCM63P531–8
MCM63P531–9
I
DDA
— — 350
CMOS Standby Supply Current (Deselected,
MCM63P531–4.5 I
SB1
— — TBD mA 1
Clock (K) Cycle Time ≥ t
KHKH
, All Inputs Toggling at
CMOS Levels Vin ≤ VSS + 0.2 V or ≥ VDD – 0.2 V)
MCM63P531–7
MCM63P531–8
MCM63P531–9
I
SB1
— — 120
Sleep Mode Supply Current (Sleep Mode, Clock (K) Cycle Time ≥ t
KHKH
,
All Other Inputs Held to Static CMOS Levels Vin ≤ VSS + 0.2 V
or ≥ VDD – 0.2 V)
I
ZZ
(100 MHz)
I
ZZ
—
—
—
—
65
10
mA 2
Output Low Voltage (IOL = 8 mA) V
OL
— — 0.4 V
Output High Voltage (IOH = –4 mA) V
OH
2.4 — — V
NOTES:
1.Device in Deselected mode as defined by the Truth Table.
2.Device in Sleep Mode as defined by the Asynchronous Truth Table.
3.Reference AC Operating Conditions and Characteristics for input and timing (VIH/VIL, tr/tf, pulse level 0 to 3.0 V).
4.All addresses transition simultaneously low (LSB) and then high (MSB).
5.Data states are all zero.
CAPACITANCE (f = 1.0 MHz, dV = 3.0 V, T
J
= 20 to 110°C, Periodically Sampled Rather Than 100% Tested)
Parameter
Symbol Min Typ Max Unit
Input Capacitance C
in
— 3 5 pF
Input/Output Capacitance C
I/O
— 6 8 pF
Page 8
MCM63P531
8
MOTOROLA FAST SRAM
AC OPERATING CONDITIONS AND CHARACTERISTICS
(VDD = 3.3 V + 10%, – 5%, TJ = 20 to 110°C, Unless Otherwise Noted)
Input Timing Measurement Reference Level 1.5 V. . . . . . . . . . . . . . .
Input Pulse Levels 0 to 3.0 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input Rise/Fall Time 2 ns. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Output Timing Reference Level 1.5 V. . . . . . . . . . . . . . . . . . . . . . . . . .
Output Load See Figure 1 Unless Otherwise Noted. . . . . . . . . . . . . .
READ/WRITE CYCLE TIMING (See Notes 1, 2, 3, and 4)
MCM63P531–4.5
100 MHz
MCM63P531–7
75 MHz
MCM63P531–8
66 MHz
MCM63P531–9
60 MHz
Parameter Symbol Min Max Min Max Min Max Min Max Unit Notes
Cycle Time t
KHKH
10 — 13.3 — 15 — 16.6 — ns
Clock High Pulse Width t
KHKL
3.2 — 4.5 — 5 — 5 — ns
Clock Low Pulse Width t
KLKH
3.2 — 4.5 — 5 — 5 — ns
Clock Access Time t
KHQV
— 4.5 — 7 — 8 — 9 ns 5
Output Enable to Output
Valid
t
GLQV
— 4.5 — 6 — 6 — 7 ns 5
Clock High to Output Active t
KHQX1
0 — 0 — 0 — 0 — ns 5, 7
Clock High to Output
Change
t
KHQX2
1.5 — 2 — 2 — 2 — ns 5, 7
Output Enable to Output
Active
t
GLQX
0 — 0 — 0 — 0 — ns 5, 7
Output Disable to Q High–Z t
GHQZ
— 5.5 — 7 — 8 — 9 ns 6, 7
Clock High to Q High–Z t
KHQZ
1.5 10 2 7 2 8 2 9 ns 6, 7
Setup Times: Address
ADSP
, ADSC, ADV
Data In
Write
Chip Enable
t
ADKH
t
ADSKH
t
DVKH
t
WVKH
t
EVKH
2.0 — 2.5 — 2.5 — 2.5 — ns
4
Hold Times: Address
ADSP
, ADSC, ADV
Data In
Write
Chip Enable
t
KHAX
t
KHADSX
t
KHDX
t
KHWX
t
KHEX
0.5 — 0.5 — 0.5 — 0.5 — ns
4
NOTES:
1. Write applies to all SBx
, SW, and SGW signals when the chip is selected and ADSP high.
2. Chip Enable applies to all SE1
, SE2 and SE3 signals whenever ADSP or ADSC is asserted.
3. All read and write cycle timings are referenced from K or G
.
4. G
is a don’t care after write cycle begins. To prevent bus contention, G should be negated prior to start of write cycle.
5. Tested per AC Test Load.
6. Measured at
± 200 mV from steady state. Tested per High–Z Test Load.
7. This parameter is sampled and is not 100% tested.
(a) AC Test Load (b) High–Z Test Load
5 pF
+ 3.3 V
OUTPUT
317
Ω
351
Ω
OUTPUT
Z0 = 50
Ω
RL = 50
Ω
VT = 1.5 V
Figure 1. Test Loads
Page 9
MCM63P531
9
MOTOROLA FAST SRAM
BURST READSINGLE READ
ADSC
t
KHKL
t
KHKH
DQx
E
K
ADSP
ADV
Q(A)
BURST WRITE
ADSP, SA
SA
A B
READ/WRITE CYCLES
t
KLKH
C D
SE1
W
Q(B) Q(B+1)
t
KHQV
BURST WRAPS AROUND
Q(B+2) Q(B+3)
Q(B) D(C) D(C+1) D(C+2) D(C+3) Q(D)
t
KHQV
DESELECTED SINGLE READ
SE2, SE3
IGNORED
G
t
KHQX1
t
KHQX2
t
GHQZ
t
GLQX
W low = SGW low and / or SW and SBx low.
Note: E low = SE2 high and SE3 low.
Q(n–1)
t
KHQZ
Page 10
MCM63P531
10
MOTOROLA FAST SRAM
ЙЙЙЙЙЙЙЙЙЙЙЙЙ
ЙЙЙЙЙЙЙЙЙЙЙЙЙ
ЙЙЙЙЙЙЙЙЙЙЙЙЙ
ЙЙЙЙЙЙЙЙЙЙЙЙЙ
ЙЙЙЙЙЙЙЙЙЙЙЙЙ
ЙЙЙЙЙЙЙЙЙЙЙЙЙ
ЙЙЙЙЙЙЙЙЙЙЙЙЙ
ZZ
E
K
ADS
ADV
SLEEP MODE TIMING
W
G
t
ZZQZ
ADS high = both ADSC, ADSP high.
NOTE: ADS low = ADSC low or ADSP low.
IDD
t
ZZS
t
ZZREC
E low = SE1 low, SE2 high, SE3 low.
(= 15 ns)
(= 100 ns)
(= 100 ns)
ADDR
DQ
NORMAL OPERATION
NO READS OR
WRITES ALLOWED
IN SLEEP MODE
NO NEW READS OR
WRITES ALLOWED
NORMAL OPERATION
I
ZZ
Page 11
MCM63P531
11
MOTOROLA FAST SRAM
APPLICATION INFORMATION
The MCM63P531 BurstRAM is a high speed synchronous
SRAM intended for use primarily in secondary or level two (L2)
cache memory applications. L2 caches are found in a variety
of classes of computers – from the desktop personal computer
to the high–end servers and transaction processing machines. For simplicity, the majority of L2 caches today are direct mapped and are single bank implementations. These
caches tend to be designed for bus speeds in the range of 33
to 66 MHz. At these bus rates, non–pipelined (flow–through)
BurstRAMs can be used since their access times meet the
speed requirements for a minimum–latency, zero–wait state
L2 cache interface. Latency is a measure (time) of “dead” time
the memory system exhibits as a result of a memory request.
For those applications that demand bus operation at greater
than 66 MHz or multi–bank L2 caches at 66 MHz, the pipelined
(register/register) v ersion o f the 3 2Kx32 B urstRAM
(MCM63P531) allows the designer to maintain zero–wait
state operation. Multiple banks of BurstRAMs create additional bus loading and can cause the system to otherwise miss its
timing requirements. The access time (clock–to–valid–data)
of a pipelined BurstRAM is inherently faster than a non–pipelined device by a few nanoseconds. This does not come without cost. The cost is latency – “dead” time.
Since most L2 caches are tied to the processor bus and bus
speeds continue to i ncrease o ver time, pipelined (R/R)
BurstRAMs are the best choice in achieving zero–wait state
L2 cache performance. For cost–sensitive applications that
require zero–wait state L2 cache bus speeds of up to 75 MHz,
pipelined BurstRAMs are able to provide fast clock to valid
data times required of these high speed buses.
SLEEP MODE
A sleep mode feature, the ZZ pin, has been implemented on
the MCM63P531. It allows the system designer to place the
RAM in the lowest possible power condition by asserting ZZ.
The sleep mode timing diagram shows the different modes of
operation: Normal Operation, No READ/WRITE Allowed, and
Sleep Mode. Each mode has its own set of constraints and
conditions that are allowed.
Normal Operation: a ll inputs must meet setup and hold
times prior to sleep and t
ZZREC
nanoseconds after recovering
from sleep. Clock (K) must also meet cycle, high, and low
times during these periods. Two cycles prior to sleep, initiation
of either a read or write operation is not allowed.
No READ/WRITE: during the period of time just prior to
sleep and during recovery from sleep, the assertion of either
ADSC
, ADSP, or any write signal is not allowed. If a write op-
eration occurs during these periods, the memory array may be
corrupted. V alidity of data out from the RAM cannot be guaranteed immediately after ZZ is asserted (prior to being in sleep).
Sleep Mode: the RAM automatically deselects itself. The
RAM disconnects its internal clock buffer. The external clock
may continue to run without impacting the RAMs sleep current
(IZZ). All inputs are allowed to toggle – the RAM will not be selected and perform any reads or writes. However, if inputs
toggle, the IZZ (max) specification will not be met.
FUNCTIONAL EQUIVALENT
The following describes t he configuration o f the
MCM63P531 as a functional equivalent to a 5 V BurstRAM. A
migration from 5 V BurstRAMs to 3.3 V BurstRAMs (e.g.
MCM63P531) can be somewhat confusing due to functional
and pinout differences. Because the 3.3 V devices offer more
pins than the 5 V PLCC devices, it is no longer necessary to
supply multiple part numbers for the different burst, address
pipeline support (“H” part), etc. options. The MCM63P531 can
be configured to function as if it were the equivalent of two 5
V BurstRAMs, assuming parity is not required. The following
table lists control pins on the MCM63P531 that can be tied off
to either 3.3 V or ground in order to satisfy the migration to this
3.3 V RAM.
CONTROL PIN TIE VALUES
(H ≥ VIH, L ≤ VIL)
5 V Device Numbers
ADSP ADSC ADV SE1 LBO
MCM67C518 — — — L H
MCM67J518 — — — — H
MCM67N518 — — — L L
NOTE: If no tie value is given, then the pin should be used as intended
on the 5 V device.
NON–BURST SYNCHRONOUS OPERATION
Although this BurstRAM has been designed for PowerPC–
and Pentium – based systems, these SRAMs can be used in
other high speed L2 cache or memory applications that do not
require the burst address feature. Most L2 caches designed
with a synchronous i nterface can make use of the
MCM63P531. The burst counter feature of the
BurstRAM can be disabled, and the SRAM can be configured
to act upon a continuous stream of addresses. See Figure 2.
CONTROL PIN TIE VALUES
(H ≥ VIH, L ≤ VIL)
Non–Burst
ADSP ADSC ADV SE1 LBO
Sync Non–Burst,
Pipelined SRAM
H L H L X
NOTE: Although X is specified in the table as a don’t care, the pin must
be tied either high or low.
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MCM63P531
12
MOTOROLA FAST SRAM
WRITESREADS
DQx
K
Q(B)Q(A)
ADDR
A B
C D E F G H
W
Q(D)Q(C) D(F)D(E) D(H)D(G)
G
Figure 2. Configured as Non–Burst Pipelined Synchronous SRAM
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MCM63P531
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MOTOROLA FAST SRAM
ORDERING INFORMATION
(Order by Full Part Number)
MCM 63P531 XX X X
Motorola Memory Prefix
Part Number
Full Part Numbers — MCM63P531TQ4.5 MCM63P531TQ7 MCM63P531TQ8 MCM63P531TQ9
MCM63P531TQ4.5R MCM63P531TQ7R MCM63P531TQ8R MCM63P531TQ9R
Speed (4.5 = 4.5 ns, 7 = 7 ns, 8 = 8 ns, 9 = 9 ns)
Package (TQ = TQFP)
Blank = Trays, R = Tape and Reel
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MCM63P531
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MOTOROLA FAST SRAM
TQ PACKAGE
TQFP
CASE 983A–01
PACKAGE DIMENSIONS
DIM MIN MAX MIN MAX
INCHESMILLIMETERS
A ––– 1.60 ––– 0.063
A1 0.05 0.15 0.002 0.006
A2 1.35 1.45 0.053 0.057
b 0.22 0.38 0.009 0.015
b1 0.22 0.33 0.009 0.013
c 0.09 0.20 0.004 0.008
c1 0.09 0.16 0.004 0.006
D 22.00 BSC 0.866 BSC
E 16.00 BSC 0.630 BSC
E1 14.00 BSC 0.551 BSC
e 0.65 BSC 0.026 BSC
L 0.45 0.75 0.018 0.030
L1 1.00 REF 0.039 REF
L2 0.50 REF
S 0.20 ––– 0.008 –––
R1 0.08 ––– 0.003 –––
R2 0.08 0.20 0.003 0.008
q
0 7 0 7
q
0 ––– 0 –––
q
11 13 11 13
q
11 13 11 13
1
2
3
D1 20.00 BSC 0.787 BSC
0.020 REF
_
_
_
_
_
_
_
_
_
_
_
_
_
_
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DATUM PLANE –H– IS LOCATED AT BOTTOM OF
LEAD AND IS COINCIDENT WITH THE LEAD
WHERE THE LEAD EXITS THE PLASTIC BODY AT
THE BOTTOM OF THE PARTING LINE.
4. DATUMS –A–, –B– AND –D– TO BE DETERMINED
AT DATUM PLANE –H–.
5. DIMENSIONS D AND E TO BE DETERMINED AT
SEATING PLANE –C–.
6. DIMENSIONS D1 AND E1 DO NOT INCLUDE MOLD
PROTRUSION. ALLOWABLE PROTRUSION IS 0.25
(0.010) PER SIDE. DIMENSIONS D1 AND B1 DO
INCLUDE MOLD MISMATCH AND ARE
DETERMINED AT DATUM PLANE –H–.
7. DIMENSION b DOES NOT INCLUDE DAMBAR
PROTRUSION. DAMBAR PROTRUSION SHALL
NOT CAUSE THE b DIMENSION TO EXCEED 0.45
(0.018).
A–B0.20 (0.008) H
e
D
A–B0.20 (0.008)
C D
A–B0.20 (0.008)
C D
0.10 (0.004)
C
0.25 (0.010)
S
0.05 (0.002)
S
A–B
M
0.13 (0.005) D
S
C
e/2
D/2
E
E1
D1
D
D1/2
E1/2
E/2
4X
2X 30 TIPS
2X 20 TIPS
–D–
–B–
–A–
–C–
–H–
q
1
q
3
q
2
q
100
81
80 51
50
31
301
PLATING
SECTION B–B
c1
c
b
b1
BASE
METAL
A
SEATING
PLANE
VIEW AB
S
VIEW AB
A2
A1
R1
L2
L
L1
R2
GAGE PLANE
–X–
VIEW Y
B
B
X=A, B, OR D
Page 15
MCM63P531
15
MOTOROLA FAST SRAM
Motorola reserves the right to make changes without further notice to any products herein. Motorola makes no warranty , representation or guarantee regarding
the suitability of its products for any particular purpose, nor does Motorola assume any liability arising out of the application or use of any product or circuit, and
specifically disclaims any and all liability, including without limitation consequential or incidental damages. “T ypical” parameters which may be provided in Motorola
data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals”
must be validated for each customer application by customer’s technical experts. Motorola does not convey any license under its patent rights nor the rights of
others. Motorola products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other
applications intended to support or sustain life, or for any other application in which the failure of the Motorola product could create a situation where personal injury
or death may occur. Should Buyer purchase or use Motorola products for any such unintended or unauthorized application, Buyer shall indemnify and hold Motorola
and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees
arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that
Motorola was negligent regarding the design or manufacture of the part. Motorola and are registered trademarks of Motorola, Inc. Motorola, Inc. is an Equal
Opportunity/Affirmative Action Employer.
Page 16
MCM63P531
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MOTOROLA FAST SRAM
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MCM63P531/D
*MCM63P531/D*
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