Page 1
SEMICONDUCTOR TECHNICAL DATA
1
REV 1
Motorola, Inc. 1996
5/96
The SX1125 is an integrated limiting amplifier for high frequency fiber
optic applications. The device interfaces directly to the trans–impedance
amplifier of a typical optical to electrical conversion portion of a fiber optic
link. With data rate capabilities in the 622Mb/s range, the high gain
limiting amplification of the SX1125 is ideal for high speed fiber optic
applications like SONET/SDM, A TM, FDDI, Fibre Channel or Serial Hippi.
The device is functionally and pin compatible to the Signetics SA5225
with a significantly higher bandwidth. The C
AZP
and C
AZN
inputs to the
limiting amplifier provide an auto-zero function to effectively cancel any
input offset voltage present in the amplifier.
The SX1125 incorporates a programmable level detect function to
identify when the input signal has been lost. This information can be fed
back to the Disable input of the device to maintain stability under loss of
signal conditions. Using the V
set
pin the sensitivity of the level detect can
be adjusted. The CLD input is used to filter the level detect input so that
random noise spikes are filtered out.
The MC10SX1125 is compatible with MECL10H logic levels.
• Wideband Operation: 20kHz to 550MHz
• Programmable Input Signal Level Detection
• Operation with single +5V or standard ECL supply
• Standard 16-lead SOIC Package
• Fully Differential Design to Minimize Noise Affects
• 10KH Compatible
BLOCK DIAGRAM
LOS
LOS
D
out
D
out
Reference
ECL
Buffer
Level
Detect
Limiting
Amplifier
ECL
Buffer
Disable
Disable
C
LD
D
in
D
in
V
ref
V
set
C
AZPCAZN
1516 14 13 12 11 10
21 34567
V
set
9
8
V
refVCCEDout
D
out
GNDELOS LOS
C
AZNCAZP
GNDADinD
in
V
CCACLD
Disable
Pinout: 16-Lead Plastic Package
(Top View)
FIBER OPTIC
POST AMPLIFIER
D SUFFIX
PLASTIC SOIC PACKAGE
CASE 751B-05
Page 2
MC10SX1125
MOTOROLA ECLinPS and ECLinPS Lite
DL140 — Rev 3
2
FUNCTION TABLE
Pin Function
C
AZN
Auto-zero capacitor pin. A capacitor between this pin and C
AZP
cancels any offset inherent to the limiting amplifier.
C
AZP
Auto-zero capacitor pin. A capacitor between this pin and C
AZN
cancels any offset inherent to the limiting amplifier.
GND
A
Analog ground pin. Ground for PECL operation or –5.2V for standard ECL operation. GNDA and GNDE must be at the same
potential.
Din, D
in
Differential data input.
V
CCA
Analog power supply pin. +5V for PECL operation or ground for standard ECL operation. V
CCA
and V
CCE
must be at the
same potential.
C
LD
Filter capacitor for the level detect comparator. Capacitor should be connected to V
CCA
.
Disable When asserted LOW, or left open and pulled LOW via the input pulldown resistor , the output buffer will be enabled and will
respond to the input stimulus on the Din input. Forcing Disable HIGH will force the D
out
output LOW and its complimentary
output HIGH.
LOS Loss of signal. This output will go HIGH when the input signal falls below (V
set
/100) mV
P-P
.
GND
E
Digital ground pin. Ground for PECL operation or –5.2V for standard ECL operation. GNDA and GNDE must be at the same
potential.
D
out
, D
out
Differential data outputs.
V
CCE
Digital power supply pin. +5V for PECL operation or ground for standard ECL operation. V
CCA
and V
CCE
must be at the
same potential.
V
ref
Reference voltage for threshold level set voltage division network (2.64V).
V
set
Input threshold level detect setting input. Input generated from voltage divider between V
ref
and GNDA.
Figure 1. Typical Operating Circuit
161
C
AZN
V
set
152
C
AZP
V
ref
143
GND
A
V
CCE
134
D
in
D
out
125
D
in
D
out
116
V
CCA
GND
E
107
C
LD
LOS
98
Disable LOS
R1 R2
50
DATA OUT
50
5V
3V
50
LEVEL
DETECT OUT
50
C
bypass
C
AZ
C
in
C
in
DATA IN
5V
C
AZ
C
bypass
Page 3
MC10SX1125
ECLinPS and ECLinPS Lite
DL140 — Rev 3
3 MOTOROLA
Coupling Capacitors
The SX1125 inputs must be AC coupled to allow proper
operation of the offset correction function. The coupling
capacitors, Cin, must be large enough to pass the lowest
input frequency of interest.
Cin+
1
2p(Rin)(f
low
)
where Rin= input resistance = 5000Ω
f
low
= lowest frequency.
Auto–zero Capacitors
A feedback amplifier is used to cancel the offset voltage of
the forward signal path, so the input to the internal ECL
comparator is at its toggle point in the absence of any input
signal. The time constant of the cancelling circuitry is set by
an external capacitor (CAZ) connected between Pins 1 and 2.
The formula for the calculation of the auto–zero capacitor is:
CAZ+
150
2p(RAZ)(f
low
)
where RAZ= internal driving impedance = 290kΩ
f
low
= lowest frequency.
Input Signal Level Detector
The SX1125 allows for user programmable input signal
level–detection and can automatically disable the switching
of its ECL data output if the input level is below a set
threshold. This prevents the outputs from reacting to noise in
the absence of a valid input signal, and ensures that data will
only be transmitted when the signal–to–noise ratio is
sufficient for low bit–error–rate system operation.
Complimentary ECL flags (LOS and LOSB) indicate whether
the input signal is above or below the desired threshold level.
In the level detect system, the input signal is amplified and
rectified before being compared to a programmable
reference. A filter is included to prevent noise spikes from
triggering the level–detector. The filter has a nominal 1µs
time constant, and additional filtering can be achieved by
using an external capacitor (CLD) from Pin 7 to V
CCA
(the
internal driving impedance is nominally 28k). The formula for
the calculation of the CLD capacitor is:
CLD+
t
R
Z
where RZ= internal driving impedance = 28kΩ
t = LOS filter time constant.
DC CHARACTERISTICS (GNDA = GNDE = Ground; V
CCA
= V
CCE
= 4.5V to 5.5V)
Symbol Characteristic Min Typ Max Unit Condition
V
IN
Input Signal Voltage (Din) Single-Ended 0.008 1.5 V
P-P
Note 1.
V
OS
Input Offset Voltage 50 µV
V
N
Input RMS Noise 225 µV
V
TH
Input Level Detect Programmability 8.0 20 mV
P-P
V
HYS
Level Detect Hysteresis 1.5 2.5 7.0 dB Note 2.
I
IH
Input HIGH Current Disable 150 µA
I
CC
Power Supply Current 33 45 mA
1. This device functions with Vinmin = 6mV
P–P
, but with increased BER (See BER data).
2. This device has an anomoly in V
HYS
when 0.65 < V
SET
< 0.75V . Operation in this region is not recommended. (See Figure 3)
0
5
10
15
20
25
30
35
0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 1.1 1.2 1.3 1.4
Vset (V)
V
Figure 2. LOS versus Vset (TA = 25°C)
0
1
2
3
4
5
6
7
8
0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 1.1 1.2 1.3 1.4
Vset (V)
(dB)
Figure 3. LOS Hysteresis (TA = 25°C)
HYS
V
IN
(mVpp)
Input detect
level (LOS 1
→
0)
Page 4
MC10SX1125
MOTOROLA ECLinPS and ECLinPS Lite
DL140 — Rev 3
4
I/O DC CHARACTERISTICS
1
–40°C 0°C 25°C 85°C
Symbol Characteristic Min Max Min Max Min Max Min Max Unit
V
OH
Output HIGH Voltage
VCC = –4.5 to –5.5V
VCC = 5.0V
2
1080
3920
–890
4110
1020
3980
–840
4160
–980
4020
–810
4190
–910
4090
–720
4280
mV
V
OL
Output LOW Voltage
VCC = –4.5 to –5.5V
VCC = 5.0V
2
–1950
3050
–1650
3350
–1950
3050
–1630
3370
–1950
3050
–1630
3370
–1950
3050
–1595
3405
mV
V
IH
Input HIGH Voltage
3
VCC = –4.5 to –5.5V
VCC = 5.0V
2
–1230
3770
–890
4110
–1170
3830
–840
4160
–1130
3870
–810
4190
–1060
3940
–720
4280
mV
V
IL
Input LOW Voltage
3
VCC = –4.5 to –5.5V
VCC = 5.0V
2
–1950
3050
–1500
3500
–1950
3050
–1480
3520
–1950
3050
–1480
3520
–1950
3050
–1445
3555
mV
I
IL
Input LOW Current
3
0.5 0.5 0.5 0.3 µA
1. 10SX circuits are designed to meet the DC specifications shown in the table after thermal equilibrium has been established. The circuit is in
a test socket or mounted on a printed circuit board and transverse airflow greater than 500lfpm is maintained. Outputs are terminated through
a 50Ω resistor to –2.0 volts except where otherwise specified on the individual data sheets.
2. Limits hold for VCC = 5.0V only. Parametric values will vary 1:1 with any variation of VCC.
3. Parametric values for the Disable input only.
AC CHARACTERISTICS (V
CCA
= V
CCE
= 4.5V to 5.5V)
Symbol Characteristic Min Typ Max Unit Condition
BW
min
Lower –3dB Bandwidth 20 kHz
BW
max
Upper –3dB Bandwidth 550 MHz
t
PWD
Pulse Width Distortion 70 ps
tr, t
f
Rise/Fall Times 150 250 650 ps 20% – 80%
R
AZ
Auto-Zero Output Resistance 200 325 450 kΩ
R
F
Level Detect Filter Resistance 14 25 41 kΩ
t
LD
Level Detect Time Constant 0.5 4.0 µs
BER (Bit–Error–Rate)
Using a 622Mb/s SONET STS–12 pattern, the SX1125 shows the following typical BERs at T = 25°C:
Input V
pp
BER
6mV
7mV
8mV
4E–13
<1E–14
<5E–15
Page 5
MC10SX1125
ECLinPS and ECLinPS Lite
DL140 — Rev 3
5 MOTOROLA
OUTLINE DIMENSIONS
D SUFFIX
PLASTIC SOIC PACKAGE
CASE 751B-05
0.25 (0.010) T B A
M
S S
MIN MINMAX MAX
MILLIMETERS INCHES
DIM
A
B
C
D
F
G
J
K
M
P
R
9.80
3.80
1.35
0.35
0.40
0.19
0.10
0
°
5.80
0.25
10.00
4.00
1.75
0.49
1.25
0.25
0.25
7
°
6.20
0.50
0.386
0.150
0.054
0.014
0.016
0.008
0.004
0
°
0.229
0.010
0.393
0.157
0.068
0.019
0.049
0.009
0.009
7
°
0.244
0.019
1.27 BSC 0.050 BSC
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSION A AND B DO NOT INCLUDE MOLD
PROTRUSION.
4. MAXIMUM MOLD PROTRUSION 0.15 (0.006)
PER SIDE.
5. DIMENSION D DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.127 (0.005) TOTAL
IN EXCESS OF THE D DIMENSION AT
MAXIMUM MATERIAL CONDITION.
1
8
916
-A-
-B-
D
16 PL
K
C
G
-T-
SEATING
PLANE
R X 45°
M
J
F
P
8 PL
0.25 (0.010) B
M M
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MC10SX1125/D
*MC10SX1125/D*
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