Datasheet MC10H640FNR2, MC100H640FNR2 Datasheet (MOTOROLA)

Page 1

MOTOROLA

SEMICONDUCTOR TECHNICAL DATA

68030/040 PECL-TTL Clock Driver

The MC10H/100H640 generates the necessary clocks for the 68030, 68040 and similar microprocessors. It is guaranteed to meet the clock specifications required by the 68030 and 68040 in terms of part–to–part skew, within–part skew and also duty cycle skew.

The user has a choice of using either TTL or PECL (ECL referenced to +5.0V) for the input clock. TTL clocks are typically used in present MPU systems. However, as clock speeds increase to 50MHz and beyond, the inherent superiority of ECL (particularly differential ECL) as a means of clock signal distribution becomes increasingly evident. The H640 also uses differential PECL internally to achieve its superior skew characteristic.

The H640 includes divide–by–two and divide–by–four stages, both to achieve the necessary duty cycle skew and to generate MPU clocks as required. A typical 50MHz processor application would use an input clock running at 100MHz, thus obtaining output clocks at 50MHz and 25MHz (see Logic Symbol).

The 10H version is compatible with MECL 10H ECL logic levels, while the 100H version is compatible with 100K levels (referenced to +5.0V).

• Generates Clocks for 68030/040

• Meets 030/040 Skew Requirements

• TTL or PECL Input Clock

• Extra TTL and PECL Power/Ground Pins

• Asynchronous Reset

• Single +5.0V Supply

MC10H640

MC100H640

68030/040

PECL–TTL CLOCK

DRIVER

FN SUFFIX

PLASTIC PACKAGE

CASE 776–02

Function

Reset (R):

Power–Up:

Select (SEL):

The H640 also contains circuitry to force a stable state of the ECL input differential pair, should both sides be left open. In this case, the DE side of the input is pulled LOW, and DE

LOW on RESET forces all Q outputs LOW and all Q outputs HIGH.

The device is designed to have the POS edges of the ÷2 and ÷4 outputs synchronized at power up.

LOW selects the ECL input source (DE/DE). HIGH selects the TTL input source (DT).

goes HIGH.

VT VT Q1 GT GT Q0 VT

25 24 23 22 21 20 19

Pinout: 28–Lead PLCC

(Top View)

567891011

GT GT Q4 Q5 VT SEL

DTQ0

11/93

 Motorola, Inc. 1996

2–1

REV 3

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MC10H640 MC100H640

LOGIC DIAGRAM

TTL Outputs

PIN NAMES

TTL/ECL Clock Inputs

DE DE

SEL

MUX

÷ 2

÷ 4

GT VT VE GE DE, DE V

DT Qn, Qn SEL R

PIN FUNCTION

TTL Ground (0 V) TTL VCC (+5.0 V) ECL VCC (+5.0 V) ECL Ground (0 V) ECL Signal Input (positive ECL) VBB Reference Output TTL Signal Input Signal Outputs (TTL) Input Select (TTL) Reset (TTL)

TTL Control Inputs

AC CHARACTERISTICS (VT = VE = 5.0V ±5%)

0°C 25°C 85°C

Symbol Characteristic Min Max Min Max Min Max Unit Condition

PLH

tskwd* Within–Device Skew 0.5 0.5 0.5 ns CL = 25pF t

PLH

max

* Within–Device Skew defined as identical transitions on similar paths through a device.

Propagation Delay ECL D to Output

Propagation Delay TTL D to Output

Propagation Delay ECL D to Output

Propagation Delay TTL D to Output

Propagation Delay ECL D to Output

Propagation Delay TTL D to Output

Propagation Delay R to Output

Output Rise/Fall Time

0.8 V – 2.0 V Maximum Input Frequency 135 135 135 MHz CL = 25pF Minimum Pulse Width 1.50 1.50 1.50 ns Reset Recovery Time 1.25 1.25 1.25 ns

Q0–Q3 4.9 5.9 4.9 5.9 5.2 6.2 ns CL = 25pF

5.0 6.0 5.0 6.0 5.3 6.3 ns CL = 25pF

Q0, Q1 4.9 5.9 4.9 5.9 5.2 6.2 ns CL = 25pF

5.0 6.0 5.0 6.0 5.3 6.3 ns CL = 25pF

Q4, Q5 4.9 5.9 4.9 5.9 5.2 6.2 ns CL = 25pF

5.0 6.0 5.0 6.0 5.3 6.3 ns CL = 25pF

All Outputs

4.3 6.3 4.3 6.3 5.0 7.0 ns CL = 25pF

2.5

ns CL = 25pF

MOTOROLA MECL Data

2–2

DL122 — Rev 6

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MC10H640 MC100H640

VCC and CLOAD RANGES TO MEET DUTY CYCLE REQUIREMENTS (0°C ≤ TA ≤ 85°C Output Duty Cycle Measured

Relative to 1.5V)

Symbol Characteristic Min Nom Max Unit Condition

Range of VCC and CL to meet minimum pulse width (HIGH or LOW) = 11.5 ns at f

Range of VCC and CL to meet minimum pulse width (HIGH or LOW) = 9.5 ns at 40 < f

≤ 40 MHz

out

≤ 50 MHz

DC CHARACTERISTICS (VT = VE = 5.0 V ±5%)

0°C 25°C 85°C

Symbol Characteristic Min Max Min Max Min Max Unit Condition

CCH

CCL

Power Supply Current ECL 57 57 57 mA VE Pin

TTL 30 30 30 mA Total all VT pins

30 30 30 mA

4.75 10

4.875155.0 5.125

5.0 5.25 50

Q0–Q3

–Q1

Q0 Q0–Q3

TTL DC CHARACTERISTICS (VT = VE = 5.0 V ±5%)

0°C 25°C 85°C

Symbol Characteristic Min Max Min Max Min Max Unit Condition

V V

I V

V V I

IH IL

OL IK

Input HIGH Voltage Input LOW Voltage

Input HIGH Current 20

Input LOW Current –0.6 –0.6 –0.6 mA VIN = 0.5V Output HIGH Voltage 2.5

Output LOW Voltage 0.5 0.5 0.5 V IOL = 24mA Input Clamp Voltage –1.2 –1.2 –1.2 V IIN = –18mA Output Short Circuit Current –100 –225 –100 –225 –100 –225 mA V

2.0

0.8

100

2.0

2.5

2.0

0.8 20

100

2.0

2.5

2.0

0.8 20

100

µA VIN = 2.7V

VIN = 7.0V

V IOH = –3.0mA

IOH = –15mA

= 0V

OUT

DL122 — Rev 6

2–3 MOTOROLAMECL Data

Page 4

MC10H640 MC100H640

10H PECL DC CHARACTERISTICS (VT = VE = 5.0 V ±5%)

0°C 25°C 85°C

Symbol Characteristic Min Max Min Max Min Max Unit Condition

VIH* VIL*

VBB* Output Reference Voltage 3.62 3.73 3.65 3.75 3.69 3.81 V

*NOTE: PECL levels are referenced to VCC and will vary 1:1 with the power supply. The values shown are for VCC = 5.0V.

100H PECL DC CHARACTERISTICS (VT = VE = 5.0 V ±5%)

Symbol Characteristic Min Max Min Max Min Max Unit Condition

VIH* VIL*

VBB* Output Reference Voltage 3.62 3.74 3.62 3.74 3.62 3.74 V

*NOTE: PECL levels are referenced to VCC and will vary 1:1 with the power supply. The values shown are for VCC = 5.0V.

Input HIGH Current Input LOW Current

Input HIGH Voltage Input LOW Voltage

Input HIGH Current Input LOW Current

Input HIGH Voltage Input LOW Voltage

0.5

3.83

3.05

0.5

3.835

3.19

225

4.16

3.52

0°C 25°C 85°C

225

4.12

3.525

0.5

3.87

3.05

0.5

3.835

3.19

175

4.19

3.52

175

4.12

3.525

0.5

3.94

3.05

0.5

3.835

3.19

175 µA

4.28

3.555

175 µA

4.12

3.525

V VE = 5.0V

10/100H640

DUTY CYCLE CONTROL

T o maintain a duty cycle of ±5% at 50MHz, limit the load capacitance and/or power supply variation as shown in Figures 1 and 2. For a ±2.5% duty cycle limit, see Figures 3 and 4. Figures 5 and 6 show duty cycle variation with temperature. Figure 7 shows typical TPD versus load. Figure 8 shows reset recovery time. Figure 9 shows output states after power up.

Best duty cycle control is obtained with a single µP load and minimum line length.

MOTOROLA MECL Data

2–4

DL122 — Rev 6

Page 5

MC10H640 MC100H640

LSE

5.25 V

5 V

4.75 V

PW (ns)

NEGATIVE PULSE WIDTH (ns)

4.75 V 5 V

5.25 V

0 25507585

LOAD (pF)

Figure 1. Positive Pulse Width at

25°C Ambient and 50 MHz Out

5.125 V

5 V

4.875 V

H (ns)

PU I

I P

025507585

LOAD (pF)

Figure 3. Positive Pulse Width at

25°C Ambient at 50 MHz Out

025507585

LOAD (pF)

Figure 2. Negative Pulse Width @ 50 MHz

Out and 25°C Ambient

4.875 V

5 V

5.125 V

NEGATIVE PULSE WIDTH (ns)

025507585

LOAD (pF)

Figure 4. Negative Pulse Width @ 50 MHz

Out and 25°C Ambient

50 pF

H (ns)

PU I

I P

0° 25° 50° 75° 85°

TEMPERATURE (°C)

25 pF

10 pF

Figure 5. T emperature versus Positive Pulse W idth

for 100H640 at 50 MHz and +5.0 V V

DL122 — Rev 6

10 pF

NEGATIVE PULSE WIDTH (ns)

0°

25°

TEMPERATURE (°C)

25 pF

50° 75° 85°

Figure 6. T emperature versus Negative Pulse W idth

for MC100H640 @ 50 MHz and +5.0 V V

2–5 MOTOROLAMECL Data

Page 6

MC10H640 MC100H640

6.2

TP (ns)

D++

6.0

5.8

5.6

5.4

4.75 V 5 V

5.25 V

RESET, R

Q0, Q1, Q2, Q3

, Q1

Q4, Q5

5.2

50 75 85

(pF)

LOAD

Figure 7. TP versus Load T ypical at TA = 25°C

tpw

trec

Figure 8. MC10H/100H640 Clock Phase and Reset Recovery Time After Reset Pulse

Q0 Q

Q4 & Q

AFTER POWER UP OUTPUTS Q4 & Q5 WILL SYN WITH POSITIVE EDGES OF Din & Q0 Q3 & NEGATIVE EDGES OF Q

& Q

Figure 9. Output Timing Diagram

MOTOROLA MECL Data

2–6

DL122 — Rev 6

Page 7

OUTLINE DIMENSIONS

FN SUFFIX

PLASTIC PLCC PACKAGE

CASE 776–02

ISSUE D

MC10H640 MC100H640

–L–

–N–

28 1

0.010 (0.250) N

L–M

Y BRK

0.007 (0.180) N

–M–

0.010 (0.250) N

G1X

L–M

VIEW D–D

0.007 (0.180) N

L–M

0.007 (0.180) N

L–M

0.004 (0.100)

SEATING

–T–

PLANE

VIEW S

0.007 (0.180) N

L–M

NOTES:

1. DATUMS –L–, –M–, AND –N– DETERMINED WHERE TOP OF LEAD SHOULDER EXITS PLASTIC BODY AT MOLD PARTING LINE.

2. DIMENSION G1, TRUE POSITION TO BE MEASURED AT DATUM –T–, SEATING PLANE.

3. DIMENSIONS R AND U DO NOT INCLUDE MOLD FLASH. ALLOWABLE MOLD FLASH IS

0.010 (0.250) PER SIDE.

4. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982.

5. CONTROLLING DIMENSION: INCH.

6. THE PACKAGE TOP MAY BE SMALLER THAN THE PACKAGE BOTTOM BY UP TO 0.012 (0.300). DIMENSIONS R AND U ARE DETERMINED AT THE OUTERMOST EXTREMES OF THE PLASTIC BODY EXCLUSIVE OF MOLD FLASH, TIE BAR BURRS, GATE BURRS AND INTERLEAD FLASH, BUT INCLUDING ANY MISMATCH BETWEEN THE TOP AND BOTTOM OF THE PLASTIC BODY.

7. DIMENSION H DOES NOT INCLUDE DAMBAR PROTRUSION OR INTRUSION. THE DAMBAR PROTRUSION(S) SHALL NOT CAUSE THE H DIMENSION TO BE GREATER THAN 0.037 (0.940). THE DAMBAR INTRUSION(S) SHALL NOT CAUSE THE H DIMENSION TO BE SMALLER THAN 0.025 (0.635).

DIM MIN MAX MIN MAX

A 0.485 0.495 12.32 12.57 B 0.485 0.495 12.32 12.57 C 0.165 0.180 4.20 4.57 E 0.090 0.110 2.29 2.79 F 0.013 0.019 0.33 0.48 G 0.050 BSC 1.27 BSC H 0.026 0.032 0.66 0.81

J 0.020 ––– 0.51 ––– K 0.025 ––– 0.64 ––– R 0.450 0.456 11.43 11.58 U 0.450 0.456 11.43 11.58 V 0.042 0.048 1.07 1.21 W 0.042 0.048 1.07 1.21 X 0.042 0.056 1.07 1.42 Y ––– 0.020 ––– 0.50 Z 2 10 2 10

____

G1 0.410 0.430 10.42 10.92 K1 0.040 ––– 1.02 –––

MILLIMETERSINCHES

DL122 — Rev 6

2–7 MOTOROLAMECL Data

Page 8

MC10H640 MC100H640

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MOTOROLA MECL Data

2–8

*MC10H640/D*

◊

MC10H640/D

DL122 — Rev 6