The MC10EP56 is a dual, fully differential 2:1 multiplexer. The
differential data path makes the device ideal for multiplexing low
skew clock or other skew sensitive signals. Multiple VBB pins are
provided to ease AC coupling of input signals. If used, the VBB output
should be bypassed to ground with a 0.01µF capacitor .
The device features both individual and common select inputs to
address both data path and random logic applications.
• 350ps Typical Propagation Delays
• Typical Frequency 3.0GHz
• 20–Lead TSSOP Package
• PECL mode: 3.0V to 5.5V V
• ECL mode: 0V V
with VEE = –3.0V to –5.5V
CC
• Separate and Common Select
• Internal Input Resistors: Pulldown on D, D
• Q Output will default LOW with inputs open or at V
• ESD Protection: >4KV HBM, >200V MM
• V
BB
Outputs
• New Differential Input Common Mode Range
• Moisture Sensitivity Level 1, Indefinite Time Out of Drypack.
For Additional Information, See Application Note AND8003/D
• Flammability Rating: UL–94 code V–0 @ 1/8”,
Oxygen Index 28 to 34
• Transistor Count = 140 devices
Q0
VCCQ0
1920
SEL0SEL1 VCCQ1Q1V
17181615141312
with VEE = 0V
CC
COM_SEL
EE
EE
11
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20
1
TSSOP–20
DT SUFFIX
CASE 948E
MARKING DIAGRAM*
MC10
EP56
ALYW
*For additional information, see Application Note
AND8002/D
A = Assembly Location
L = Wafer Lot
Y = Y ear
W = Work Week
Figure 1. 20–Lead TSSOP (Top View) and Logic Diagram
This document contains information on a product under development. ON Semiconductor
reserves the right to change or discontinue this product without notice.
NOTE: 10EP circuits are designed to meet the DC specifications shown in the above table after thermal equilibrium has been established. The
1. VCC = 0V, VEE = V
2. All loading with 50 ohms to VCC–2.0 volts.
3. V
4. Input and output parameters vary 1:1 with VCC.
Power Supply Current
(Note 1.)
Output HIGH Voltage
(Note 2.)
Output LOW Voltage
(Note 2.)
Input HIGH Voltage
Single Ended
Input LOW Voltage
Single Ended
Output Voltage Reference–1510 –1410 –1310–1445 –1345 –1245 –1385–1285 –1185mV
Input HIGH Voltage Common Mode
Range (Note 3.)
Input HIGH Current150150150µA
Input LOW Current
circuit is in a test socket or mounted on a printed circuit board and transverse airflow greater than 500lfpm is maintained.
min varies 1:1 with VEE, max varies 1:1 with VCC.
IHCMR
Power Supply (VCC = 0V)–6.0 to 0VDC
Power Supply (VEE = 0V)6.0 to 0VDC
Input Voltage (VCC = 0V, VI not more negative than VEE)–6.0 to 0VDC
Input Voltage (VEE = 0V, VI not more positive than VCC)6.0 to 0VDC
Output CurrentContinuous
VBB Sink/Source Current
Operating Temperature Range–40 to +85°C
Storage Temperature–65 to +150°C
Thermal Resistance (Junction–to–Ambient)Still Air
Thermal Resistance (Junction–to–Case)23 to 41 ± 5%°C/W
Solder Temperature (<2 to 3 Seconds: 245°C desired)265°C
14.Within–Device Skew is defined as identical transitions on similar paths through a device.
15.Skew is measured between outputs under identical transitions. Duty cycle skew is defined only for differential operation when the delays
are measured from the cross point of the inputs to the cross point of the outputs.
Cycle–to–Cycle JitterTBDTBDTBDps
Input Voltage Swing (Diff.)150800120015080012001508001200mV
Output Rise/Fall TimesQ, Q
(20% – 80%)
guaranteed for functionality only.
max
D–>Q, Q
D–>Q, Q
COM_SEL–>Q, Q
(Diff)
(SE)
SEL–>Q, Q
250
250
200
200
100150200100150200100160220ps
340
340
340
350
TBD
TBD
480
480
550
580
250
250
200
200
3.0GHz
360
360
340
360
TBD
TBD
480
480
550
580
0V)
300
300
200
200
400
400
390
400
TBD
TBD
ps
520
520
650
675
ps
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4
Page 5
MC10EP56
P ACKAGE DIMENSIONS
TSSOP–20
DT SUFFIX
20 PIN PLASTIC TSSOP PACKAGE
CASE 948E–02
ISSUE A
L
U0.15 (0.006) T
2X
L/2
PIN 1
IDENT
U0.15 (0.006) T
C
0.100 (0.004)
–T–
20X REFK
S
0.10 (0.004)V
M
S
U
T
1120
B
–U–
110
S
A
–V–
G
H
SEATING
PLANE
D
S
JJ1
N
N
DETAIL E
K
K1
SECTION N–N
0.25 (0.010)
M
F
DETAIL E
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSION A DOES NOT INCLUDE MOLD
FLASH, PROTRUSIONS OR GATE BURRS. MOLD
FLASH OR GATE BURRS SHALL NOT EXCEED
0.15 (0.006) PER SIDE.
4. DIMENSION B DOES NOT INCLUDE
INTERLEAD FLASH OR PROTRUSION.
INTERLEAD FLASH OR PROTRUSION SHALL NOT
EXCEED 0.25 (0.010) PER SIDE.
5. DIMENSION K DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.08 (0.003) TOTAL IN
EXCESS OF THE K DIMENSION AT MAXIMUM
MATERIAL CONDITION.
6. TERMINAL NUMBERS ARE SHOWN FOR
REFERENCE ONLY.
7. DIMENSION A AND B ARE TO BE
DETERMINED AT DATUM PLANE –W–.
ON Semiconductor and are trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes
without further notice to any products herein. SCILLC makes no warranty , representation or guarantee regarding the suitability of its products for any particular
purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability ,
including without limitation special, consequential or incidental damages. “Typical” parameters which may be provided in SCILLC data sheets and/or
specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be
validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights nor the rights of others.
SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications
intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or
death may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold
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attorney fees arising out of, directly or indirectly , any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim
alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer .
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MC10EP56/D
8
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