Page 1
SEMICONDUCTOR
TECHNICAL DATA
TV AND VCR
PLL TUNING CIRCUIT
WITH 1.3 GHz PRESCALER
AND I2C BUS
PIN CONNECTIONS
Order this document by MC44818/D
116
15
14
13
12
11
10
9
2
3
4
5
6
7
8
SDA
SCL
XTAL
V
CC2
33 V
V
CC1
5.0 V
HF In
AS
Gnd
D SUFFIX
PLASTIC PACKAGE
CASE 751B
(SO–16)
16
1
Amp In
V
TUN
Lock
V
CC3
12 V
B
3
B
2
B
1
B
0
(Top View)
1
MOTOROLA ANALOG IC DEVICE DATA
The MC44818 is a tuning circuit for TV and VCR tuner applications. It
contains, on one chip, all the functions required for PLL control of a VCO.
This integrated circuit also contains a high frequency prescaler and thus can
handle frequencies up to 1.3 GHz. The MC44818 is a pin compatible drop in
replacement for the MC44817, where the only difference is the MC44818
has a fixed divide–by–8 prescaler (cannot be bypassed) and the MC44817
uses the three wire bus.
The MC44818 has a programmable 512/1024 reference divider and is
manufactured on a single silicon chip using Motorola’s high density bipolar
process, MOSAIC (Motorola Oxide Self Aligned Implanted Circuits).
• Complete Single Chip System for MPU Control (I
2
C Bus). Data and
Clock Inputs are 3–Wire Bus Compatible
• Divide–by–8 Prescaler Accepts Frequencies up to 1.3 GHz
• 15 Bit Programmable Divider Accepts Input Frequencies up to 165 MHz
• Reference Divider: Programmable for Division Ratios 512 and 1024.
• 3–State Phase/Frequency Comparator
• Operational Amplifier for Direct Tuning Voltage Output (30 V)
• Four Integrated PNP Band Buffers for 40 mA (V
CC1
to 14.4 V)
• Output Options for the Reference Frequency and the
Programmable Divider
• High Sensitivity Preamplifier
• Circuit to Detect Phase Lock
• Fully ESD Protected
MOSAIC is a trademark of Motorola, Inc.
ORDERING INFORMATION
Device
Operating
Temperature Range
Package
MC44818D TA = –20° to +80°C SO–16
Motorola, Inc. 1996 Rev 2
Page 2
MC44818
2
MOTOROLA ANALOG IC DEVICE DATA
Representative Block Diagram
This device contains 3,204 active transistors.
Gnd
Test
Logic
Buffers
Latches
P–On
Reset
I2C Bus
Receiver
Latches
Phase
Comp
Ref
Divider
Osc
Latch Control
Program Divider
15 Bit
Latches B
Latches A
Shift Register
15 Bit
÷
8
Prescaler
DTB2
POR
Operational
Amplifier
2.7 V
20 k
DTB1
CL
Data
RL
DTF
F
out
TDI
F
out
F
ref
T10, T
11
T9, T12, T
14
T
13
4
6
15
10111213 14 5 675.0 V
F
out
F
ref
9
16
1
2
8
AS
Data
Clock
HF Input
V
CC1
V
CC3
V
TUN
V
CC2
Bands Out 30 mA
(40 mA at 0
°
to 80°C)
Amp In
Lock
XTAL
B3B2B1B
0
DTS, EN
512/1024
4
15
3
12 V
MAXIMUM RATINGS (T
A
= 25°C, unless otherwise noted.)
Rating Pin Value Unit
Power Supply Voltage (V
CC1
) 7 6.0 V
Band Buffer “Off” Voltage 10–13 14.4 V
Band Buffer “On” Current 10–13 50 mA
Band Buffer – Short Circuit Duration (0 to V
CC3
) (Note 2) 10–13 Continuous –
Operational Amplifier Power Supply Voltage (V
CC2
) 6 40 V
Operational Amplifier Short Circuit Duration (0 to V
CC2
) 5 Continuous –
Power Supply Voltage (V
CC3
) 14 14.4 V
Storage Temperature – –65 to +150 °C
Operating Temperature Range – –20 to +80 °C
Band Buffer Operation (Note 1) at 50 mA each Buffer All
Buffers “On” Simultaneously
10–13 10 sec
Operational Amplifier Output Voltage 5 V
CC2
V
RF Input Level (10 MHz to 1.3 GHz) – 1.5 Vrms
NOTES: 1. At V
CC3
= V
CC1
to 14.4 V and TA = –20° to +80°C.
2.At V
CC3
= V
CC1
to 14.4 V and TA = –20° to +80°C one buffer “On” only .
Page 3
MC44818
3
MOTOROLA ANALOG IC DEVICE DATA
ELECTRICAL CHARACTERISTICS (V
CC1
= 5.0 V , V
CC2
= 33 V, V
CC3
= 12 V, TA = 25°C, unless otherwise noted.)
Characteristic
Pin Min Typ Max Unit
V
CC1
Supply Voltage Range 7 4.5 5.0 5.5 V
V
CC1
Supply Current (V
CC1
= 5.0 V) 7 – 37 50 mA
V
CC2
Supply Voltage Range 6 25 – 37 V
V
CC2
Supply Current (Output Open) 6 – 1.5 2.3 mA
Band Buffer Leakage Current when “Off” at 12 V 10–13 – 0.01 1.0 µA
Band Buffer Saturation Voltage when “On” at 30 mA 10–13 – 0.15 0.3 V
Band Buffer Saturation Voltage when “On” at 40 mA
only for 0° to 80°C
10–13 – 0.2 0.5 V
Data/Clock Current at 0 V 1, 2 –10 – 0 µA
Clock Current at 5.0 V 2 0 – 1.0 µA
Data Current at 5.0 V Acknowledge “Off” 1 0 – 1.0 µA
Data Saturation Voltage at 15 mA Acknowledge “On” 1 – – 1.0 V
Data/Clock Input Voltage Low 1, 2 – – 1.5 V
Data/Clock Input Voltage High 1, 2 3.0 – – V
Clock Frequency Range 2 – – 100 kHz
Oscillator Frequency Range 3 3.15 3.2 4.05 MHz
Operational Amplifier Internal Reference Voltage – 2.0 2.75 3.2 V
Operational Amplifier Input Current 4 –15 0 15 nA
DC Open Loop Voltage Gain – 100 250 – V/V
Gain Bandwidth Product (CL = 1.0 nF) – 0.3 – – MHz
V
out
Low, Sinking 50 µA 5 – 0.2 0.4 V
V
out
High, Sourcing 10 µA, V
CC2
– V
out
5 – 0.2 0.5 V
Phase Detector Current in the High Impedance State 4 –15 0 15 nA
Charge Pump High Current of Phase Comparator 4 30 50 85 µA
Charge Pump Low Current of Phase Comparator 4 10 15 30 µA
V
CC3
Supply Voltage Range 14 V
CC1
– 14.4 V
V
CC3
Supply Current 14 mA
All Buffers “Off” – 0.2 0.5
One Buffer “On” when Open – 8.0 13
One Buffer “On” at 40 mA – 48 53
Data Format and Bus Receiver
The circuit receives the information for tuning and control
via the I2C bus. The incoming information, consisting of a
chip address byte followed by two or four data bytes, is
treated in the I2C bus receiver. The definition of the
permissible bus protocol is shown below:
1_ST A CA CO BA STO
2_ST A CA FM FL STO
3_ST A CA CO BA FM FL STO
4_ST A CA FM FL CO BA STO
STA = Start Condition
STO = Stop Condition
CA = Chip Address Byte
CO = Data Byte for Control Information
BA = Band Information
FM = Data Byte for Frequency Information
FL = Data Byte for Frequency Information
Figure 1. Complete Data Transfer Process
SDA
SCL
S P
1–7 8 9 1–7 8 9 1–7 8 9
STA ADDRESSCAR/W ACK DATA ACK DATA ACK STO
Page 4
MC44818
4
MOTOROLA ANALOG IC DEVICE DATA
Figure 2 shows the five bytes of information that are
needed for circuit operation: there is the chip address, two
bytes of control and band information and two bytes of
frequency information.
After the chip address, two or four data bytes may be
received: if three data bytes are received the third data byte
is ignored.
If five or more data bytes are received the fifth and
following data bytes are ignored and the last acknowledge
pulse is sent at the end of the fourth data byte.
The first and the third data bytes contain a function bit
which allows the IC to distinguish between frequency
information and control plus band information.
Frequency information is preceeded by a Logic “0”. If the
function bit is Logic “1” the two following bytes contain control
and band information. The first data byte, shifted after the
chip address, may be byte CO or byte FM.
The two permissible bus protocols with five bytes are
shown in Figure 2.
Figure 2. Definition of Bytes
CA_Chip Address 1 1 0 0 0 0/1 0/1 0 ACK
CO_Information
1
T
14
T
13
T
12
T
11
T
10
T
9
T
8
ACK
BA_Band Information X X X X B
3
B
2
B
1
B
0
ACK
FM_Frequency Information
0
N
14
N
13
N
12
N
11
N
10
N
9
N
8
ACK
FL_Frequency Information N
7
N
6
N
5
N
4
N
3
N
2
N
1
N
0
ACK
CA_Chip Address 1 1 0 0 0 0/1 0/1 0 ACK
FM_Frequency Information
0
N
14
N
13
N
12
N
11
N
10
N
9
N
8
ACK
FL_Frequency Information N
7
N
6
N
5
N
4
N
3
N
2
N
1
N
0
ACK
ЙЙЙЙЙЙЙЙЙЙЙЙЙЙЙЙЙЙЙЙЙ
É
CO_Information
1
T
14
T
13
T
12
T
11
T
10
T
9
T
8
ACK
BA_Band Information X X X X B
3
B
2
B
1
B
0
ACK
Chip Address
The chip address is programmable by Pin 16 (AS –
Address Select).
AS – Pin 16 Address (HEX.)
Gnd to 0.1 V
CC1
C0
Open or 0.2 V
CC1
to 0.3 V
CC1
C2
0.4 V
CC1
to 0.7 V
CC1
C4
0.8 V
CC1
to 1.1 V
CC1
C6
Bits B0, B1, B2, B3: Control the Band Buffers
B0, B1, B2, B3 = 0
B0, B1, B2, B3 = 1
Buffer “Off”
Buffer “On”
Figure 3. Equivalent Circuit of the Integrated
Band Buffers
“On”/“Off”
I
SUB
30 mA (40 mA
at 0 to 80
°
C)
V
CC3
12 V
25 V
Protection
I
B
Out
B
0
…
B
3
NOTE:
IB + I
SUB
= 8.0 mA Typical, 13 mA Max
IB = Base Current
I
SUB
= Substrate Current of PNP
Gnd
Bit T8: Controls the Output of the Operational Amplifier
T8 = 0
T8 = 1
Normal Operation
Operational Amplifier Active
Output State of Operational Amplifier Switched “Off”,
Output Pulls High Through 20 k Internal Pull–Up
Resistor
Bits T9, T12: Control the Phase Comparator
T
9
T
12
Function
1
1
0
0
0
1
0
1
Normal Operation
High Impedance
Upper Source “On” Only
Lower Source “On” Only
Bits T10, T11: Control the Reference Ratio
T
10
T
11
Division Ratio
0
0
1
1
0
1
0
1
512
1024
1024
512
Bit T13: Switches the Internal Signals F
ref
and F
BY2
to
Bit T13: the Band Buffer Outputs (Test)
T13 = 0
T13 = 1
Normal Operation
Test Mode
F
ref
Output at B2 (Pin 12)
F
BY2
Output at B3 (Pin 13)
Bits B2 and B3 have to be “On”, B2 = B3 = 1 in the test mode.
F
ref
is the reference frequency.
F
BY2
is the output frequency of the programmable divider, divided by two.
Page 5
MC44818
5
MOTOROLA ANALOG IC DEVICE DATA
Bit T14: Controls the Charge Pump Current of the
Bit T14: Phase Comparator
T14 = 0
T13 = 1
Pump Current 15 µA Typical
Pump Current 50 µA Typical
The Programmable Divider
The programmable divider is a presettable down counter.
When it has counted to zero it takes its required division ratio
out of the latches B. Latches B are loaded from latches A by
means of signal TDI which is synchronous to the
programmable divider output signal.
Since latches A receive the data asynchronously with the
programmable divider; this double latch scheme is needed to
assure correct data transfer to the counter.
The division ratio definition is given by:
N = 16384 x N14 + 8192 x N13 + … + 4 x N2 + 2 x N1 + N
0
Maximum Ratio 32767
Minimum Ratio 17
N0 … N14 are the different bits for frequency information.
At power “on” the whole bus receiver is reset and the
programmable divider is set to a counting ratio of N = 256 or
higher.
The Prescaler
The prescaler has a preamplifier which guarantees high
input sensitivity.
The Phase Comparator
The phase comparator is phase and frequency sensitive
and has very low output leakage current in the high
impedance state.
Lock Detector
The lock detector output is low in lock. The output goes
immediately high when an unlock condition is detected. The
output goes low again when the loop is in lock during a
complete period of the reference frequency.
Figure 4. Equivalent Circuit of the Lock Output
2.0 k
25 V Protection
Lock
V
CC1
5.0 V
100 k
200
µ
A Typical
The Operational Amplifier
The operational amplifier is designed for very low noise,
low input bias current and high power supply rejection. The
positive input is biased internally. The operational amplifier
needs 28.5 V supply (V
CC2)
as minimum voltage for a
guaranteed maximum tuning voltage of 28 V.
Figure NO TAG shows a possible filter arrangement. The
component values depend very much on the application
(tuner characteristic, reference frequency, etc.).
The Oscillator
The oscillator uses a 3.2 to 4.0 MHz crystal tied to ground in
series with a capacitor. The crystal operates in the series
resonance mode.
The voltage at Pin 3 has low amplitude and low harmonic
distortion.
1.0 nF
÷
8
Pres
Figure 5. Typical Tuner Application
111213 10
B3B2B1B
0
12 pF
3.2/4.0 MHz
Gnd
9
65 4 15
B III
VHF
UHF
AGC
V
TUN
33 V
Phase
Comp
Program
Divider
Lock
2.7 V
Mixer
B. P. Filter
Antenna
Filter
Oscillator
IF
7
5.0 V
2
1
16
3
Osc &
Ref Div
F
osc
SCL
SDA
AS
V
CC3
14 12 V
Bus
Rec
22 nF
47 k
(Note 1)
(Note 2)
330 p
47 nF
NOTES: 1. On some layouts the 100 Ω resistor will not be required.
2.C2 = 330 pF minimum is required for stability.
External Switching
MC44818
8
Page 6
MC44818
6
MOTOROLA ANALOG IC DEVICE DATA
Figure 6. HF Sensitivity Test Circuit
Device is in test mode. B2, B3 are “On” and B0, B1 are “Off”.
Sensitivity is level of HF generator on 50 Ω load (without Pin 8 loading).
12 14
HF8Gnd9B
0
10
B
1
11
B
2
12
B
3
13
Bus Controller
HF Generator
HF Out Gnd
7V
CC1
Frequency
Counter
In
V
CC3
Bus
390
Ω
390
Ω
4.7 k 4.7 k
50
Ω
50 Ω Cable
1.0 nF
MC44818
HF CHARACTERISTICS (See Figure NO T AG)
Characteristic
Pin Min Typ Max Unit
DC Bias 8 – 1.6 – V
Input Voltage Range mVrms
80–150 MHz 8 10 – 315
150–600 MHz 8 5.0 – 315
600–950 MHz 8 10 – 315
950–1300 MHz 8 50 – 315
500 MHz
1.3 GHz
–j +j
2
0.5
1
0.5
1
2
0.5
1
2
Figure 7. Typical HF Input Impedance
ZO = 50
Ω
1.0 GHz
50 MHz
0
Page 7
MC44818
7
MOTOROLA ANALOG IC DEVICE DATA
Figure 8. Pin Circuit Schematic
50
132 k
V
CC1
96 k
96 k
1/2 V
CC1
V
CC1
96 k
96 k
1/2 V
CC1
20 V
500
132 k
20 V
V
CC1
150 k
50 k
500
20 V
5.0 V
100
2.0 k
10 k
20 V
20 V
20 V
100
20 k
20 V
20 V
5.0 V
5.0 V
18 k
2.0 k
2.0 k
1.2
…
1.8 V
“On”/“Off”
“On”/“Off”
“On”/“Off”
“On”/“Off”
2.0 k
20 V
20 V
20 V
20 V
20 V
20 V
16 AS
Address Select
(I2C bus)
15 LOCK
Lock detector output
14 V
CC3
Positive supply for integrated
band buffers (12 V)
13 B
3
12 B
2
11 B
1
10 B
0
9 GND
Circuit Ground
SDA 1
Data input
(I2C bus)
SCL 2
Clock input (supplied
by a microprocessor
via I2C bus)
XTAL 3
Crystal oscillator
(3.2 MHz or 4.0 MHz)
AMP IN 4
Negative input of
operation amplifier and
charge pump output
V
TUN
5
Operational amplifier
output which provides
the tuning voltage
V
CC2
6
Operational amplifier
positive supply (33 V)
V
CC1
7
Positive supply of
the circuit (5.0 V)
HF IN 8
HF input from
local oscillator
V
CC1
100 k
Band buffer outputs
can drive up to 30 mA
(40 mA at 0
°
to 80°C
)
ACK
Page 8
MC44818
8
MOTOROLA ANALOG IC DEVICE DATA
D SUFFIX
PLASTIC PACKAGE
CASE 751B–05
(SO–16)
ISSUE J
0.25 (0.010) T B A
M
S S
MIN MINMAX MAX
MILLIMETERS INCHES
DIM
A
B
C
D
F
G
J
K
M
P
R
9.80
3.80
1.35
0.35
0.40
0.19
0.10
0
°
5.80
0.25
10.00
4.00
1.75
0.49
1.25
0.25
0.25
7
°
6.20
0.50
0.386
0.150
0.054
0.014
0.016
0.008
0.004
0
°
0.229
0.010
0.393
0.157
0.068
0.019
0.049
0.009
0.009
7
°
0.244
0.019
1.27 BSC 0.050 BSC
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSIONS A AND B DO NOT INCLUDE
MOLD PROTRUSION.
4. MAXIMUM MOLD PROTRUSION 0.15 (0.006)
PER SIDE.
5. DIMENSION D DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.127 (0.005) TOTAL
IN EXCESS OF THE D DIMENSION AT
MAXIMUM MATERIAL CONDITION.
1
8
916
–A–
–B–
D
16 PL
K
C
G
–T–
SEATING
PLANE
R X 45°
M
J
F
P 8 PL
0.25 (0.010) B
M M
OUTLINE DIMENSIONS
Motorola reserves the right to make changes without further notice to any products herein. Motorola makes no warranty , representation or guarantee regarding
the suitability of its products for any particular purpose, nor does Motorola assume any liability arising out of the application or use of any product or circuit, and
specifically disclaims any and all liability, including without limitation consequential or incidental damages. “T ypical” parameters which may be provided in Motorola
data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals”
must be validated for each customer application by customer’s technical experts. Motorola does not convey any license under its patent rights nor the rights of
others. Motorola products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other
applications intended to support or sustain life, or for any other application in which the failure of the Motorola product could create a situation where personal injury
or death may occur. Should Buyer purchase or use Motorola products for any such unintended or unauthorized application, Buyer shall indemnify and hold Motorola
and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees
arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that
Motorola was negligent regarding the design or manufacture of the part. Motorola and are registered trademarks of Motorola, Inc. Motorola, Inc. is an Equal
Opportunity/Affirmative Action Employer.
How to reach us:
USA/EUROPE/Locations Not Listed: Motorola Literature Distribution; JAP AN: Nippon Motorola Ltd.; Tatsumi–SPD–JLDC, 6F Seibu–Butsuryu–Center,
P.O. Box 20912; Phoenix, Arizona 85036. 1–800–441–2447 or 602–303–5454 3–14–2 Ta tsumi Koto–Ku, Tokyo 135, Japan. 03–81–3521–8315
MFAX: RMF AX0@email.sps.mot.com – TOUCHT ONE 602–244–6609 ASIA/PACIFIC: Motorola Semiconductors H.K. Ltd.; 8B Tai Ping Industrial Park,
INTERNET: http://Design–NET .com 51 Ting Ko k Road, Tai Po, N.T., Hong Kong. 852–26629298
MC44818/D
*MC44818/D*
◊
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