Datasheet MC10192P Datasheet (Motorola)



SEMICONDUCTOR TECHNICAL DATA

  

The MC10192 contains four line drivers with complementary outputs. Each

driver has a Data (D) input and shares an Enable

(E) input with another driver.
The two driver outputs are the uncommitted collectors of a pair of NPN
transistors operating as a current switch. Each driver accepts 10K MECL input
signals and provides a nominal signal swing of 800 mV across a 50 Ω load at
each output collector. Outputs can drive higher values of load resistance,
provided that the combination of IR drop and load return voltage VLR does not
cause an output collector to go more negative than –2.4 V with respect to VCC.
To avoid output transistor breakdown, the load return voltage should not be
more positive than +5.5 V with respect to VCC. When the E
output transistors of a driver are nonconducting. When not used, the E

input is high, both

inputs,

as well as the D inputs, may be left open.

Open Collector Outputs Drive Terminated Lines or

Transformers

50 kΩ Input Pulldown Resistors on All Inputs (Unused

Inputs May Be Left Open)
Power Dissipation = 575 mW typ/pkg (No Load)
Propagation Delay= 3.5 ns typ (E

— Output)

3.0 ns typ (D — Output)

LOGIC DIAGRAM

7

E1

D1

D2

D3

D4

5

6

10

11

3

4

1

2

14

13

15

Z1

Z1

Z2

Z2

Z3

Z3

Z4



CERAMIC PACKAGE

CASE 620–10

PLASTIC PACKAGE

CASE 648–08

CASE 775–02

DIP

PIN ASSIGNMENT

Z2
Z2
Z1

Z1
D1
D2
E1

V

EE

1
2
3
4
5
6
7
8

L SUFFIX

P SUFFIX

FN SUFFIX

PLCC

16
15
14
13
12
11
10

9

V
Z3
Z3
Z4
Z4
D4
D3
E2

CC

E2

3/93

 Motorola, Inc. 1996

9

TRUTH TABLE

Inputs

E D Z Z

H X H H
L H H L
L L L H

Note: Unused outputs must be terminated
to VCC for proper operation.

Output

3–160

12

Z4

VCC= PIN 16

VEE= PIN 8

Pin assignment is for Dual–in–Line Package.

For PLCC pin assignment, see the Pin Conversion

T ables on page 6–11 of the Motorola MECL Data

Book (DL122/D).

REV 5

MC10192

Under

Und

(VCC)

ELECTRICAL CHARACTERISTICS

Test Limits

Pin

Characteristic Symbol

Power Supply Drain Current I
Input Current I

Output Current High Logic 1 I
Output Current Low Logic 0 I
Threshold Current High Logic 1 I
Threshold Current Low Logic 0 I
Output Sink Current Low Logic 0 I
Load Return Voltage Absolute Max

Rating (Note 1.)
Output Voltage Low (Note 2.) V
Switching Times (50Ω Load) ns
Propagation Delay E to Output

D to Output

Rise/Fall Time (20 to 80%) t

1. The 5.5V value is a maximum rating, do not exceed. A 270Ω resistor will prevent output transistor breakdown.

2. Limitations of load resistor and load return voltage combinations. Refer to page 3–160 description.

E

inH

I

inL

OH

OL

OHC

OLC

OS

V

LR

OLS

t

PHL

t

PLH

TLH

t

THL

Under

Test

8 154 140 154 mAdc
5 350 220 220 µAdc
5 0.5 0.5 0.3 µAdc
2 2.0 mAdc
2 13.5 18.0 14.0 18.0 14.0 19.0 mAdc
2 2.0 2.0 2.0 mAdc
2 13.5 14.0 14.0 mAdc
2 13.3 13.9 13.3 mAdc

–30°C +25°C +85°C

Min Max Min Max Min Max

5.5 5.5 5.5 V

–2.4 V

2.0

1.5

6.0

4.5

3.3

Unit

ELECTRICAL CHARACTERISTICS (continued)

TEST VOLTAGE VALUES (Volts)

@ Test Temperature V

–30°C –0.890 –1.890 –1.205 –1.500 –5.2
+25°C –0.810 –1.850 –1.105 –1.475 –5.2
+85°C –0.700 –1.825 –1.035 –1.440 –5.2

Pin

Characteristic Symbol

Power Supply Drain Current I
Input Current I

Output Current High Logic 1 I
Output Current Low Logic 0 I
Threshold Current High Logic 1 I
Threshold Current Low Logic 0 I
Output Sink Current Low Logic 0 I
Load Return Voltage Absolute Max

Rating (Note 1.)
Output Voltage Low (Note 2.) V

Each MECL 10,000 series circuit has been designed to meet the dc specifications shown in the test table, after thermal equilibrium has been
established. The circuit is in a test socket or mounted on a printed circuit board and transverse air flow greater than 500 linear fpm is maintained.
Outputs are terminated through a 50–ohm resistor to –2.0 volts. Test procedures are shown for only one gate. The other gates are tested in the
same manner.

E

inH

I

inL

OH

OL

OHC

OLC

OS

V

LR

OLS

Test

8 8 16
5 5 8 16
5 5 8 16
2 5,6,10,1 1 8 16
2 5,6,10,11 8 16
2 5,7,9,10,1 1 6 8 16

2 5,6,10,11 8 16

IHmax

er

TEST VOLTAGE APPLIED TO PINS LISTED BELOW

V

IHmax

5,10,1 1 7,9 6 8 16

V

ILmin

V

ILmin

V

IHAminVILAmax

V

IHAminVILAmax

V

EE

V

EE

8 16

8 16

Gnd

DL122 — Rev 6

3–161 MOTOROLAMECL Data

MC10192

OUTLINE DIMENSIONS

FN SUFFIX

PLASTIC PLCC PACKAGE

CASE 775–02

ISSUE C

–L–

20 1

Z

C

G

G1

0.010 (0.250) N

S

T

–N–

L–M

Y BRK

–M–

W

V

A

0.007 (0.180) N

0.007 (0.180) N

R

E

0.004 (0.100)

–T–

J

VIEW S

S

S

D

D

M

M

SEATING
PLANE

0.007 (0.180) N

B

0.007 (0.180) N

U

M

S

L–M

T

M

S

S

L–M

T

S

Z

0.010 (0.250) N

X

G1

S

S

L–M

T

S

VIEW D–D

S

L–M

T

L–M

T

S

S

S

0.007 (0.180) N

H

M

S

L–M

T

S

K1

K

0.007 (0.180) N

F

M

S

L–M

T

S

VIEW S

NOTES:

1. DATUMS –L–, –M–, AND –N– DETERMINED
WHERE TOP OF LEAD SHOULDER EXITS PLASTIC
BODY AT MOLD PARTING LINE.

2. DIMENSION G1, TRUE POSITION TO BE
MEASURED AT DA TUM –T–, SEATING PLANE.

3. DIMENSIONS R AND U DO NOT INCLUDE MOLD
FLASH. ALLOWABLE MOLD FLASH IS 0.010 (0.250)
PER SIDE.

4. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.

5. CONTROLLING DIMENSION: INCH.

6. THE PACKAGE TOP MAY BE SMALLER THAN THE
PACKAGE BOTTOM BY UP TO 0.012 (0.300).
DIMENSIONS R AND U ARE DETERMINED AT THE
OUTERMOST EXTREMES OF THE PLASTIC BODY
EXCLUSIVE OF MOLD FLASH, TIE BAR BURRS,
GATE BURRS AND INTERLEAD FLASH, BUT
INCLUDING ANY MISMATCH BETWEEN THE TOP
AND BOTTOM OF THE PLASTIC BODY.

7. DIMENSION H DOES NOT INCLUDE DAMBAR
PROTRUSION OR INTRUSION. THE DAMBAR
PROTRUSION(S) SHALL NOT CAUSE THE H
DIMENSION TO BE GREATER THAN 0.037 (0.940).
THE DAMBAR INTRUSION(S) SHALL NOT CAUSE
THE H DIMENSION TO BE SMALLER THAN 0.025
(0.635).

MOTOROLA MECL Data

DIM MIN MAX MIN MAX

A 0.385 0.395 9.78 10.03
B 0.385 0.395 9.78 10.03
C 0.165 0.180 4.20 4.57
E 0.090 0.110 2.29 2.79
F 0.013 0.019 0.33 0.48
G 0.050 BSC 1.27 BSC
H 0.026 0.032 0.66 0.81
J 0.020 ––– 0.51 –––
K 0.025 ––– 0.64 –––
R 0.350 0.356 8.89 9.04
U 0.350 0.356 8.89 9.04
V 0.042 0.048 1.07 1.21
W 0.042 0.048 1.07 1.21
X 0.042 0.056 1.07 1.42
Y ––– 0.020 ––– 0.50
Z 2 10 2 10

____

G1 0.310 0.330 7.88 8.38
K1 0.040 ––– 1.02 –––

3–162

MILLIMETERSINCHES

DL122 — Rev 6

OUTLINE DIMENSIONS

CERAMIC DIP PACKAGE

–A–

16 9

–B–

18

C

–T–

SEATING
PLANE

E

F

G

16 PLD

0.25 (0.010) T

M

–A–

916

B

18

F

C

S

H

G

D

16 PL

0.25 (0.010) T

K

M

K

N

S

A

PLASTIC DIP PACKAGE

SEATING

–T–

PLANE

M

A

L SUFFIX

CASE 620–10

ISSUE V

L

M

16 PLJ

0.25 (0.010) T

P SUFFIX

CASE 648–08

ISSUE R

L

J

MC10192

NOTES:

1. DIMENSIONING AND TOLERANCING PER
ANSI Y14.5M, 1982.

2. CONTROLLING DIMENSION: INCH.

3. DIMENSION L TO CENTER OF LEAD WHEN
FORMED PARALLEL.

4. DIMENSION F MAY NARROW TO 0.76 (0.030)
WHERE THE LEAD ENTERS THE CERAMIC
BODY.

DIM MIN MAX MIN MAX

A 0.750 0.785 19.05 19.93
B 0.240 0.295 6.10 7.49
C ––– 0.200 ––– 5.08
D 0.015 0.020 0.39 0.50
E 0.050 BSC 1.27 BSC
F 0.055 0.065 1.40 1.65
G 0.100 BSC 2.54 BSC
H 0.008 0.015 0.21 0.38
K 0.125 0.170 3.18 4.31

M

S

B

NOTES:

1. DIMENSIONING AND TOLERANCING PER ANSI

2. CONTROLLING DIMENSION: INCH.

3. DIMENSION L TO CENTER OF LEADS WHEN

4. DIMENSION B DOES NOT INCLUDE MOLD FLASH.

5. ROUNDED CORNERS OPTIONAL.

M

L 0.300 BSC 7.62 BSC
M 0 15 0 15

____

N 0.020 0.040 0.51 1.01

Y14.5M, 1982.

FORMED PARALLEL.

DIM MIN MAX MIN MAX

A 0.740 0.770 18.80 19.55
B 0.250 0.270 6.35 6.85
C 0.145 0.175 3.69 4.44
D 0.015 0.021 0.39 0.53
F 0.040 0.70 1.02 1.77
G 0.100 BSC 2.54 BSC
H 0.050 BSC 1.27 BSC
J 0.008 0.015 0.21 0.38
K 0.110 0.130 2.80 3.30
L 0.295 0.305 7.50 7.74
M 0 10 0 10
S 0.020 0.040 0.51 1.01

MILLIMETERSINCHES

MILLIMETERSINCHES

____

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specifically disclaims any and all liability, including without limitation consequential or incidental damages. “T ypical” parameters which may be provided in Motorola
data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals”
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MC10192/D

DL122 — Rev 6

◊

3–163 MOTOROLAMECL Data

*MC10192/D*