Datasheet MC10161L, MC10161FN Datasheet (Motorola)

Page 1

SEMICONDUCTOR TECHNICAL DATA
    
The MC10161 is designed to decode a three bit input word to a one of eight line output. The selected output will be low while all other outputs will be high. The enable inputs, when either or both are high, force all outputs high.
The MC10161 is a true parallel decoder. No series gating is used internally, eliminating unequal delay times found in other decoders. This design provides the identical 4 ns delay from any address or enable input to any output.
A complete mux/demux operation on 16 bits for data distribution is illustrated in Figure 1. This system, using the MC10136 control counters, has the capability of incrementing, decrementing or holding data channels. When both S0 and S1 are low, the index counters reset, thus initializing both the mux and demux units. The four binary outputs of the counter are buffered by the MC10101s to send twisted–pair select data to the multiplexer/demultiplexer to units.
PD= 315 mW typ/pkg (No Load) tpd= 4.0 ns typ
tr, tf= 2.0 ns typ (20%–80%)
LOGIC DIAGRAM
E0 2
E1
A7
B9
C14
15
6Q0
5Q1
4Q2
3Q3
13 Q4
12 Q5
11 Q6
10 Q7
V
= PIN 1
CC1
V
= PIN 16
CC2 VEE= PIN 8

L SUFFIX
CERAMIC PACKAGE
CASE 620–10
P SUFFIX
PLASTIC PACKAGE
CASE 648–08
FN SUFFIX
CASE 775–02
DIP
PIN ASSIGNMENT
1
V
CC1
E0 Q3 Q2 Q1 Q0
V
EE
A
16
2
15
3
14
4
13
5
12
6
11
7
10
8
9
PLCC
V E1 C Q4
Q5 Q6
Q7 B
CC2
ENABLE
INPUTS E1 E0 C B A Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7
L L L L L L H H H H H H H L L L L H H L H H H H H H L L L H L H H L H H H H H L L L H H H H H L H H H H L L H L L H H H H L H H H L L H L H H H H H H L H H L L H H L H H H H H H L H
L L H H H H H H H H H H L H X X X X H H H H H H H H X H X X X H H H H H H H H
3/93
Motorola, Inc. 1996
TRUTH TABLE
INPUTS OUTPUTS
3–73
Pin assignment is for Dual–in–Line Package.
For PLCC pin assignment, see the Pin Conversion
T ables on page 6–11 of the Motorola MECL Data
Book (DL122/D).
REV 5
Page 2
MC10161
Under
Und
(VCC)
ELECTRICAL CHARACTERISTICS
Test Limits
Pin
Characteristic Symbol
Power Supply Drain Current I Input Current I
Output Voltage Logic 1 V
Output Voltage Logic 0 V Threshold Voltage Logic 1 V
Threshold Voltage Logic 0 V Switching Times (50 Load) ns Propagation Delay t
Rise Time (20 to 80%) t Fall Time (20 to 80%) t
E
inH
I
inL
OH
OL
OHA
OLA
14+13–
t
14–13+
13+ 13–
Under
Test
8 84 61 76 84 mAdc 14 350 220 220 µAdc 14 0.5 0.5 0.3 µAdc 13
13 13 –1.890 –1.675 –1.850 –1.650 –1.825 –1.615 Vdc 13
13 13 –1.655 –1.630 –1.595 Vdc
13 13
13 1.0 3.3 1.1 2.0 3.3 1.1 3.5 13 1.0 3.3 1.1 2.0 3.3 1.1 3.5
–30°C +25°C +85°C
Min Max Min Typ Max Min Max
–1.060 –1.060
–1.080 –1.080
1.5
1.5
–0.890 –0.890
6.2
6.2
–0.960 –0.960
–0.980 –0.980
1.5
1.5
4.0
4.0
–0.810 –0.810
6.0
6.0
–0.890 –0.890
–0.910 –0.910
1.5
1.5
–0.700 –0.700
6.4
6.4
Unit
Vdc
Vdc
ELECTRICAL CHARACTERISTICS (continued)
TEST VOLTAGE VALUES (Volts)
@ Test Temperature V
–30°C –0.890 –1.890 –1.205 –1.500 –5.2 +25°C –0.810 –1.850 –1.105 –1.475 –5.2 +85°C –0.700 –1.825 –1.035 –1.440 –5.2
Pin
Characteristic Symbol
Power Supply Drain Current I Input Current I
Output Voltage Logic 1 V
Output Voltage Logic 0 V Threshold Voltage Logic 1 V
Threshold Voltage Logic 0 V Switching Times (50 Load) Pulse In Pulse Out –3.2 V +2.0 V Propagation Delay t
Rise Time (20 to 80%) t Fall Time (20 to 80%) t
Each MECL 10,000 series circuit has been designed to meet the dc specifications shown in the test table, after thermal equilibrium has been established. The circuit is in a test socket or mounted on a printed circuit board and transverse air flow greater than 500 linear fpm is maintained. Outputs are terminated through a 50–ohm resistor to –2.0 volts. Test procedures are shown for only one gate. The other gates are tested in the same manner.
E
inH
I
inL OH
OL
OHA
OLA
14+13–
t
14–13+
13+ 13–
er
Test
8 2,7,9,14,15 8 1,16 14 14 8 1,16 14 14 8 1,16 13
13 13 14 8 1,16 13
13 13 14 8 1,16
13 13
13 14 13 8 1,16 13 14 13 8 1,16
IHmax
TEST VOLTAGE APPLIED TO PINS LISTED BELOW
V
IHmax
2
15
V
ILmin
V
ILmin
V
IHAminVILAmax
V
IHAminVILAmax
2
15
14 14
13 13
V
EE
V
EE
8 8
8 8
8 8
Gnd
1,16 1,16
1,16 1,16
1,16 1,16
MOTOROLA MECL Data
3–74
DL122 — Rev 6
Page 3
FIGURE 1 — HIGH SPEED 16-BIT MULTIPLEXER/DEMULTIPLEXER
Control Selection
MC10101 MC10115
MC10161
S0 S1
MC10136
C
R ABCD
S0
S1
C
R
MC10101 MC10115
Start/Stop
S0 S1
MC10136
C
R
ABCD
15 14 13 12 11 10 9 8
1
E C
MC10164
B A
E
C B A
D0
E0
1
MC10161
15 141312 11 10 9 8
765432
E
1 C B A
E
1 C B A
76543210
MC10164
D0
E0
MC10161
1
0
DL122 — Rev 6
3–75 MOTOROLAMECL Data
Page 4
MC10161
OUTLINE DIMENSIONS
FN SUFFIX
PLASTIC PLCC PACKAGE
CASE 775–02
ISSUE C
–L–
20 1
Z
C
G
G1
0.010 (0.250) N
S
T
–N–
L–M
Y BRK
–M–
W
V
A
0.007 (0.180) N
0.007 (0.180) N
R
E
0.004 (0.100)
–T–
J
VIEW S
S
S
D
D
M
M
SEATING PLANE
0.007 (0.180) N
B
0.007 (0.180) N
U
M
S
L–M
T
M
S
S
L–M
T
S
Z
0.010 (0.250) N
X
G1
S
S
L–M
T
S
VIEW D–D
S
L–M
T
L–M
T
S
S
S
0.007 (0.180) N
H
M
S
L–M
T
S
K1
K
0.007 (0.180) N
F
M
S
L–M
T
S
VIEW S
NOTES:
1. DATUMS –L–, –M–, AND –N– DETERMINED WHERE TOP OF LEAD SHOULDER EXITS PLASTIC BODY AT MOLD PARTING LINE.
2. DIMENSION G1, TRUE POSITION TO BE MEASURED AT DA TUM –T–, SEATING PLANE.
3. DIMENSIONS R AND U DO NOT INCLUDE MOLD FLASH. ALLOWABLE MOLD FLASH IS 0.010 (0.250) PER SIDE.
4. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982.
5. CONTROLLING DIMENSION: INCH.
6. THE PACKAGE TOP MAY BE SMALLER THAN THE PACKAGE BOTTOM BY UP TO 0.012 (0.300). DIMENSIONS R AND U ARE DETERMINED AT THE OUTERMOST EXTREMES OF THE PLASTIC BODY EXCLUSIVE OF MOLD FLASH, TIE BAR BURRS, GATE BURRS AND INTERLEAD FLASH, BUT INCLUDING ANY MISMATCH BETWEEN THE TOP AND BOTTOM OF THE PLASTIC BODY.
7. DIMENSION H DOES NOT INCLUDE DAMBAR PROTRUSION OR INTRUSION. THE DAMBAR PROTRUSION(S) SHALL NOT CAUSE THE H DIMENSION TO BE GREATER THAN 0.037 (0.940). THE DAMBAR INTRUSION(S) SHALL NOT CAUSE THE H DIMENSION TO BE SMALLER THAN 0.025 (0.635).
MOTOROLA MECL Data
DIM MIN MAX MIN MAX
A 0.385 0.395 9.78 10.03 B 0.385 0.395 9.78 10.03 C 0.165 0.180 4.20 4.57 E 0.090 0.110 2.29 2.79
F 0.013 0.019 0.33 0.48 G 0.050 BSC 1.27 BSC H 0.026 0.032 0.66 0.81 J 0.020 ––– 0.51 ––– K 0.025 ––– 0.64 ––– R 0.350 0.356 8.89 9.04 U 0.350 0.356 8.89 9.04 V 0.042 0.048 1.07 1.21 W 0.042 0.048 1.07 1.21 X 0.042 0.056 1.07 1.42 Y ––– 0.020 ––– 0.50 Z 2 10 2 10
____
G1 0.310 0.330 7.88 8.38 K1 0.040 ––– 1.02 –––
3–76
MILLIMETERSINCHES
DL122 — Rev 6
Page 5
OUTLINE DIMENSIONS
CERAMIC DIP PACKAGE
–A–
16 9
–B–
18
C
–T–
SEATING PLANE
E
F
G
16 PLD
0.25 (0.010) T
M
–A–
916
B
18
F
C
S
H
G
D
16 PL
0.25 (0.010) T
K
M
K
N
S
A
PLASTIC DIP PACKAGE
SEATING
–T–
PLANE
M
A
L SUFFIX
CASE 620–10
ISSUE V
L
M
16 PLJ
0.25 (0.010) T
P SUFFIX
CASE 648–08
ISSUE R
L
J
MC10161
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982.
2. CONTROLLING DIMENSION: INCH.
3. DIMENSION L TO CENTER OF LEAD WHEN FORMED PARALLEL.
4. DIMENSION F MAY NARROW TO 0.76 (0.030) WHERE THE LEAD ENTERS THE CERAMIC BODY.
DIM MIN MAX MIN MAX
A 0.750 0.785 19.05 19.93 B 0.240 0.295 6.10 7.49 C ––– 0.200 ––– 5.08 D 0.015 0.020 0.39 0.50 E 0.050 BSC 1.27 BSC
F 0.055 0.065 1.40 1.65 G 0.100 BSC 2.54 BSC H 0.008 0.015 0.21 0.38 K 0.125 0.170 3.18 4.31
M
S
B
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
2. CONTROLLING DIMENSION: INCH.
3. DIMENSION L TO CENTER OF LEADS WHEN
4. DIMENSION B DOES NOT INCLUDE MOLD FLASH.
5. ROUNDED CORNERS OPTIONAL.
M
L 0.300 BSC 7.62 BSC M 0 15 0 15
____
N 0.020 0.040 0.51 1.01
Y14.5M, 1982.
FORMED PARALLEL.
DIM MIN MAX MIN MAX
A 0.740 0.770 18.80 19.55 B 0.250 0.270 6.35 6.85 C 0.145 0.175 3.69 4.44 D 0.015 0.021 0.39 0.53 F 0.040 0.70 1.02 1.77 G 0.100 BSC 2.54 BSC H 0.050 BSC 1.27 BSC J 0.008 0.015 0.21 0.38 K 0.110 0.130 2.80 3.30 L 0.295 0.305 7.50 7.74 M 0 10 0 10 S 0.020 0.040 0.51 1.01
MILLIMETERSINCHES
MILLIMETERSINCHES
____
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MC10161/D
DL122 — Rev 6
3–77 MOTOROLAMECL Data
*MC10161/D*
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