Datasheet MC10141P, MC10141FN, MC10141L Datasheet (Motorola)

Page 1

SEMICONDUCTOR TECHNICAL DATA
    
The MC10141 is a four–bit universal shift register which performs shift left, or shift right, serial/parallel in, and serial/parallel out operations with no external gating. Inputs S1 and S2 control the four possible operations of the register without external gating of the clock. The flip–flops shift information on the positive edge of the clock. The four operations are stop shift, shift left, shift right, and parallel entry of data. The other six inputs are all data type inputs; four for parallel entry data, and one for shifting in from the left (DL) and one for shifting in from the right (DR).
PD= 425 mW typ/pkg (No Load)
f
= 200 MHz typ
Shift tr, tf= 2.0 ns typ (20%–80%)
LOGIC DIAGRAM
D3
S1
1 of 4
Decoder
S2
DR
C
SELECT OUTPUTS S1 S2 OPERATING MODE Q0
L L Parallel Entry D0 D1 D2 D3
L H Shift Right* Q1 H L Shift Left* DL Q0 H H Stop Shift Q0
*Outputs as exist after pulse appears at “C” input with input conditions as
shown. (Pulse = Positive transition of clock input).
Parallel Enter
Shift Right
Shift Left
Hold
D2 D1 D0
Q
D C
Q3
Q
D C
Q2 Q1 Q0
TRUTH TABLE
Q1
n+1
Q2
n
Q1
n
n+1
n n n
Q
D C
V
CC1
V
CC2 VEE= PIN 8
Q2
n+1
Q3
n
Q1
n
Q2
n
D C
= PIN 1 = PIN 16
Q3
n+1
DR
Q2
n
Q3
n
DL
Q

L SUFFIX
CERAMIC PACKAGE
CASE 620–10
P SUFFIX
PLASTIC PACKAGE
CASE 648–08
FN SUFFIX
PLCC
CASE 775–02
DIP
PIN ASSIGNMENT
V
CC1
Q2 Q3
DR
D3
S2
V
EE
Pin assignment is for Dual–in–Line Package.
For PLCC pin assignment, see the Pin Conversion
T ables on page 6–11 of the Motorola MECL Data
C
1 2 3 4 5 6 7 8
Book (DL122/D).
16 15 14 13 12 11 10
V
CC2
Q1 Q0 DL D0 D1 S1 D2
9
3/93
Motorola, Inc. 1996
3–46
REV 5
Page 2
V
IN
COAX
INPUT
PULSE GENERAT OR
50–ohm termination to ground located in each scope channel input.
SHIFT FREQUENCY TEST CIRCUIT
V
= V
CC1
CC2
25 uF
C D0
D1 D2 D3 S1 S2
DR
DL
+2.0 VDC
16
1
Q0
Q1
Q2
Q3
8
0.1
0.1
µ
F
µ
F
V
OUT
MC10141
All input and output cables to the scope are equal lengths of 50–ohm coaxial cable. Wire length should be
Coax
TEST PROCEDURES:
1. SET D1, D2, D3 = +0.31 VDC (LOGIC L)
2. APPY CLOCK PULSE TO SET Q0 HIGH.
3. MAINTAIN CLOCK LOW. SET S1 = +0.31 VDC (LOGIC L)
4. TEST SHIFT FREQUENCY
< 1/4 inch from TPin to input pin and TP
to output pin.
out
D0 = +1.11 VDC (LOGIC H)
S2 = +1.11 VDC (LOGIC H)
V
IH
V
IL
VEE = –3.2VDC
DL122 — Rev 6
3–47 MOTOROLAMECL Data
Page 3
MC10141
Under
ELECTRICAL CHARACTERISTICS
Test Limits
Pin
Characteristic Symbol
Power Supply Drain Current I Input Current I
Output Voltage Logic 1 V Output Voltage Logic 0 V Threshold Voltage Logic 1 V
Threshold Voltage Logic 0 V
Switching Times (50 Load) ns Propagation Delay
Setup TIme (t
Hold Time (t Rise Time (20 to 80%) t Fall Time (20 to 80%) t Shift Frequency f
1. These tests to be performed in sequence as shown.
2. See shift frequency test circuit for test procedures.
3. Reset to zero before performing test.
4. Reset to one before performing test.
setup
hold
)
)
E
inH
I
inL
OH
OL
OHA
(Note 1.)
OLA
(Note 1.)
t
4+3+
t
12+4+
t
10+4+
t
4+12+
3+ 3–
shift
Under
Test
8 112 82 102 112 mAdc 5
6 7 4
12 0.5 0.5 0.3 µAdc
3 –1.060 –0.890 –0.960 –0.810 –0.890 –0.700 Vdc 3 –1.890 –1.675 –1.850 –1.650 –1.825 –1.615 Vdc 3
3 3 3
3 3 3 3
3 14 14 14
3 1.0 3.4 1.1 2.0 3.3 1.1 3.6
3 1.0 3.4 1.1 2.0 3.3 1.1 3.6
–30°C +25°C +85°C
Min Max Min Typ Max Min Max
350 350 390 425
–1.080 –1.080 –1.080 –1.080
–1.655 –1.655 –1.655 –1.655
1.7
2.5
5.5
1.5
150 150 200 150 MHz
P1
3.9 1.8
–0.980 –0.980 –0.980 –0.980
2.5
5.0
1.5
V
IH
V
IL
2.9 3.8 2.0
P2
–1.630 –1.630 –1.630 –1.630
V
IHA
V
IL
220 220 245 265
–0.910 –0.910 –0.910 –0.910
2.5
5.5
1.5
P3
220 220 245 265
–1.595 –1.595 –1.595 –1.595
4.2
V V
ILA IL
Unit
µAdc
Vdc
Vdc
MOTOROLA MECL Data
3–48
DL122 — Rev 6
Page 4
MC10141
Und
(VCC)
ELECTRICAL CHARACTERISTICS (continued)
TEST VOLTAGE VALUES (Volts)
@ Test Temperature V
–30°C –0.890 –1.890 –1.205 –1.500 –5.2 +25°C –0.810 –1.850 –1.105 –1.475 –5.2 +85°C –0.700 –1.825 –1.035 –1.440 –5.2
Pin
Characteristic Symbol
Power Supply Drain Current I Input Current I
Output Voltage Logic 1 V Output Voltage Logic 0 V Threshold Voltage Logic 1 V
Threshold Voltage Logic 0 V
Switching Times (50 Load) –3.2 V +2.0 V Propagation Delay
Setup TIme (t
Hold Time (t Rise Time (20 to 80%) t Fall Time (20 to 80%) t Shift Frequency f
1. These tests to be performed in sequence as shown.
2. See shift frequency test circuit for test procedures.
3. Reset to zero before performing test.
4. Reset to one before performing test.
setup
hold
)
)
E
inH
I
inL
OH
OL
OHA
(Note 1.)
OLA
(Note 1.)
t
4+3+
t
12+4+
t
10+4+
t
4+12+
3+ 3–
shift
Test
8 8 1, 16 5
6 7 4
12
3 6 8 4 1, 16 3 8 4 1, 16 3
3 3 3
3 3 3 3
3 14 14 14
3 8 1, 16
3 8 1, 16
IHmax
TEST VOLTAGE APPLIED TO PINS LISTED BELOW
er
V
IHmax
5 6 7 4
4,5,6,7,9,
10,11,13
6 6
6
Note 2. 8 1, 16
P1
V
ILminVIHAminVILAmax
V
ILminVIHAminVILAmax
12 8 1, 16
Note 3. Note 3.
Note 4. Note 4.
V V
IH IL
6
7
6 7
P2
V V
IHA IL
V
EE
EE
8 8 8 8
8 8 8 8
8 8 8 8
8 8 8 8
P1 P2 P3
4 4
4 4
P3
4
4
4
4
V
ILA
V
IL
V
Gnd
1, 16 1, 16 1, 16 1, 16
1, 16 1, 16 1, 16 1, 16
1, 16 1, 16 1, 16 1, 16
1, 16 1, 16 1, 16 1, 16
Each MECL 10,000 series circuit has been designed to meet the dc specifications shown in the test table, after thermal equilibrium has been established. The circuit is in a test socket or mounted on a printed circuit board and transverse air flow greater than 500 linear fpm is maintained. Outputs are terminated through a 50–ohm resistor to –2.0 volts. Test procedures are shown for only one gate. The other gates are tested in the same manner.
3–49 MOTOROLAMECL Data
DL122 — Rev 6
Page 5
MC10141
OUTLINE DIMENSIONS
FN SUFFIX
PLASTIC PLCC PACKAGE
CASE 775–02
ISSUE C
–L–
20 1
Z
C
G
G1
0.010 (0.250) N
S
T
–N–
L–M
S
Y BRK
–M–
W
V
A
0.007 (0.180) N
0.007 (0.180) N
R
E
0.004 (0.100)
J
PLANE
SEATING
–T–
VIEW S
S
0.007 (0.180) N
B
0.007 (0.180) N
U
M
S
L–M
T
M
S
S
L–M
T
S
D
Z
D
X
0.010 (0.250) N
G1
S
S
L–M
T
S
VIEW D–D
M
M
S
L–M
T
L–M
T
S
S
S
0.007 (0.180) N
H
M
S
L–M
T
S
K1
K
0.007 (0.180) N
F
M
S
L–M
T
S
VIEW S
NOTES:
1. DATUMS –L–, –M–, AND –N– DETERMINED WHERE TOP OF LEAD SHOULDER EXITS PLASTIC BODY AT MOLD PARTING LINE.
2. DIMENSION G1, TRUE POSITION TO BE MEASURED AT DA TUM –T–, SEATING PLANE.
3. DIMENSIONS R AND U DO NOT INCLUDE MOLD FLASH. ALLOWABLE MOLD FLASH IS 0.010 (0.250) PER SIDE.
4. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982.
5. CONTROLLING DIMENSION: INCH.
6. THE PACKAGE TOP MAY BE SMALLER THAN THE PACKAGE BOTTOM BY UP TO 0.012 (0.300). DIMENSIONS R AND U ARE DETERMINED AT THE OUTERMOST EXTREMES OF THE PLASTIC BODY EXCLUSIVE OF MOLD FLASH, TIE BAR BURRS, GATE BURRS AND INTERLEAD FLASH, BUT INCLUDING ANY MISMATCH BETWEEN THE TOP AND BOTTOM OF THE PLASTIC BODY.
7. DIMENSION H DOES NOT INCLUDE DAMBAR PROTRUSION OR INTRUSION. THE DAMBAR PROTRUSION(S) SHALL NOT CAUSE THE H DIMENSION TO BE GREATER THAN 0.037 (0.940). THE DAMBAR INTRUSION(S) SHALL NOT CAUSE THE H DIMENSION TO BE SMALLER THAN 0.025 (0.635).
MOTOROLA MECL Data
DIM MIN MAX MIN MAX
A 0.385 0.395 9.78 10.03 B 0.385 0.395 9.78 10.03 C 0.165 0.180 4.20 4.57 E 0.090 0.110 2.29 2.79 F 0.013 0.019 0.33 0.48 G 0.050 BSC 1.27 BSC H 0.026 0.032 0.66 0.81 J 0.020 ––– 0.51 ––– K 0.025 ––– 0.64 ––– R 0.350 0.356 8.89 9.04 U 0.350 0.356 8.89 9.04 V 0.042 0.048 1.07 1.21 W 0.042 0.048 1.07 1.21 X 0.042 0.056 1.07 1.42 Y ––– 0.020 ––– 0.50 Z 2 10 2 10
____
G1 0.310 0.330 7.88 8.38 K1 0.040 ––– 1.02 –––
3–50
MILLIMETERSINCHES
DL122 — Rev 6
Page 6
OUTLINE DIMENSIONS
CERAMIC DIP PACKAGE
–A–
16 9
–B–
18
C
–T–
SEATING PLANE
E
F
G
16 PLD
0.25 (0.010) T
M
–A–
916
B
18
F
C
S
H
G
D
16 PL
K
0.25 (0.010) T
K
N
S
A
PLASTIC DIP PACKAGE
SEATING
–T–
PLANE
M
M
A
L SUFFIX
CASE 620–10
ISSUE V
L
M
16 PLJ
0.25 (0.010) T
P SUFFIX
CASE 648–08
ISSUE R
L
J
MC10141
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982.
2. CONTROLLING DIMENSION: INCH.
3. DIMENSION L TO CENTER OF LEAD WHEN FORMED PARALLEL.
4. DIMENSION F MAY NARROW TO 0.76 (0.030) WHERE THE LEAD ENTERS THE CERAMIC BODY.
DIM MIN MAX MIN MAX
A 0.750 0.785 19.05 19.93 B 0.240 0.295 6.10 7.49 C ––– 0.200 ––– 5.08 D 0.015 0.020 0.39 0.50 E 0.050 BSC 1.27 BSC F 0.055 0.065 1.40 1.65 G 0.100 BSC 2.54 BSC H 0.008 0.015 0.21 0.38 K 0.125 0.170 3.18 4.31
M
S
B
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
2. CONTROLLING DIMENSION: INCH.
3. DIMENSION L TO CENTER OF LEADS WHEN
4. DIMENSION B DOES NOT INCLUDE MOLD FLASH.
5. ROUNDED CORNERS OPTIONAL.
M
L 0.300 BSC 7.62 BSC M 0 15 0 15
____
N 0.020 0.040 0.51 1.01
Y14.5M, 1982.
FORMED PARALLEL.
DIM MIN MAX MIN MAX
A 0.740 0.770 18.80 19.55 B 0.250 0.270 6.35 6.85 C 0.145 0.175 3.69 4.44 D 0.015 0.021 0.39 0.53 F 0.040 0.70 1.02 1.77 G 0.100 BSC 2.54 BSC H 0.050 BSC 1.27 BSC J 0.008 0.015 0.21 0.38 K 0.110 0.130 2.80 3.30 L 0.295 0.305 7.50 7.74 M 0 10 0 10 S 0.020 0.040 0.51 1.01
MILLIMETERSINCHES
MILLIMETERSINCHES
____
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MC10141/D
DL122 — Rev 6
3–51 MOTOROLAMECL Data
*MC10141/D*
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