Datasheet MC10138P, MC10138FN, MC10138L Datasheet (Motorola)

Page 1

SEMICONDUCTOR TECHNICAL DATA
 
The MC10138 is a four bit counter capable of divide by two, five, or ten functions. It is composed of four set–reset master–slave flip–flops. Clock inputs trigger on the positive going edge of the clock pulse.
Set or reset input override the clock, allowing asynchronous “set” or “clear.” Individual set and common reset inputs are provided, as well as complementary outputs for the first and fourth bits.
PD= 370 mW typ/pkg (No Load)
f
= 150 MHz typ
tog
tr, tf= 2.5 ns typ (20%–80%)
LOGIC DIAGRAM
Clock
Reset
S0 Q0
11
15
S
1
D
Q
12
9
Q’
C1
Q
R
14
Q
0
S1 Q1
10
13
S
D1
Q
2
D
Q’
C2
Q
R
7
C2
V
CC1
= PIN 1; V
S2 Q2
6
4
S
D
1
Q
C1
Q’
C2
Q
R
= PIN 16; VEE = PIN 8
CC2
S3 Q3
5
S
1
D D2 C2
R
Q’
Q Q
3
Q
COUNTER TRUTH TABLES
BI–QUINARY
(Clock connected to C2
and Q3
connected to C1)
COUNT
Q1 Q2 Q3 Q0 COUNT Q0 Q1 Q2 Q3
(Clock connected to C1
and Q0 connected to C2)
0 L L L L 0 L L L L 1 H L L L 1 H L L L 2 L H L L 2 L H L L 3 H H L L 3 H H L L
4 L L H L 4 L L H L 5 L L L H 5 H L H L 6 H L L H 6 L H H L 7 L H L H 7 H H H L
8 H H L H 8 L L L H 9 L L H H 9 H L L H
BCD

L SUFFIX
CERAMIC PACKAGE
CASE 620–10
P SUFFIX
PLASTIC PACKAGE
CASE 648–08
2
PIN ASSIGNMENT
V
CC1
3
Q3 Q3 Q2
S3 S2
C2
V
EE
Pin assignment is for Dual–in–Line Package.
For PLCC pin assignment, see the Pin Conversion
T ables on page 6–11 of the Motorola MECL Data
1 2 3 4 5 6 7 8
Book (DL122/D).
CASE 775–02
DIP
FN SUFFIX
PLCC
16 15 14 13 12 11 10
9
V
CC2
Q0 Q0 Q1 C1 S0 S1 RESET
CLOCK CONNECTED TO C2 Q0 CONNECTED TO C2
4
32
3/93
Motorola, Inc. 1996
COUNTER STATE DIAGRAM — POSITIVE LOGIC
0
71
5
6
3–41
01 2
14
15
98
3
10
11
12
13
7
65
4
REV 5
Page 2
MC10138
Under
ELECTRICAL CHARACTERISTICS
Test Limits
Pin
Characteristic Symbol
Power Supply Drain Current I Input Current I
Output Voltage Logic 1 V
Output Voltage Logic 0 V
Threshold Voltage Logic 1 V
Threshold Voltage Logic 0 V
Switching Times (50 Load) ns Propagation Clock Delays
Delay
Set Delay t
Reset Delay t
Rise Time (20 to 80%) t
Fall Time (20 to 80%) t
Counting Frequency f
1. Individually test each input; apply V
2. Set all four flip–flops by applying pulse
3. Reset all four flip–flops by applying pulse
E
inH
I
inL
OH
OL
OHA
OLA
t
12+15+
t
12+14+ t
7+13+ t
7+4+
t
7+2+
t
7+3+
t
12+15–
t
12+14– t
7+13– t
7+4–
t
7+2–
t
7+3–
11+15+
t
11+14–
9+14+
t
9+15–
14+
t
15+ 14–
t
15–
count
ILmin
Under
Test
8 97 70 88 97 mAdc
12
5,6,10,1 1
7 9
All 0.5 0.5 0.3 µAdc
3,14 (3.)
2,4,13,15 (2.)
3,14 (2.)
2,4,13,15 (3.) 2,4,13,15 (2.)
3,14 (3.)
13,15 (2.)
2,4,13,15 (3.)
3,14 (2.)
13,15 (3.)
15 14 13
4 2 3
15 14 13
4 2 3
15 14
14 15
14 15
14 15
2
15
to pin under test.
–30°C +25°C +85°C
Min Max Min Typ Max Min Max
–1.060 –1.060
–1.890 –1.890
–1.080 –1.080 –1.080
V
IHmax
V
ILmin
V V
350 390 460 650
–0.890 –0.890
–1.675 –1.675
–1.655 –1.655 –1.655
1.4
1.4
1.4
1.4
1.4
1.4
1.4
1.4
1.4
1.4
1.4
1.4
1.4
1.4
1.4
1.4
1.1
1.1
1.1
1.1
125 125
IHmax ILmin
5.0
5.0
5.2
5.2
5.2
5.2
5.0
5.0
5.2
5.2
5.2
5.2
5.2
5.2
5.2
5.2
4.7
4.7
4.7
4.7
to pins 5, 6, 10, and 11 prior to applying test voltage indicated.
to pin 9 prior to applying test voltage indicated.
–0.960 –0.960
–1.850 –1.850
–0.980 –0.980 –0.980
1.5
1.5
1.5
1.5
1.5
1.5
1.5
1.5
1.5
1.5
1.5
1.5
1.5
1.5
1.5
1.5
1.1
1.1
1.1
1.1
125 125
3.5
3.5
3.5
3.5
3.5
3.5
3.5
3.5
3.5
3.5
3.5
3.5
2.5
2.5
2.5
2.5
150 150
220 245 290 410
–0.810 –0.810
–1.650 –1.650
–1.630 –1.630 –1.630
4.8
4.8
5.0
5.0
5.0
5.0
4.8
4.8
5.0
5.0
5.0
5.0
5.0
5.0
5.0
5.0
4.5
4.5
4.5
4.5
–0.890 –0.890
–1.825 –1.825
–0.910 –0.910 –0.910
1.5
1.5
1.5
1.5
1.5
1.5
1.5
1.5
1.5
1.5
1.5
1.5
1.5
1.5
1.5
1.5
1.1
1.1
1.1
1.1
125 125
220 245 290
–0.700 –0.700
–1.615 –1.615
–1.595 –1.595 –1.595
5.3
5.3
5.5
5.5
5.5
5.5
5.3
5.3
5.5
5.5
5.5
5.5
5.5
5.5
5.5
5.5
5.0
5.0
5.0
5.0
Unit
µAdc
Vdc
Vdc
Vdc
Vdc
MHz
MOTOROLA MECL Data
3–42
DL122 — Rev 6
Page 3
ELECTRICAL CHARACTERISTICS (continued)
b
ificati
has been established. The circuit is in a test
transverse air flow greater than 500 linear fpm is
p
Pin
NOTE: Each MECL 10,000 series circuit has
een designed to meet the dc spec shown in the test table, after thermal equilibrium has been established. The circuit is in a test socket or mounted on a printed circuit board and transverse air flow greater than 500 linear fpm is maintained. Outputs are terminated through a 50–ohm resistor to –2.0 volts. Test procedures are shown for only one gate. The other gates are tested in the same manner.
ons
@ Test Temperature V
TEST VOLTAGE VALUES (Volts)
IHmax
V
ILmin
V
IHAminVILAmax
V
EE
–30°C –0.890 –1.890 –1.205 –1.500 –5.2 +25°C –0.810 –1.850 –1.105 –1.475 –5.2 +85°C –0.700 –1.825 –1.035 –1.440 –5.2
MC10138
TEST VOLTAGE APPLIED TO PINS LISTED BELOW
V
IHmax
V
ILmin
V
IHAminVILAmax
12
5,6,10,1 1
7 9
9
5,6,10,11 5,6,10,11
9
5,6,10,11
9
7,12
5,6,10,11
9
7,12
(VCC)
V
EE
8 8 8 8
8 8
8 8
8 8 8
8 8 8
Gnd
1, 16 1, 16 1, 16 1, 16
1, 16 1, 16
1, 16 1, 16
1, 16 1, 16 1, 16
1, 16 1, 16 1, 16
Characteristic Symbol
Power Supply Drain Current I Input Current I
Output Voltage Logic 1 V
Output Voltage Logic 0 V
Threshold Voltage Logic 1 V
Threshold Voltage Logic 0 V
E
inH
I
inL
OH
OL
OHA
OLA
Pin
Under
Test
8 9 8 1, 16
12
5,6,10,1 1
7 9
All Note 1. 8 1, 16
3,14 (3.)
2,4,13,15 (2.)
3,14 (2.)
2,4,13,15 (3.) 2,4,13,15 (2.)
3,14 (3.)
13,15 (2.)
2,4,13,15 (3.)
3,14 (2.)
13,15 (3.) Switching Times (50 Load) Pulse In Pulse Out –3.2 V +2.0 V Propagation Delay Clock Delays t
Set Delay t
Reset Delay t
12+15+
t
12+14+ t
7+13+ t
7+4+
t
7+2+
t
7+3+
t
12+15–
t
12+14– t
7+13– t
7+4–
t
7+2–
t
7+3–
11+15+
t
11+14–
9+14+
t
9+15–
Rise Time (20 to 80%) t
t
Fall Time (20 to 80%) t
t
Counting Frequency f
1. Individually test each input; apply V
count
ILmin
2. Set all four flip–flops by applying pulse
3. Reset all four flip–flops by applying pulse
14+ 15+
14– 15–
to pin under test.
15 14 13
4 2 3
15 14 13
4 2 3
15 14
14 15
14 15
14 15
2
15
V
IHmax
V
ILmin
V V
12 12
7 7 7 7
12 12
7 7 7 7
11 11
9 9
11 11
9 9
7
12
15 14 13
4 2 3
15 14 13
4 2 3
15 14
14 15
14 15
14 15
2
15
to pins 5, 6, 10, and 11 prior to applying test voltage indicated.
IHmax
to pin 9 prior to applying test voltage indicated.
ILmin
8 8 8 8 8 8
8 8 8 8 8 8
8 8
8 8
8 8
8 8
8 8
1, 16 1, 16 1, 16 1, 16 1, 16 1, 16
1, 16 1, 16 1, 16 1, 16 1, 16 1, 16
1, 16 1, 16
1, 16 1, 16
1, 16 1, 16
1, 16 1, 16
1, 16 1, 16
DL122 — Rev 6
3–43 MOTOROLAMECL Data
Page 4
MC10138
OUTLINE DIMENSIONS
FN SUFFIX
PLASTIC PLCC PACKAGE
CASE 775–02
ISSUE C
–L–
20 1
Z
C
G
G1
0.010 (0.250) N
S
T
–N–
L–M
S
Y BRK
–M–
W
V
A
0.007 (0.180) N
0.007 (0.180) N
R
E
0.004 (0.100)
J
PLANE
SEATING
–T–
VIEW S
S
0.007 (0.180) N
B
U
M
0.007 (0.180) N
S
L–M
T
M
S
S
L–M
T
S
D
Z
D
X
0.010 (0.250) N
G1
S
S
L–M
T
S
VIEW D–D
M
M
S
L–M
T
L–M
T
S
S
S
0.007 (0.180) N
H
M
S
L–M
T
S
K1
K
0.007 (0.180) N
F
M
S
L–M
T
S
VIEW S
NOTES:
1. DATUMS –L–, –M–, AND –N– DETERMINED WHERE TOP OF LEAD SHOULDER EXITS PLASTIC BODY AT MOLD PARTING LINE.
2. DIMENSION G1, TRUE POSITION TO BE MEASURED AT DA TUM –T–, SEATING PLANE.
3. DIMENSIONS R AND U DO NOT INCLUDE MOLD FLASH. ALLOWABLE MOLD FLASH IS 0.010 (0.250) PER SIDE.
4. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982.
5. CONTROLLING DIMENSION: INCH.
6. THE PACKAGE TOP MAY BE SMALLER THAN THE PACKAGE BOTTOM BY UP TO 0.012 (0.300). DIMENSIONS R AND U ARE DETERMINED AT THE OUTERMOST EXTREMES OF THE PLASTIC BODY EXCLUSIVE OF MOLD FLASH, TIE BAR BURRS, GATE BURRS AND INTERLEAD FLASH, BUT INCLUDING ANY MISMATCH BETWEEN THE TOP AND BOTTOM OF THE PLASTIC BODY.
7. DIMENSION H DOES NOT INCLUDE DAMBAR PROTRUSION OR INTRUSION. THE DAMBAR PROTRUSION(S) SHALL NOT CAUSE THE H DIMENSION TO BE GREATER THAN 0.037 (0.940). THE DAMBAR INTRUSION(S) SHALL NOT CAUSE THE H DIMENSION TO BE SMALLER THAN 0.025 (0.635).
MOTOROLA MECL Data
DIM MIN MAX MIN MAX
A 0.385 0.395 9.78 10.03 B 0.385 0.395 9.78 10.03 C 0.165 0.180 4.20 4.57 E 0.090 0.110 2.29 2.79 F 0.013 0.019 0.33 0.48 G 0.050 BSC 1.27 BSC H 0.026 0.032 0.66 0.81 J 0.020 ––– 0.51 ––– K 0.025 ––– 0.64 ––– R 0.350 0.356 8.89 9.04 U 0.350 0.356 8.89 9.04 V 0.042 0.048 1.07 1.21 W 0.042 0.048 1.07 1.21 X 0.042 0.056 1.07 1.42 Y ––– 0.020 ––– 0.50 Z 2 10 2 10
____
G1 0.310 0.330 7.88 8.38 K1 0.040 ––– 1.02 –––
3–44
MILLIMETERSINCHES
DL122 — Rev 6
Page 5
OUTLINE DIMENSIONS
CERAMIC DIP PACKAGE
–A–
16 9
–B–
18
C
–T–
SEATING PLANE
N
E
F
G
16 PLD
0.25 (0.010) T
M
–A–
916
B
18
F
C
S
H
G
D
16 PL
0.25 (0.010) T
K
M
K
S
A
PLASTIC DIP PACKAGE
SEATING
–T–
PLANE
M
A
L SUFFIX
CASE 620–10
ISSUE V
L
M
16 PLJ
0.25 (0.010) T
P SUFFIX
CASE 648–08
ISSUE R
L
J
MC10138
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982.
2. CONTROLLING DIMENSION: INCH.
3. DIMENSION L TO CENTER OF LEAD WHEN FORMED PARALLEL.
4. DIMENSION F MAY NARROW TO 0.76 (0.030) WHERE THE LEAD ENTERS THE CERAMIC BODY.
DIM MIN MAX MIN MAX
A 0.750 0.785 19.05 19.93 B 0.240 0.295 6.10 7.49 C ––– 0.200 ––– 5.08 D 0.015 0.020 0.39 0.50 E 0.050 BSC 1.27 BSC F 0.055 0.065 1.40 1.65 G 0.100 BSC 2.54 BSC H 0.008 0.015 0.21 0.38 K 0.125 0.170 3.18 4.31
M
S
B
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
2. CONTROLLING DIMENSION: INCH.
3. DIMENSION L TO CENTER OF LEADS WHEN
4. DIMENSION B DOES NOT INCLUDE MOLD FLASH.
5. ROUNDED CORNERS OPTIONAL.
M
L 0.300 BSC 7.62 BSC M 0 15 0 15
____
N 0.020 0.040 0.51 1.01
Y14.5M, 1982.
FORMED PARALLEL.
DIM MIN MAX MIN MAX
A 0.740 0.770 18.80 19.55 B 0.250 0.270 6.35 6.85 C 0.145 0.175 3.69 4.44 D 0.015 0.021 0.39 0.53 F 0.040 0.70 1.02 1.77 G 0.100 BSC 2.54 BSC H 0.050 BSC 1.27 BSC J 0.008 0.015 0.21 0.38 K 0.110 0.130 2.80 3.30 L 0.295 0.305 7.50 7.74 M 0 10 0 10 S 0.020 0.040 0.51 1.01
MILLIMETERSINCHES
MILLIMETERSINCHES
____
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MC10138/D
DL122 — Rev 6
3–45 MOTOROLAMECL Data
*MC10138/D*
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