Datasheet MC10137L Datasheet (Motorola)

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Page 1

STATE DIAGRAMS

987

012

987

COUNT UP

COUNT DOWN



SEMICONDUCTOR TECHNICAL DATA

3–35

REV 5

 Motorola, Inc. 1996

3/93

  

The MC10137 is a high speed synchronous counter that can count up, down, preset, or stop count at frequencies exceeding 100 MHz. The flexibility of this device allows the designer to use one basic counter for most applications. The synchronous count feature makes the MC10137 suitable for either computers or instrumentation.

Three control lines (S1, S2, and Carry In

) determine the operation mode of the counter. Lines S1 and S2 determine one of four operations; preset (program), increment (count up), decrement (count down), or hold (stop count). Note that in the preset mode a clock pulse is necessary to load the counter, and the information present on the data inputs (D0, D1, D2, and D3) will be entered into the counter. Carry Out

goes low on the terminal count. The Carry Out on the MC10137 is partially decoded from Q1 and Q2 directly, so in the preset mode the condition of the Carry Out

after the Clock’s positive excursion will depend on the condition of Q1 and/or Q2. The counter changes state only on the positive going edge of the clock. Any other input may change at any time except during the positive transition of the clock. The sequence for counting out of improper states is as shown in the State Diagrams.

PD= 625 mW typ/pkg (No Load)

count

= 150 MHz typ

tpd= 3.3 ns typ (C–Q)

= 7.0 ns typ (C–C

out

)

= 5.0 ns typ (C

in–Cout

)

FUNCTION SELECT TABLE

S1 S2 Operating Mode

L L Preset (Program) L H Increment (Count Up) H L Decrement (Count Down) H H Hold (Stop Count)



PIN ASSIGNMENT

CC1

2 3

OUT

D3 D2 S2

CC2

Q1 Q0 C D0 D1 C

16 15 14 13 12 11 10

1 2 3 4 5 6 7 8

L SUFFIX

CERAMIC PACKAGE

CASE 620–10

P SUFFIX

PLASTIC PACKAGE

CASE 648–08

Page 2

MC10137

MOTOROLA MECL Data

DL122 — Rev 6

3–36

LOGIC DIAGRAM

NOTE: Flip–flops will toggle when all T inputs are low.

CC1

= PIN 1

CC2

= PIN 16

VEE= PIN 8

K T

J T

T T

S1 9

S2 7

Carry In

13 Clock

12 D0

14 Q0

11 D1 15 Q1

6D2

2Q2

5D3

3Q3

4 Carry Out

SEQUENTIAL TRUTH TABLE*

INPUTS OUTPUTS

S1 S2 D0 D1 D2 D3

Carry

Clock

Q0 Q1 Q2 Q3

Carry

Out L L H H H L X H H H H L H L H X X X X L H L L L H H L H X X X X L H H L L H L L H X X X X L H L L L L H L H X X X X L H H L L L H L H X X X X H L H L L L H L H X X X X H H H L L L H

H H X X X X X H H L L L H L L H H L L X H H H L L H H L X X X X L H L H L L H H L X X X X L H H L L L H H L X X X X L H L L L L L

* Truth table shows logic states assuming inputs vary in sequence shown from top to bottom.

** A clock H is defined as a clock input transition from a low to a high logic level.

Page 3

MC10137

3–37 MOTOROLAMECL Data

DL122 — Rev 6

ELECTRICAL CHARACTERISTICS

Test Limits

Under

–30°C +25°C +85°C

Characteristic Symbol

Under

Test

Min Max Min Typ Max Min Max

Unit

Power Supply Drain Current I

8 165 120 150 165 mAdc

Input Current I

inH

5,6,11,12

9,10

350 425 390 460

220 265 245 290

µAdc

inL

All 0.5 0.5 0.3 µAdc

Output Voltage Logic 1 V

14 (2.) –1.060 –0.890 –0.960 –0.810 –0.890 –0.700 Vdc

Output Voltage Logic 0 V

14 (2.) –1.890 –1.675 –1.850 –1.650 –1.825 –1.615 Vdc

Threshold Voltage Logic 1 V

OHA

14 (2.) –1.080 –0.980 –0.910 Vdc

Threshold Voltage Logic 0 V

OLA

14 (2.) –1.655 –1.630 –1.595 Vdc Switching Times (50Ω Load) ns Propagation Delay Clock Input t

13+14+

13+14– t

13+4+

13+4–

14 14

4 4

0.8

2.0

4.8

10.9

1.0

2.5

3.3

7.0

4.5

10.5

1.1

2.4

5.0

11.5

Carry In to Carry Out t

10–4–

10+4+

4 (3.)

1.6

7.4

1.6

5.0

6.9

1.9

7.5

Setup Time Data Inputs t

12+13+

12–13+

14 14

3.5

Select Inputs t

9+13+

7+13+

14 14

7.5

Carry In Input t

10–13+

13+10+

14 14

4.5

–1.0

3.7

–1.0

4.5

–1.0

Hold Time Data Inputs t

13+12+

13+12–

14 14

0 0

Select Inputs t

13+9+

13+7+

14 14

–2.5 –2.5

Carry In Input t

13+10–

10+13+

14 14

–1.6

4.0

–1.6

3.1

–1.6

4.0

Counting Frequency f

countup

countdown

14 14

125 125

150 150

125 125

MHz

Rise Time (20 to 80%) t

14+

0.9

3.3

1.1

2.0

3.3

1.1

3.5

Fall Time (20 to 80%) t

4–

14–

0.9

3.3

1.1

2.0

3.3

1.1

3.5

1. Individually apply V

ILmin

to pin under test.

2. Measure output after clock pulse

appears at clock input (Pin 13).

3. Before test set Q1 and Q2 outputs to a logic low.

Page 4

MC10137

MOTOROLA MECL Data

DL122 — Rev 6

3–38

ELECTRICAL CHARACTERISTICS (continued)

TEST VOLTAGE VALUES (Volts)

@ Test Temperature V

IHmax

ILminVIHAminVILAmax

–30°C –0.890 –1.890 –1.205 –1.500 –5.2 +25°C –0.810 –1.850 –1.105 –1.475 –5.2 +85°C –0.700 –1.825 –1.035 –1.440 –5.2

TEST VOLTAGE APPLIED TO PINS LISTED BELOW

Characteristic Symbol

Und

Test

IHmax

ILminVIHAminVILAmax

(VCC)

Gnd

Power Supply Drain Current I

8 8 1, 16

Input Current I

inH

5,6,11,12

9,10

5,6,11,12

9,10

8 8 8 8

1, 16 1, 16 1, 16 1, 16

inL

All Note 1. 8 1, 16

Output Voltage Logic 1 V

14 (2.) 12 7, 9 8 1, 16

Output Voltage Logic 0 V

14 (2.) 7, 9 8 1, 16

Threshold Voltage Logic 1 V

OHA

14 (2.) 7, 9 12 8 1, 16

Threshold Voltage Logic 0 V

OLA

14 (2.) 7, 9 12 8 1, 16 Switching Times (50Ω Load) +1.1 1V +0.31V Pulse In Pulse Out –3.2 V +2.0 V Propagation Delay Clock Input t

13+14+

13+14– t

13+4+

13+4–

14 14

4 4

7 7

13 13 13 13

14 14

4 4

8 8 8 8

1, 16 1, 16 1, 16 1, 16

Carry In to Carry Out t

10–4–

10+4+

4 (3.)

7 7

13 13

10 10

4 4

8 8

1, 16 1, 16

Setup Time Data Inputs t

12+13+

12–13+

14 14

7, 9 7, 9

12, 13 12, 13

14 14

8 8

1, 16 1, 16

Select Inputs t

9+13+

7+13+

14 14

9, 13 7, 13

14 14

8 8

1, 16 1, 16

Carry In Inputs t

10–13+

13+10+

14 14

7 7

9 9

10, 13 10, 13

14 14

8 8

1, 16 1, 16

Hold Time Data Inputs t

13+12+

13+12–

14 14

7, 9 7, 9

12, 13 12, 13

14 14

8 8

1, 16 1, 16

Select Inputs t

13+9+

13+7+

14 14

9, 13 7, 13

14 14

8 8

1, 16 1, 16

Carry In Inputs t

13+10–

10+13+

14 14

7 7

9 9

10, 13 10, 13

14 14

8 8

1, 16 1, 16

Counting Frequency f

countup

countdown

14 14

7 9

13 13

14 14

8 8

1, 16 1, 16

Rise Time (20 to 80%) t

14+

7 7

13 13

8 8

1, 16 1, 16

Fall Time (20 to 80%) t

4–

14–

7 7

13 13

8 8

1, 16 1, 16

1. Individually test each input; apply V

ILmin

to pin under test.

2. Measure output after clock pulse

appears at clock input (Pin 13).

3. Before test set all Q outputs to a logic high. Each MECL 10,000 series circuit has been designed to meet the dc specifications shown in the test table, after thermal equilibrium has been

established. The circuit is in a test socket or mounted on a printed circuit board and transverse air flow greater than 500 linear fpm is maintained. Outputs are terminated through a 50-ohm resistor to –2.0 volts. Test procedures are shown for only one gate. The other gates are tested in the same manner.

Page 5

MC10137

3–39 MOTOROLAMECL Data

DL122 — Rev 6

Clock Input

D or S

Clock

Q Output

SWITCHING TIME TEST CIRCUIT AND WAVEFORMS @ 25°C

(a) is the minimum time to wait after the counter has been enabled to clock it.

(b) is the minimum time before the counter has been disabled that it may be clocked.

(c) is the minimum time before the counter is enabled that a clock pulse may be applied with no effect on the state of the counter.

(d) is the minimum time to wait after the counter is disabled that a clock pulse may be applied with no effect in the state of the counter.

(b) and (c) may be negative numbers.

out

Coax

out

Q0 C D0

D1 D2 D3 S1 S2

out

Coax

0.1

VEE = –3.2 Vdc

CC1

= V

CC2

= +2.0 Vdc

0.1

setup L

hold L

50%

hold H

setup H

50%

C+Q+

Q+

80% 50% 20%

Q–

C+Q–

+0.31 V

+1.11 V

+0.31 V

+1.11 V

50-ohm termination to ground located in each scope channel input.

All input and output cables to the scope are equal lengths of 50-ohm coaxial cable. Wire length should be < 1/4 inch from TPin to input pin and TP

out

to output pin.

Unused outputs are connected to a 50-ohm resistor to ground.

NOTE:

setup

is the minimum time before the positive transition of the clock pulse (C) that information must be present at the input D or S.

hold

is the minimum time after the positive transition of the clock pulse (C) that information must remain unchanged at the input D or S.

Input Pulse

t+ = t– = 2.0

0.2 ns

(20 to 80%)

Clock

Carry in

(c)

(d)

Clock

Carry In

(a)

(b)

Page 6

MC10137

MOTOROLA MECL Data

DL122 — Rev 6

3–40

OUTLINE DIMENSIONS

P SUFFIX

PLASTIC DIP PACKAGE

CASE 648–08

ISSUE R

NOTES:

1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982.

2. CONTROLLING DIMENSION: INCH.

3. DIMENSION L TO CENTER OF LEADS WHEN FORMED PARALLEL.

4. DIMENSION B DOES NOT INCLUDE MOLD FLASH.

5. ROUNDED CORNERS OPTIONAL.

–A–

16 PL

SEATING

916

PLANE

–T–

0.25 (0.010) T

DIM MIN MAX MIN MAX

MILLIMETERSINCHES

A 0.740 0.770 18.80 19.55 B 0.250 0.270 6.35 6.85 C 0.145 0.175 3.69 4.44 D 0.015 0.021 0.39 0.53 F 0.040 0.70 1.02 1.77 G 0.100 BSC 2.54 BSC H 0.050 BSC 1.27 BSC J 0.008 0.015 0.21 0.38 K 0.110 0.130 2.80 3.30 L 0.295 0.305 7.50 7.74 M 0 10 0 10 S 0.020 0.040 0.51 1.01

____

L SUFFIX

CERAMIC DIP PACKAGE

CASE 620–10

ISSUE V

NOTES:

1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982.

2. CONTROLLING DIMENSION: INCH.

3. DIMENSION L TO CENTER OF LEAD WHEN FORMED PARALLEL.

4. DIMENSION F MAY NARROW TO 0.76 (0.030) WHERE THE LEAD ENTERS THE CERAMIC BODY.

–A–

–B–

–T–

SEATING PLANE

16 PLD

0.25 (0.010) T

16 PLJ

0.25 (0.010) T

DIM MIN MAX MIN MAX

MILLIMETERSINCHES

A 0.750 0.785 19.05 19.93 B 0.240 0.295 6.10 7.49 C ––– 0.200 ––– 5.08 D 0.015 0.020 0.39 0.50 E 0.050 BSC 1.27 BSC F 0.055 0.065 1.40 1.65

G 0.100 BSC 2.54 BSC

H 0.008 0.015 0.21 0.38 K 0.125 0.170 3.18 4.31 L 0.300 BSC 7.62 BSC

M 0 15 0 15

N 0.020 0.040 0.51 1.01

____

16 9

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MC10137/D

*MC10137/D*

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