Datasheet MC10136P, MC10136FN Datasheet (Motorola)

Page 1

SEMICONDUCTOR TECHNICAL DATA
  
Three control lines (S1, S2, and Carry In the counter. Lines S1 and S2 determine one of four operations; preset (program), increment (count up), decrement (count down), or hold (stop count). Note that in the preset mode a clock pulse is necessary to load the counter, and the information present on the data inputs (D0, D1, D2, and D3) will be entered into the counter. Carry Out
goes low on the terminal count, or when the counter
is being preset.
This device is not designed for use with gated clocks. Control is via S1 and S2.
PD= 625 mW typ/pkg (No Load)
f
= 150 MHz typ
count
tpd= 3.3 ns typ (C-Q)
7.0 ns typ (C-C
5.0 ns typ (C
FUNCTION TABLE
CinS1 S2 Operating Mode
X L L Preset (Program)
L L H Increment (Count Up)
H L H Hold Count
L H L Decrement (Count Down) H H L Hold Count X H H Hold (Stop Count)
) determine the operation mode of
)
out
-C
)
out
in

L SUFFIX
CERAMIC PACKAGE
CASE 620–10
P SUFFIX
PLASTIC PACKAGE
CASE 648–08
FN SUFFIX
PLCC
CASE 775–02
DIP
PIN ASSIGNMENT
V
CC1
Q2 Q3
C
out D3
D2
S2
V
EE
Pin assignment is for Dual–in–Line Package.
For PLCC pin assignment, see the Pin Conversion
T ables on page 6–11 of the Motorola MECL Data
1 2 3 4 5 6 7 8
Book (DL122/D).
16 15 14 13 12 11 10
V
CC2
Q1 Q0 CLOCK D0 D1 C
in
S1
9
3/93
Motorola, Inc. 1996
3–27
REV 5
Page 2
MC10136
S1 9
S2 7
Carry In
10
Clock
13
Q0
T
Q0
T T
C
LOGIC DIAGRAM
Q1T Q1
T
C
V
= PIN 1
CC1
V
= PIN 16
CC2
Q2T
T
Q2
T
C
T
T
Q3
T T
Q3
T
T
C
VEE= PIN 8
12 D0 14 Q0 11 D1 15 Q1 6 D2 2 Q2 5 D3 3 Q3 4 Carry Out
NOTE: Flip-flops will toggle when all T inputs are low.
INPUTS OUTPUTS
S1 S2 D0 D1 D2 D3
L L L L H H X H L L H H L L H X X X X L H H L H H H L H X X X X L H L H H H H L H X X X X L H H H H H L
L H X X X X H L H H H H H L H X X X X H H H H H H H
H H X X X X X H H H H H H
L L H H L L X H H H L L L
H L X X X X L H L H L L H H L X X X X L H H L L L H H L X X X X L H L L L L L H L X X X X L H H H H H H
* Truth table shows logic states assuming inputs vary in sequence shown from top to bottom.
** A clock H is defined as a clock input transition from a low to a high logic level.
SEQUENTIAL TRUTH TABLE*
CarryInClock
**
Q0 Q1 Q2 Q3
Carry
Out
MOTOROLA MECL Data
3–28
DL122 — Rev 6
Page 3
MC10136
Under
ELECTRICAL CHARACTERISTICS
Test Limits
Pin
Characteristic Symbol
Power Supply Drain Current I Input Current I
Output Voltage Logic 1 V Output Voltage Logic 0 V Threshold Voltage Logic 1 V Threshold Voltage Logic 0 V Switching Times (50 Load) ns Propagation Delay Clock Input t
Carry In to Carry Out t
Setup Time Data Inputs t
Select Inputs t
Carry In Input t
Hold Time Data Inputs t
Select Inputs t
Carry In Input t
Counting Frequency f
Rise Time (20 to 80%) t
Fall Time (20 to 80%) t
1. Individually test each input; apply V
2. Measure output after clock pulse
3. Before test set all Q outputs to a logic high.
4. To preserve reliable performance, the MC10136 (plastic packaged device only) is to be operated in ambient temperatures above 70°C only when 500lfpm blown air or equivalent heat sinking is provided.
E
inH
I
inL
OH
OL
OHA
OLA
13+14+
t
13+14– t
13+4+
t
13+4– 10–4–
t
10+4+
12+13+
t
12–13+
9+13+
t
7+13+
10–13+
t
10+13+ 13+12+
t
13+12–
13+9+
t
13+7+
13+10–
t
13+10+
countup
f
countdown
4+
t
14+
4–
t
14–
ILmin
V
IL
Under
Test
8 138 100 125 138 mAdc
5,6,1 1,12
7
9,10
13
All 0.5 0.5 0.3 µAdc 14 (2.) –1.060 –0.890 –0.960 –0.810 –0.890 –0.700 Vdc 14 (2.) –1.890 –1.675 –1.850 –1.650 –1.825 –1.615 Vdc 14 (2.) –1.080 –0.980 –0.910 Vdc 14 (2.) –1.655 –1.630 –1.595 Vdc
14
14
4 4
4 (3.)
4
14
14
14
14
14
14
14
14
14
14
14
14
14
14
4
14
4
14
to pin under test.
V
IH
appears at clock input (Pin 13).
–30°C +25°C +85°C
Min Max Min Typ Max Min Max
0.8
0.8
2.0
2.0
1.6
1.6
3.5
3.5
6.0
6.0
2.5
1.5 0
0
–1.0 –1.0
0 0
125 125
0.9
0.9
0.9
0.9
350 425 390 460
4.8
4.8
10.9
10.9
7.4
7.4
3.3
3.3
3.3
3.3
1.0
1.0
2.5
2.5
1.6
1.6
3.5
3.5
6.0
6.0
2.5
1.5 0
0
–1.0 –1.0
0 0
125 125
1.1
1.1
1.1
1.1
3.3
3.3
7.0
7.0
5.0
5.0
150 150
2.0
2.0
2.0
2.0
220 265 245 290
4.5
4.5
10.5
10.5
6.9
6.9
3.3
3.3
3.3
3.3
1.4
1.4
2.4
2.4
1.9
1.9
3.5
3.5
6.0
6.0
3.0
1.5 0
0
–1.0 –1.0
0 0
125 125
1.1
1.1
1.1
1.1
220 265 245 290
5.0
5.0
11.5
11.5
7.5
7.5
3.5
3.5
3.5
3.5
Unit
µAdc
MHz
ns
DL122 — Rev 6
3–29 MOTOROLAMECL Data
Page 4
MC10136
Und
(VCC)
ELECTRICAL CHARACTERISTICS (continued)
TEST VOLTAGE VALUES (Volts)
@ Test Temperature V
–30°C –0.890 –1.890 –1.205 –1.500 –5.2 +25°C –0.810 –1.850 –1.105 –1.475 –5.2 +85°C –0.700 –1.825 –1.035 –1.440 –5.2
Pin
Characteristic Symbol
Power Supply Drain Current I Input Current I
Output Voltage Logic 1 V Output Voltage Logic 0 V Threshold Voltage Logic 1 V Threshold Voltage Logic 0 V Switching Times (50 Load) +1.1 1V +0.31V Pulse In Pulse Out –3.2 V +2.0 V Propagation Delay Clock Input t
Carry In to Carry Out t
Setup Time Data Inputs t
Select Inputs t
Carry In Inputs t
Hold Time Data Inputs t
Select Inputs t
Carry In Inputs t
Counting Frequency f
Rise Time (20 to 80%) t
Fall Time (20 to 80%) t
1. Individually test each input; apply V
2. Measure output after clock pulse
3. Before test set all Q outputs to a logic high.
4. To preserve reliable performance, the MC10136 (plastic packaged device only) is to be operated in ambient temperatures above 70°C only when 500lfpm blown air or equivalent heat sinking is provided.
E
inH
I
inL
OH
OL
OHA
OLA
13+14+
t
13+14– t
13+4+
t
13+4– 10–4–
t
10+4+
12+13+
t
12–13+
9+13+
t
7+13+
10–13+
t
10+13+ 13+12+
t
13+12–
13+9+
t
13+7+
13+10–
t
13+10+ countup
f
countdown
4+
t
14+
4–
t
14–
to pin under test.
ILmin
V
IL
Test
8 8 1, 16
5,6,1 1,12
7
9,10
13
All Note 1. 8 1, 16 14 (2.) 12 7, 9 8 1, 16 14 (2.) 7, 9 8 1, 16 14 (2.) 7, 9 12 8 1, 16 14 (2.) 7, 9 12 8 1, 16
14
14
4 4
4 (3.)
4
14
14
14
14
14
14
14
14
14
14
14
14
14
14
4
14
4
14
V
IH
appears at clock input (Pin 13).
er
IHmax
TEST VOLTAGE APPLIED TO PINS LISTED BELOW
V
IHmax
5,6,1 1,12
7
9,10
13
12
7 7
7 7
7 7
7 7
7 9
7 7
7 7
V
ILmin
V
ILmin
13 13
7, 9 7, 9
9 9
7, 9 7, 9
9 10, 13
V
IHAminVILAmax
V
IHAminVILAmax
13 13 13 13
10 10
12, 13 12, 13
9, 13 7, 13
10, 13 10, 13
12, 13 12, 13
9, 13 7, 13
10, 13
13 13
13 13
13 13
14 14
4 4
4 4
14 14
14 14
14 14
14 14
14 14
14 14
14 14
4
14
4
14
V
EE
V
EE
8 8 8 8
8 8 8 8
8 8
8 8
8 8
8 8
8 8
8 8
8 8
8 8
8 8
8 8
Gnd
1, 16 1, 16 1, 16 1, 16
1, 16 1, 16 1, 16 1, 16
1, 16 1, 16
1, 16 1, 16
1, 16 1, 16
1, 16 1, 16
1, 16 1, 16
1, 16 1, 16
1, 16 1, 16
1, 16 1, 16
1, 16 1, 16
1, 16 1, 16
Each MECL 10,000 series circuit has been designed to meet the dc specifications shown in the test table, after thermal equilibrium has been established. The circuit is in a test socket or mounted on a printed circuit board and transverse air flow greater than 500 linear fpm is maintained. Outputs are terminated through a 50-ohm resistor to –2.0 volts. Test procedures are shown for only one gate. The other gates are tested in the same manner.
MOTOROLA MECL Data
3–30
DL122 — Rev 6
Page 5
SWITCHING TIME TEST CIRCUIT AND WAVEFORMS @ 25°C
NOTE:
t
is the minimum time before the positive
setup
transition of the clock pulse (C) that information must be present at the input D or S.
t
is the minimum time after the positive tran-
hold
sition of the clock pulse (C) that information must remain unchanged at the input D or S.
INPUT PULSE
Clock
Q Output
D or S
T+ = T– = 2.0 (20 TO 80%)
50%
t
C+Q+
80% 50% 20%
t
Q+
C
Q
50%
t
hold H
t
setup H
50%
±
0.2 NS
t
C+Q–
t
Q–
CLOCK INPUT
+1.11 V
+0.31 V
t
hold L
t
setup L
COAX
MC10136
V
= V
V
IN
TP
CC1
25 µF
in
VEE = –3.2 VDC
+1.11 V +0.31 V
50-ohm termination to ground lo­cated in each scope channel input.
All input and output cables to the scope are equal lengths of 50-ohm coaxial cable. Wire length should be < 1/4 inch from TPin to input pin and TP
Unused outputs are connected to a 50-ohm resistor to ground.
= +2.0 VDC
CC2
16
1
C
Q0
IN
C
Q1
D0 D1
Q2
D2 D3
Q3
S1
C
S2
OUT 8
to output pin.
out
0.1
0.1
V
OUT
µ
F
µ
F
COAX
TP
out
DL122 — Rev 6
CARRY IN SET UP AND HOLD TIMES
Carry in
t
t
set (L)
hold (L)
C
3–31 MOTOROLAMECL Data
t
set (N)
t
hold (N)
Page 6
MC10136
APPLICATIONS INFORMATION
To provide more than four bits of counting capability several MC10136 counters may be cascaded. The Carry In input overrides the clock when the counter is either in the increment mode or the decrement mode of operation. This input allows several devices to be cascaded in a fully synchronous multistage counter as illustrated in Figure 1. The carry is advanced between stages as shown with no external gating. The Carry In open. The system clock is common to all devices.
The various operational modes of the counter make it useful for a wide variety of applications. If used with MECL III devices, prescalers with input toggle frequencies in excess of 300 MHz are possible. Figure 2 shows such a prescaler using the MC10136 and MC1670. Use of the MC10231 in place of the MC1670 permits 200 MHz operation.
FIGURE 1 — 12 BIT SYNCHRONOUS COUNTER FIGURE 2 — 300 MHz PRESCALER
of the first device may be left
The MC10136 may also be used as a programmable counter. The configuration of Figure 3 requires no additional gates, although maximum frequency is limited to about 50 MHz. The divider modulus is equal to the program input plus one (M = N + 1), therefore, the counter will divide by a modulus varying from 1 to 16.
A second programmable configuration is also illustrated in Figure 4. A pulse swallowing technique is used to speed the counter operation up to 1 10 MHz typically . The divider modulus for this figure is equal to the program input (M = N). The minimum modulus is 2 because of the pulse swallowing technique, and the modulus may vary from 2 to 15. This programmable configuration requires an additional gate, such as 1/2MC10109 and a flip-flop such as 1/2MC10131.
System Clock
LSB
Q0 Q1 Q2 Q3
C
in
C
NOTE: S1 and S2 are set either for increment or decrement operation.
C
out
Q0 Q1 Q2 Q3
C
in
C
Q0 Q1 Q2 Q3
C
out
C
in
C
MSB
Input Frequency
DQ C
Q
MC1670
Logic High
MC10136
S1 S2
C
Input Frequency
Q3
32
FIGURE 3 — 50 MHz PROGRAMMABLE COUNTER FIGURE 4 — 100 MHz PROGRAMMABLE COUNTER
Program Input
f
Program Input
D0 D1 D3D2
f
in
C C
S2 S1
in
C
out
f
out
in
D0 D1 D3D2
C S2
S1
MC10136
Q0 Q2 Q3
DQ
f
out
1/2MC10109 1/2MC10131
f
1f
=
out
2f
50 MHz Typ.
max
3 Divide Ratio is from 1 to 16.
MOTOROLA MECL Data
in
Program Input + 1
3–32
1f
=
out
Program Input
2f
110 MHz Typ.
max
3 Divide Ratio is from 2 to 15.
CQ
f
in
DL122 — Rev 6
Page 7
OUTLINE DIMENSIONS
FN SUFFIX
PLASTIC PLCC PACKAGE
CASE 775–02
ISSUE C
MC10136
–L–
20 1
Z
C
G
G1
0.010 (0.250) N
S
T
–N–
L–M
S
Y BRK
–M–
W
V
A
0.007 (0.180) N
0.007 (0.180) N
R
E
0.004 (0.100)
J
PLANE
SEATING
–T–
VIEW S
S
0.007 (0.180) N
B
0.007 (0.180) N
U
M
S
L–M
T
M
S
S
L–M
T
S
D
Z
D
X
0.010 (0.250) N
G1
S
S
L–M
T
S
VIEW D–D
M
M
S
L–M
T
L–M
T
S
S
S
0.007 (0.180) N
H
M
S
L–M
T
S
K1
K
0.007 (0.180) N
F
M
S
L–M
T
S
VIEW S
DL122 — Rev 6
NOTES:
1. DATUMS –L–, –M–, AND –N– DETERMINED WHERE TOP OF LEAD SHOULDER EXITS PLASTIC BODY AT MOLD PARTING LINE.
2. DIMENSION G1, TRUE POSITION TO BE MEASURED AT DA TUM –T–, SEATING PLANE.
3. DIMENSIONS R AND U DO NOT INCLUDE MOLD FLASH. ALLOWABLE MOLD FLASH IS 0.010 (0.250) PER SIDE.
4. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982.
5. CONTROLLING DIMENSION: INCH.
6. THE PACKAGE TOP MAY BE SMALLER THAN THE PACKAGE BOTTOM BY UP TO 0.012 (0.300). DIMENSIONS R AND U ARE DETERMINED AT THE OUTERMOST EXTREMES OF THE PLASTIC BODY EXCLUSIVE OF MOLD FLASH, TIE BAR BURRS, GATE BURRS AND INTERLEAD FLASH, BUT INCLUDING ANY MISMATCH BETWEEN THE TOP AND BOTTOM OF THE PLASTIC BODY.
7. DIMENSION H DOES NOT INCLUDE DAMBAR PROTRUSION OR INTRUSION. THE DAMBAR PROTRUSION(S) SHALL NOT CAUSE THE H DIMENSION TO BE GREATER THAN 0.037 (0.940). THE DAMBAR INTRUSION(S) SHALL NOT CAUSE THE H DIMENSION TO BE SMALLER THAN 0.025 (0.635).
3–33 MOTOROLAMECL Data
DIM MIN MAX MIN MAX
A 0.385 0.395 9.78 10.03 B 0.385 0.395 9.78 10.03 C 0.165 0.180 4.20 4.57 E 0.090 0.110 2.29 2.79 F 0.013 0.019 0.33 0.48 G 0.050 BSC 1.27 BSC H 0.026 0.032 0.66 0.81 J 0.020 ––– 0.51 ––– K 0.025 ––– 0.64 ––– R 0.350 0.356 8.89 9.04 U 0.350 0.356 8.89 9.04 V 0.042 0.048 1.07 1.21 W 0.042 0.048 1.07 1.21 X 0.042 0.056 1.07 1.42 Y ––– 0.020 ––– 0.50 Z 2 10 2 10
____
G1 0.310 0.330 7.88 8.38
K1 0.040 ––– 1.02 –––
MILLIMETERSINCHES
Page 8
MC10136
–T–
SEATING PLANE
18
OUTLINE DIMENSIONS
L SUFFIX
CERAMIC DIP PACKAGE
–A–
16 9
–B–
18
C
N
E
F
G
16 PLD
0.25 (0.010) T
M
S
A
–A–
916
B
F
C
S
–T–
H
G
D
16 PL
0.25 (0.010) T
K
M
A
CASE 620–10
ISSUE V
L
K
P SUFFIX
PLASTIC DIP PACKAGE
CASE 648–08
ISSUE R
SEATING PLANE
J
M
M
16 PLJ
0.25 (0.010) T
L
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982.
2. CONTROLLING DIMENSION: INCH.
3. DIMENSION L TO CENTER OF LEAD WHEN FORMED PARALLEL.
4. DIMENSION F MAY NARROW TO 0.76 (0.030) WHERE THE LEAD ENTERS THE CERAMIC BODY.
DIM MIN MAX MIN MAX
A 0.750 0.785 19.05 19.93 B 0.240 0.295 6.10 7.49 C ––– 0.200 ––– 5.08 D 0.015 0.020 0.39 0.50 E 0.050 BSC 1.27 BSC F 0.055 0.065 1.40 1.65 G 0.100 BSC 2.54 BSC H 0.008 0.015 0.21 0.38 K 0.125 0.170 3.18 4.31
M
S
B
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
2. CONTROLLING DIMENSION: INCH.
3. DIMENSION L TO CENTER OF LEADS WHEN
4. DIMENSION B DOES NOT INCLUDE MOLD FLASH.
5. ROUNDED CORNERS OPTIONAL.
M
L 0.300 BSC 7.62 BSC M 0 15 0 15
____
N 0.020 0.040 0.51 1.01
Y14.5M, 1982.
FORMED PARALLEL.
DIM MIN MAX MIN MAX
A 0.740 0.770 18.80 19.55 B 0.250 0.270 6.35 6.85 C 0.145 0.175 3.69 4.44 D 0.015 0.021 0.39 0.53 F 0.040 0.70 1.02 1.77 G 0.100 BSC 2.54 BSC H 0.050 BSC 1.27 BSC J 0.008 0.015 0.21 0.38 K 0.110 0.130 2.80 3.30 L 0.295 0.305 7.50 7.74 M 0 10 0 10 S 0.020 0.040 0.51 1.01
MILLIMETERSINCHES
MILLIMETERSINCHES
____
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MOTOROLA MECL Data
3–34
*MC10136/D*
MC10136/D
DL122 — Rev 6
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