Datasheet MC10136L, MC10136FNR2 Datasheet (MOTOROLA)



SEMICONDUCTOR TECHNICAL DATA

3–27

REV 5

 Motorola, Inc. 1996

3/93

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The MC10136 is a high speed synchronous counter that can count up, count down, preset, or stop count at frequencies exceeding 100 MHz. The flexibility of this device allows the designer to use one basic counter for most applications, and the synchronous count feature makes the MC10136 suitable for either computers or instrumentation.

Three control lines (S1, S2, and Carry In

) determine the operation mode of the counter. Lines S1 and S2 determine one of four operations; preset (program), increment (count up), decrement (count down), or hold (stop count). Note that in the preset mode a clock pulse is necessary to load the counter, and the information present on the data inputs (D0, D1, D2, and D3) will be entered into the counter. Carry Out

goes low on the terminal count, or when the counter

is being preset.

This device is not designed for use with gated clocks. Control is via S1 and

S2.

PD= 625 mW typ/pkg (No Load)

f

count

= 150 MHz typ

tpd= 3.3 ns typ (C-Q)

7.0 ns typ (C-C

out

)

5.0 ns typ (C

in

-C

out

)

FUNCTION TABLE

CinS1 S2 Operating Mode

X L L Preset (Program)

L L H Increment (Count Up)

H L H Hold Count

L H L Decrement (Count Down) H H L Hold Count X H H Hold (Stop Count)



DIP

PIN ASSIGNMENT

V

CC1

Q2 Q3

C

out D3

D2

S2

V

EE

V

CC2

Q1 Q0 CLOCK D0 D1 C

in

S1

16 15 14 13 12 11 10

9

1 2 3 4 5 6 7 8

Pin assignment is for Dual–in–Line Package.

For PLCC pin assignment, see the Pin Conversion

T ables on page 6–11 of the Motorola MECL Data

Book (DL122/D).

L SUFFIX

CERAMIC PACKAGE

CASE 620–10

P SUFFIX

PLASTIC PACKAGE

CASE 648–08

FN SUFFIX

PLCC

CASE 775–02

MC10136

MOTOROLA MECL Data

DL122 — Rev 6

3–28

Q2T

T

T T

T

T T

Q3

T

Q3

Q1

Q1T

T

C

T

C

T

C

Q0

LOGIC DIAGRAM

NOTE: Flip-flops will toggle when all T inputs are low.

S1 9

S2 7

Carry In

10

Clock

13

12 D0 14 Q0 11 D1 15 Q1 6 D2 2 Q2 5 D3 3 Q3 4 Carry Out

T

C

Q0

T

Q2

V

CC1

= PIN 1

V

CC2

= PIN 16

VEE= PIN 8

SEQUENTIAL TRUTH TABLE*

INPUTS OUTPUTS

S1 S2 D0 D1 D2 D3

CarryInClock

**

Q0 Q1 Q2 Q3

Carry

Out

L L L L H H X H L L H H L L H X X X X L H H L H H H L H X X X X L H L H H H H L H X X X X L H H H H H L

L H X X X X H L H H H H H L H X X X X H H H H H H H

H H X X X X X H H H H H H

L L H H L L X H H H L L L

H L X X X X L H L H L L H H L X X X X L H H L L L H H L X X X X L H L L L L L H L X X X X L H H H H H H

* Truth table shows logic states assuming inputs vary in sequence shown from top to bottom.

** A clock H is defined as a clock input transition from a low to a high logic level.

MC10136

3–29 MOTOROLAMECL Data

DL122 — Rev 6

ELECTRICAL CHARACTERISTICS

Test Limits

Under

–30°C +25°C +85°C

Characteristic Symbol

Under

Test

Min Max Min Typ Max Min Max

Unit

Power Supply Drain Current I

E

8 138 100 125 138 mAdc

Input Current I

inH

5,6,11,12

7

9,10

13

350 425 390 460

220 265 245 290

µAdc

I

inL

All 0.5 0.5 0.3 µAdc

Output Voltage Logic 1 V

OH

14 (2.) –1.060 –0.890 –0.960 –0.810 –0.890 –0.700 Vdc

Output Voltage Logic 0 V

OL

14 (2.) –1.890 –1.675 –1.850 –1.650 –1.825 –1.615 Vdc

Threshold Voltage Logic 1 V

OHA

14 (2.) –1.080 –0.980 –0.910 Vdc

Threshold Voltage Logic 0 V

OLA

14 (2.) –1.655 –1.630 –1.595 Vdc Switching Times (50Ω Load) ns Propagation Delay Clock Input t

13+14+

t

13+14– t

13+4+

t

13+4–

14 14

4 4

0.8

2.0

4.8

10.9

1.0

2.5

3.3

7.0

4.5

10.5

1.4

2.4

5.0

11.5

Carry In to Carry Out t

10–4–

t

10+4+

4 (3.)

4

1.6

7.4

1.6

5.0

6.9

1.9

7.5

Setup Time Data Inputs t

12+13+

t

12–13+

14 14

3.5

Select Inputs t

9+13+

t

7+13+

14 14

6.0

Carry In Input t

10–13+

t

10+13+

14 14

2.5

1.5

2.5

1.5

3.0

1.5

Hold Time Data Inputs t

13+12+

t

13+12–

14 14

0 0

Select Inputs t

13+9+

t

13+7+

14 14

–1.0 –1.0

Carry In Input t

13+10–

t

13+10+

14 14

0 0

Counting Frequency f

countup

f

countdown

14 14

125 125

150 150

125 125

MHz

Rise Time (20 to 80%) t

4+

t

14+

4

14

0.9

3.3

1.1

2.0

3.3

1.1

3.5

ns

Fall Time (20 to 80%) t

4–

t

14–

4

14

0.9

3.3

1.1

2.0

3.3

1.1

3.5

1. Individually test each input; apply V

ILmin

to pin under test.

2. Measure output after clock pulse

V

IH

V

IL

appears at clock input (Pin 13).

3. Before test set all Q outputs to a logic high.

4. To preserve reliable performance, the MC10136 (plastic packaged device only) is to be operated in ambient temperatures above 70°C only when 500lfpm blown air or equivalent heat sinking is provided.

MC10136

MOTOROLA MECL Data

DL122 — Rev 6

3–30

ELECTRICAL CHARACTERISTICS (continued)

TEST VOLTAGE VALUES (Volts)

@ Test Temperature V

IHmax

V

ILminVIHAminVILAmax

V

EE

–30°C –0.890 –1.890 –1.205 –1.500 –5.2 +25°C –0.810 –1.850 –1.105 –1.475 –5.2 +85°C –0.700 –1.825 –1.035 –1.440 –5.2

TEST VOLTAGE APPLIED TO PINS LISTED BELOW

Characteristic Symbol

Und

er

Test

V

IHmax

V

ILminVIHAminVILAmax

V

EE

(VCC)

Gnd

Power Supply Drain Current I

E

8 8 1, 16

Input Current I

inH

5,6,11,12

7

9,10

13

5,6,11,12

7

9,10

13

8 8 8 8

1, 16 1, 16 1, 16 1, 16

I

inL

All Note 1. 8 1, 16

Output Voltage Logic 1 V

OH

14 (2.) 12 7, 9 8 1, 16

Output Voltage Logic 0 V

OL

14 (2.) 7, 9 8 1, 16

Threshold Voltage Logic 1 V

OHA

14 (2.) 7, 9 12 8 1, 16

Threshold Voltage Logic 0 V

OLA

14 (2.) 7, 9 12 8 1, 16 Switching Times (50Ω Load) +1.1 1V +0.31V Pulse In Pulse Out –3.2 V +2.0 V Propagation Delay Clock Input t

13+14+

t

13+14– t

13+4+

t

13+4–

14 14

4 4

12

7 7

13 13 13 13

14 14

4 4

8 8 8 8

1, 16 1, 16 1, 16 1, 16

Carry In to Carry Out t

10–4–

t

10+4+

4 (3.)

4

7 7

13 13

10 10

4 4

8 8

1, 16 1, 16

Setup Time Data Inputs t

12+13+

t

12–13+

14 14

7, 9 7, 9

12, 13 12, 13

14 14

8 8

1, 16 1, 16

Select Inputs t

9+13+

t

7+13+

14 14

9, 13 7, 13

14 14

8 8

1, 16 1, 16

Carry In Inputs t

10–13+

t

10+13+

14 14

7 7

9 9

10, 13 10, 13

14 14

8 8

1, 16 1, 16

Hold Time Data Inputs t

13+12+

t

13+12–

14 14

7, 9 7, 9

12, 13 12, 13

14 14

8 8

1, 16 1, 16

Select Inputs t

13+9+

t

13+7+

14 14

9, 13 7, 13

14 14

8 8

1, 16 1, 16

Carry In Inputs t

13+10–

t

13+10+

14 14

7 7

9 10, 13

10, 13

14 14

8 8

1, 16 1, 16

Counting Frequency f

countup

f

countdown

14 14

7 9

13 13

14 14

8 8

1, 16 1, 16

Rise Time (20 to 80%) t

4+

t

14+

4

14

7 7

13 13

4

14

8 8

1, 16 1, 16

Fall Time (20 to 80%) t

4–

t

14–

4

14

7 7

13 13

4

14

8 8

1, 16 1, 16

1. Individually test each input; apply V

ILmin

to pin under test.

2. Measure output after clock pulse

V

IH

V

IL

appears at clock input (Pin 13).

3. Before test set all Q outputs to a logic high.

4. To preserve reliable performance, the MC10136 (plastic packaged device only) is to be operated in ambient temperatures above 70°C only when 500lfpm blown air or equivalent heat sinking is provided.

Each MECL 10,000 series circuit has been designed to meet the dc specifications shown in the test table, after thermal equilibrium has been established. The circuit is in a test socket or mounted on a printed circuit board and transverse air flow greater than 500 linear fpm is maintained. Outputs are terminated through a 50-ohm resistor to –2.0 volts. Test procedures are shown for only one gate. The other gates are tested in the same manner.

MC10136

3–31 MOTOROLAMECL Data

DL122 — Rev 6

SWITCHING TIME TEST CIRCUIT AND WAVEFORMS @ 25°C

50-ohm termination to ground located in each scope channel input.

All input and output cables to the scope are equal lengths of 50-ohm coaxial cable. Wire length should be < 1/4 inch from TPin to input pin and TP

out

to output pin.

Unused outputs are connected to a 50-ohm resistor to ground.

NOTE:

t

setup

is the minimum time before the positive transition of the clock pulse (C) that information must be present at the input D or S.

t

hold

is the minimum time after the positive transition of the clock pulse (C) that information must remain unchanged at the input D or S.

INPUT PULSE T+ = T– = 2.0

±

0.2 NS

(20 TO 80%)

CARRY IN SET UP AND HOLD TIMES

t

set (L)

t

set (N)

t

hold (L)

t

hold (N)

C

Carry in

C

IN

TP

out

t

setup L

t

hold L

50%

t

hold H

t

setup H

Q

D or S

50%

C

50%

t

C+Q+

t

Q+

80% 50% 20%

Clock

COAX

C

OUT

Q3

Q2

Q1

Q0 C D0 D1 D2 D3 S1 S2

t

Q–

t

C+Q–

V

OUT

CLOCK INPUT

V

IN

Q Output

COAX

+0.31 V

TP

in

+1.11 V

+0.31 V

+1.11 V

16

25 µF

1

0.1

µ

F

8

VEE = –3.2 VDC

V

CC1

= V

CC2

= +2.0 VDC

0.1

µ

F

MC10136

MOTOROLA MECL Data

DL122 — Rev 6

3–32

FIGURE 1 — 12 BIT SYNCHRONOUS COUNTER FIGURE 2 — 300 MHz PRESCALER

FIGURE 3 — 50 MHz PROGRAMMABLE COUNTER FIGURE 4 — 100 MHz PROGRAMMABLE COUNTER

APPLICATIONS INFORMATION

To provide more than four bits of counting capability several MC10136 counters may be cascaded. The Carry In input overrides the clock when the counter is either in the increment mode or the decrement mode of operation. This input allows several devices to be cascaded in a fully synchronous multistage counter as illustrated in Figure 1. The carry is advanced between stages as shown with no external gating. The Carry In

of the first device may be left

open. The system clock is common to all devices.

The various operational modes of the counter make it useful for a wide variety of applications. If used with MECL III devices, prescalers with input toggle frequencies in excess of 300 MHz are possible. Figure 2 shows such a prescaler using the MC10136 and MC1670. Use of the MC10231 in place of the MC1670 permits 200 MHz operation.

The MC10136 may also be used as a programmable counter. The configuration of Figure 3 requires no additional gates, although maximum frequency is limited to about 50 MHz. The divider modulus is equal to the program input plus one (M = N + 1), therefore, the counter will divide by a modulus varying from 1 to 16.

A second programmable configuration is also illustrated in Figure 4. A pulse swallowing technique is used to speed the counter operation up to 110 MHz typically. The divider modulus for this figure is equal to the program input (M = N). The minimum modulus is 2 because of the pulse swallowing technique, and the modulus may vary from 2 to 15. This programmable configuration requires an additional gate, such as 1/2MC10109 and a flip-flop such as 1/2MC10131.

DQ

CQ

Input Frequency

NOTE: S1 and S2 are set either for increment or decrement operation.

1f

out

=

f

in

Program Input + 1

2f

max

≅ 50 MHz Typ.

3 Divide Ratio is from 1 to 16.

System Clock

C

Q0 Q1 Q2 Q3

LSB

C

in

C

out

Logic High

MC10136

S1 S2

C

Q3

DQ C

Q

MC1670

Input Frequency

32

f

in

f

out

Q0 Q2 Q3

C

out

C

in

D0 D1 D3D2

C

S2 S1

Program Input

1/2MC10109 1/2MC10131

C

Q0 Q1 Q2 Q3

C

in

C

out

C

Q0 Q1 Q2 Q3

MSB

C

in

1f

out

=

f

in

Program Input

2f

max

≅ 110 MHz Typ.

3 Divide Ratio is from 2 to 15.

f

in

D0 D1 D3D2

C S2

S1

Program Input

MC10136

f

out

MC10136

3–33 MOTOROLAMECL Data

DL122 — Rev 6

OUTLINE DIMENSIONS

FN SUFFIX

PLASTIC PLCC PACKAGE

CASE 775–02

ISSUE C

NOTES:

1. DATUMS –L–, –M–, AND –N– DETERMINED WHERE TOP OF LEAD SHOULDER EXITS PLASTIC BODY AT MOLD PARTING LINE.

2. DIMENSION G1, TRUE POSITION TO BE MEASURED AT DATUM –T–, SEATING PLANE.

3. DIMENSIONS R AND U DO NOT INCLUDE MOLD FLASH. ALLOWABLE MOLD FLASH IS 0.010 (0.250) PER SIDE.

4. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982.

5. CONTROLLING DIMENSION: INCH.

6. THE PACKAGE TOP MAY BE SMALLER THAN THE PACKAGE BOTTOM BY UP TO 0.012 (0.300). DIMENSIONS R AND U ARE DETERMINED AT THE OUTERMOST EXTREMES OF THE PLASTIC BODY EXCLUSIVE OF MOLD FLASH, TIE BAR BURRS, GATE BURRS AND INTERLEAD FLASH, BUT INCLUDING ANY MISMATCH BETWEEN THE TOP AND BOTTOM OF THE PLASTIC BODY.

7. DIMENSION H DOES NOT INCLUDE DAMBAR PROTRUSION OR INTRUSION. THE DAMBAR PROTRUSION(S) SHALL NOT CAUSE THE H DIMENSION TO BE GREATER THAN 0.037 (0.940). THE DAMBAR INTRUSION(S) SHALL NOT CAUSE THE H DIMENSION TO BE SMALLER THAN 0.025 (0.635).

–M–

–N–

–L–

Y BRK

W

V

D

S

L–M

M

0.007 (0.180) N

S

T

S

L–M

M

0.007 (0.180) N

S

T

S

L–M

S

0.010 (0.250) N

S

T

X

G1

B

U

Z

VIEW D–D

20 1

S

L–M

M

0.007 (0.180) N

S

T

S

L–M

M

0.007 (0.180) N

S

T

S

L–M

S

0.010 (0.250) N

S

T

C

G

VIEW S

E

J

R

Z

A

0.004 (0.100)

–T–

SEATING PLANE

S

L–M

M

0.007 (0.180) N

S

T

S

L–M

M

0.007 (0.180) N

S

T

H

VIEW S

K

K1

F

G1

DIM MIN MAX MIN MAX

MILLIMETERSINCHES

A 0.385 0.395 9.78 10.03 B 0.385 0.395 9.78 10.03 C 0.165 0.180 4.20 4.57 E 0.090 0.110 2.29 2.79 F 0.013 0.019 0.33 0.48 G 0.050 BSC 1.27 BSC H 0.026 0.032 0.66 0.81 J 0.020 ––– 0.51 ––– K 0.025 ––– 0.64 ––– R 0.350 0.356 8.89 9.04 U 0.350 0.356 8.89 9.04 V 0.042 0.048 1.07 1.21 W 0.042 0.048 1.07 1.21 X 0.042 0.056 1.07 1.42 Y ––– 0.020 ––– 0.50 Z 2 10 2 10

G1 0.310 0.330 7.88 8.38

K1 0.040 ––– 1.02 –––

____

MC10136

MOTOROLA MECL Data

DL122 — Rev 6

3–34

OUTLINE DIMENSIONS

P SUFFIX

PLASTIC DIP PACKAGE

CASE 648–08

ISSUE R

NOTES:

1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982.

2. CONTROLLING DIMENSION: INCH.

3. DIMENSION L TO CENTER OF LEADS WHEN FORMED PARALLEL.

4. DIMENSION B DOES NOT INCLUDE MOLD FLASH.

5. ROUNDED CORNERS OPTIONAL.

–A–

B

F

C

S

H

G

D

J

L

M

16 PL

SEATING

18

916

K

PLANE

–T–

M

A

M

0.25 (0.010) T

DIM MIN MAX MIN MAX

MILLIMETERSINCHES

A 0.740 0.770 18.80 19.55 B 0.250 0.270 6.35 6.85 C 0.145 0.175 3.69 4.44 D 0.015 0.021 0.39 0.53 F 0.040 0.70 1.02 1.77 G 0.100 BSC 2.54 BSC H 0.050 BSC 1.27 BSC J 0.008 0.015 0.21 0.38 K 0.110 0.130 2.80 3.30 L 0.295 0.305 7.50 7.74 M 0 10 0 10 S 0.020 0.040 0.51 1.01

____

L SUFFIX

CERAMIC DIP PACKAGE

CASE 620–10

ISSUE V

NOTES:

1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982.

2. CONTROLLING DIMENSION: INCH.

3. DIMENSION L TO CENTER OF LEAD WHEN FORMED PARALLEL.

4. DIMENSION F MAY NARROW TO 0.76 (0.030) WHERE THE LEAD ENTERS THE CERAMIC BODY.

–A–

–B–

–T–

F

E

G

N

K

C

SEATING PLANE

16 PLD

S

A

M

0.25 (0.010) T

16 PLJ

S

B

M

0.25 (0.010) T

M

L

DIM MIN MAX MIN MAX

MILLIMETERSINCHES

A 0.750 0.785 19.05 19.93 B 0.240 0.295 6.10 7.49 C ––– 0.200 ––– 5.08 D 0.015 0.020 0.39 0.50 E 0.050 BSC 1.27 BSC F 0.055 0.065 1.40 1.65 G 0.100 BSC 2.54 BSC H 0.008 0.015 0.21 0.38 K 0.125 0.170 3.18 4.31 L 0.300 BSC 7.62 BSC M 0 15 0 15 N 0.020 0.040 0.51 1.01

____

16 9

18

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MC10136/D

*MC10136/D*

◊