Datasheet MC10131L, MC10131FNR2 Datasheet (MOTOROLA)

Page 1

SEMICONDUCTOR TECHNICAL DATA
3–8
REV 5
Motorola, Inc. 1996
3/93
   
and Reset (R) override Clock (CC) and Clock
Enable (CE) inputs. Each flip–flop may be clocked separately by holding the common clock in the low state and using the enable inputs for the clocking function. If the common clock is to be used to clock the flip–flop, the Clock
Enable inputs must be in the low state. In this case, the enable inputs perform the function of controlling the common clock.
The output states of the flip–flop change on the positive transition of the clock. A change in the information present at the data (D) input will not affect the output information at any other time due to master slave construction.
PD= 235 mW typ/pkg (No Load)
F
Tog
= 160 MHz typ
tpd= 3.0 ns typ
tr, tf= 2.5 ns typ (20%–80%)
LOGIC DIAGRAM
V
CC1
= PIN 1
V
CC2
= PIN 16
VEE= PIN 8
S1 5
D1 7
C
E1
6
R1 4 CC 9
R2 13
C
E2
11
D2 10
S2 12
Q1
Q
1
Q
2
Q2
2
3
14
15
CLOCKED TRUTH TABLE R–S TRUTH TABLE
C D Q
n+1
R S Q
n+1
L X Q
n
L L Q
n
H L L L H H H H H H L L
C = CE + CC.A clock H is a clock transition from a
H H N.D.
low to a high state.
N.D. = Not Defined

DIP
PIN ASSIGNMENT
V
CC1
Q1 Q1 R1
S1
C
E1
D1
V
EE
V
CC2
Q2 Q2 R2 S2 C
E2
D2 C
C
16 15 14 13 12 11 10
9
1 2 3 4 5 6 7 8
L SUFFIX
CERAMIC PACKAGE
CASE 620–10
P SUFFIX
PLASTIC PACKAGE
CASE 648–08
FN SUFFIX
PLCC
CASE 775–02
Pin assignment is for Dual–in–Line Package.
For PLCC pin assignment, see the Pin Conversion
T ables on page 6–11 of the Motorola MECL Data
Book (DL122/D).
Page 2
MC10131
3–9 MOTOROLAMECL Data
DL122 — Rev 6
ELECTRICAL CHARACTERISTICS
Test Limits
Pin
Under
–30°C +25°C +85°C
Characteristic Symbol
Under
Test
Min Max Min Typ Max Min Max
Unit
Power Supply Drain Current I
E
8 62 45 56 62 mAdc
Input Current I
inH
4 5 6 7 9
525 525 350 390 425
330 330 220 245 265
330 330 220 245 265
µAdc
I
inL
4, 5*
6, 7, 9*
0.5
0.5
0.5
0.5
0.3
0.3
µAdc
Output Voltage Logic 1 V
OH
2
2
[
–1.060 –1.060
–0.890 –0.890
–0.960 –0.960
–0.810 –0.810
–0.890 –0.890
–0.700 –0.700
Vdc
Output Voltage Logic 0 V
OL
2
3
[
–1.890 –1.890
–1.675 –1.675
–1.850 –1.850
–1.650 –1.650
–1.825 –1.825
–1.615 –1.615
Vdc
Threshold Voltage Logic 1 V
OHA
2
2
[
–1.080 –1.080
–0.980 –0.980
–0.910 –0.910
Vdc
Threshold Voltage Logic 0 V
OLA
2
3
[
–1.655 –1.655
–1.630 –1.630
–1.595 –1.595
Vdc
Switching Times (50 Load) Clock Input
ns
Propagation Delay t
9+2–
t
9+2+
t
6+2+
t
6+2–
2 2 2 2
1.7
1.7
1.7
1.7
4.6
4.6
4.6
4.6
1.8
1.8
1.8
1.8
3.0
3.0
3.0
3.0
4.5
4.5
4.5
4.5
1.8
1.8
1.8
1.8
5.0
5.0
5.0
5.0
Rise Time (20 to 80%) t
2+
2 1.0 4.6 1.1 2.5 4.5 1.1 4.9
Fall Time (20 to 80%) t
2–
2 1.0 4.6 1.1 2.5 4.5 1.1 4.9
Set Input ns
Propagation Delay t
5+2+
t
12+15+
t
5+3–
t
12+14–
2
15
3
14
1.7
1.7
1.7
1.7
4.4
4.4
4.4
4.4
1.8
1.8
1.8
1.8
2.8
2.8
2.8
2.8
4.3
4.3
4.3
4.3
1.8
1.8
1.8
1.8
4.8
4.8
4.8
4.8
Reset Input ns
Propagation Delay t
4+2–
t
13+15–
t
4+3–
t
13+14+
2
15
3
14
1.7
1.7
1.7
1.7
4.4
4.4
4.4
4.4
1.8
1.8
1.8
1.8
2.8
2.8
2.8
2.8
4.3
4.3
4.3
4.3
1.8
1.8
1.8
1.8
4.8
4.8
4.8
4.8
Setup Time t
setup
7 2.5 2.5 2.5 ns
Hold Time t
hold
7 1.5 1.5 1.5 ns
Toggle Frequency (Max) f
tog
2 125 125 160 125 MHz
* Individually test each input applying VIH or VIL to input under test.
[
Output level to be measured after a clock pulse has been applied to the C
E
Input (Pin 6)
V
IHmax
V
ILmin
Page 3
MC10131
MOTOROLA MECL Data
DL122 — Rev 6
3–10
ELECTRICAL CHARACTERISTICS (continued)
TEST VOLTAGE VALUES (Volts)
@ Test Temperature V
IHmaxVILminVIHAmin
V
ILAmax
V
EE
–30°C –0.890 –1.890 –1.205 –1.500 –5.2 +25°C –0.810 –1.850 –1.105 –1.475 –5.2 +85°C –0.700 –1.825 –1.035 –1.440 –5.2
Pin
TEST VOLTAGE APPLIED TO PINS LISTED BELOW
Characteristic Symbol
Und
er
Test
V
IHmaxVILminVIHAmin
V
ILAmax
V
EE
(VCC)
Gnd
Power Supply Drain Current I
E
8 8 1, 16
Input Current I
inH
4 5 6 7 9
4 5 6 7 9
8 8 8 8 8
1, 16 1, 16 1, 16 1, 16 1, 16
I
inL
4, 5*
6, 7, 9*
* *
8 8
1, 16 1, 16
Output Voltage Logic 1 V
OH
2
2
[
5 7
8 8
1, 16 1, 16
Output Voltage Logic 0 V
OL
2
3
[
5 7
8 8
1, 16 1, 16
Threshold Voltage Logic 1 V
OHA
2
2
[
5 7
9
8 8
1, 16 1, 16
Threshold Voltage Logic 0 V
OLA
2
3
[
5 7
9
8 8
1, 16 1, 16
Switching Times (50 Load) Clock Input
+1.11Vdc Pulse In Pulse Out –3.2 V +2.0 V
Propagation Delay t
9+2–
t
9+2+
t
6+2+
t
6+2–
2 2 2 2
7 7
9 9 6 6
2 2 2 2
8 8 8 8
1, 16 1, 16 1, 16 1, 16
Rise Time (20 to 80%) t
2+
2 7 9 2 8 1, 16
Fall Time (20 to 80%) t
2–
2 9 2 8 1, 16
Set Input
Propagation Delay t
5+2+
t
12+15+
t
5+3–
t
12+14–
2
15
3
14
6 9
5
12
5
12
2
15
3
14
8 8 8 8
1, 16 1, 16 1, 16 1, 16
Reset Input
Propagation Delay t
4+2–
t
13+15–
t
4+3–
t
13+14+
2
15
3
14
6 9
4
13
4
13
2
15
3
14
8 8 8 8
1, 16 1, 16 1, 16 1, 16
Setup Time t
setup
7 6, 7 2 8 1, 16
Hold Time t
hold
7 6, 7 2 8 1, 16
Toggle Frequency (Max) f
tog
2 6 2 8 1, 16
* Individually test each input applying VIH or VIL to input under test.
[
Output level to be measured after a clock pulse has been applied to the C
E
Input (Pin 6)
V
IHmax
V
ILmin
Each MECL 10,000 series circuit has been designed to meet the dc specifications shown in the test table, after thermal equilibrium has been established. The circuit is in a test socket or mounted on a printed circuit board and transverse air flow greater than 500 linear fpm is maintained. Outputs are terminated through a 50–ohm resistor to –2.0 volts. Test procedures are shown for only one gate. The other gates are tested in the same manner.
Page 4
MC10131
3–11 MOTOROLAMECL Data
DL122 — Rev 6
OUTLINE DIMENSIONS
FN SUFFIX
PLASTIC PLCC PACKAGE
CASE 775–02
ISSUE C
NOTES:
1. DATUMS –L–, –M–, AND –N– DETERMINED WHERE TOP OF LEAD SHOULDER EXITS PLASTIC BODY AT MOLD PARTING LINE.
2. DIMENSION G1, TRUE POSITION TO BE MEASURED AT DATUM –T–, SEATING PLANE.
3. DIMENSIONS R AND U DO NOT INCLUDE MOLD FLASH. ALLOWABLE MOLD FLASH IS 0.010 (0.250) PER SIDE.
4. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982.
5. CONTROLLING DIMENSION: INCH.
6. THE PACKAGE TOP MAY BE SMALLER THAN THE PACKAGE BOTTOM BY UP TO 0.012 (0.300). DIMENSIONS R AND U ARE DETERMINED AT THE OUTERMOST EXTREMES OF THE PLASTIC BODY EXCLUSIVE OF MOLD FLASH, TIE BAR BURRS, GATE BURRS AND INTERLEAD FLASH, BUT INCLUDING ANY MISMATCH BETWEEN THE TOP AND BOTTOM OF THE PLASTIC BODY.
7. DIMENSION H DOES NOT INCLUDE DAMBAR PROTRUSION OR INTRUSION. THE DAMBAR PROTRUSION(S) SHALL NOT CAUSE THE H DIMENSION TO BE GREATER THAN 0.037 (0.940). THE DAMBAR INTRUSION(S) SHALL NOT CAUSE THE H DIMENSION TO BE SMALLER THAN 0.025 (0.635).
–M–
–N–
–L–
Y BRK
W
V
D
D
S
L–M
M
0.007 (0.180) N
S
T
S
L–M
M
0.007 (0.180) N
S
T
S
L–M
S
0.010 (0.250) N
S
T
X
G1
B
U
Z
VIEW D–D
20 1
S
L–M
M
0.007 (0.180) N
S
T
S
L–M
M
0.007 (0.180) N
S
T
S
L–M
S
0.010 (0.250) N
S
T
C
G
VIEW S
E
J
R
Z
A
0.004 (0.100)
–T–
SEATING PLANE
S
L–M
M
0.007 (0.180) N
S
T
S
L–M
M
0.007 (0.180) N
S
T
H
VIEW S
K
K1
F
G1
DIM MIN MAX MIN MAX
MILLIMETERSINCHES
A 0.385 0.395 9.78 10.03 B 0.385 0.395 9.78 10.03 C 0.165 0.180 4.20 4.57 E 0.090 0.110 2.29 2.79 F 0.013 0.019 0.33 0.48 G 0.050 BSC 1.27 BSC H 0.026 0.032 0.66 0.81 J 0.020 ––– 0.51 ––– K 0.025 ––– 0.64 ––– R 0.350 0.356 8.89 9.04 U 0.350 0.356 8.89 9.04 V 0.042 0.048 1.07 1.21 W 0.042 0.048 1.07 1.21 X 0.042 0.056 1.07 1.42 Y ––– 0.020 ––– 0.50
Z 2 10 2 10 G1 0.310 0.330 7.88 8.38 K1 0.040 ––– 1.02 –––
____
Page 5
MC10131
MOTOROLA MECL Data
DL122 — Rev 6
3–12
OUTLINE DIMENSIONS
P SUFFIX
PLASTIC DIP PACKAGE
CASE 648–08
ISSUE R
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982.
2. CONTROLLING DIMENSION: INCH.
3. DIMENSION L TO CENTER OF LEADS WHEN FORMED PARALLEL.
4. DIMENSION B DOES NOT INCLUDE MOLD FLASH.
5. ROUNDED CORNERS OPTIONAL.
–A–
B
F
C
S
H
G
D
J
L
M
16 PL
SEATING
18
916
K
PLANE
–T–
M
A
M
0.25 (0.010) T
DIM MIN MAX MIN MAX
MILLIMETERSINCHES
A 0.740 0.770 18.80 19.55 B 0.250 0.270 6.35 6.85 C 0.145 0.175 3.69 4.44 D 0.015 0.021 0.39 0.53 F 0.040 0.70 1.02 1.77
G 0.100 BSC 2.54 BSC
H 0.050 BSC 1.27 BSC J 0.008 0.015 0.21 0.38 K 0.110 0.130 2.80 3.30 L 0.295 0.305 7.50 7.74
M 0 10 0 10
S 0.020 0.040 0.51 1.01
____
L SUFFIX
CERAMIC DIP PACKAGE
CASE 620–10
ISSUE V
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982.
2. CONTROLLING DIMENSION: INCH.
3. DIMENSION L TO CENTER OF LEAD WHEN FORMED PARALLEL.
4. DIMENSION F MAY NARROW TO 0.76 (0.030) WHERE THE LEAD ENTERS THE CERAMIC BODY.
–A–
–B–
–T–
F
E
G
N
K
C
SEATING PLANE
16 PLD
S
A
M
0.25 (0.010) T
16 PLJ
S
B
M
0.25 (0.010) T
M
L
DIM MIN MAX MIN MAX
MILLIMETERSINCHES
A 0.750 0.785 19.05 19.93 B 0.240 0.295 6.10 7.49 C ––– 0.200 ––– 5.08 D 0.015 0.020 0.39 0.50 E 0.050 BSC 1.27 BSC F 0.055 0.065 1.40 1.65 G 0.100 BSC 2.54 BSC H 0.008 0.015 0.21 0.38 K 0.125 0.170 3.18 4.31 L 0.300 BSC 7.62 BSC M 0 15 0 15 N 0.020 0.040 0.51 1.01
____
16 9
18
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MC10131/D
*MC10131/D*
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