Datasheet MC10110L, MC10110P Datasheet (Motorola)

Page 1



SEMICONDUCTOR TECHNICAL DATA

   

The MC10110 is designed to drive up to three transmission lines simul– taneously. The multiple outputs of this device also allow the wire “OR”–ing of several levels of gating for minimization of gate and package count.

The ability to control three parallel lines from a single point makes the MC10110 particularly useful in clock distribution applications where minimum clock skew is desired. Three VCC pins are provided and each one should be used.

PD= 80 mW typ/pkg (No Load) tpd= 2.4 ns typ (All Outputs Loaded)

tr, tf= 2.2 ns typ (20%–80%)

LOGIC DIAGRAM

5 6 7

9 10 11

= PIN 1, 15

CC1

= PIN 16

CC2 VEE= PIN 8

2 3 4

12 13 14



CERAMIC PACKAGE

PLASTIC PACKAGE

DIP

PIN ASSIGNMENT

OUT

CC1

1 2 3 4 5 6 7 8

L SUFFIX

CASE 620–10

P SUFFIX

CASE 648–08

16 15 14 13 12 11 10

V V B B B B B B

CC2 CC1 OUT OUT OUT IN IN IN

9/96

 Motorola, Inc. 1996

3–40

Pin assignment is for Dual–in–Line Package.

For PLCC pin assignment, see the Pin Conversion

Tables on page 6–36 of the Motorola MECL Data

Book (DL122/D).

REV 6

Page 2

MC10110

Under

ELECTRICAL CHARACTERISTICS

Test Limits

Characteristic Symbol

Power Supply Drain Current I Input Current I

Output Voltage Logic 1 V

Output Voltage Logic 0 V

Threshold Voltage Logic 1 V

Threshold Voltage Logic 0 V

Switching Times (50Ω Load) ns Propagation Delay t

Rise Time (20 to 80%) t

Fall Time (20 to 80%) t

inH

inL

OHA

OLA

5+2+

5–2–

5+3+

5–3–

5+4+

5–4–

4+ 2–

3–

4–

Under

Test

8 42 30 38 42 mAdc 5, 6, 7 680 425 425 µAdc 5, 6, 7 0.5 0.5 0.3 µAdc

–30°C +25°C +85°C

Min Max Min Typ Max Min Max

–1.060 –1.060 –1.060

–1.890 –1.890 –1.890

–1.080 –1.080 –1.080

1.4

1.0

–0.890 –0.890 –0.890

–1.675 –1.675 –1.675

–1.655 –1.655 –1.655

3.5

–0.960 –0.960 –0.960

–1.850 –1.850 –1.850

–0.980 –0.980 –0.980

1.4

1.1

2.4

2.2

–0.810 –0.810 –0.810

–1.650 –1.650 –1.650

–1.630 –1.630 –1.630

3.5

–0.890 –0.890 –0.890

–1.825 –1.825 –1.825

–0.910 –0.910 –0.910

1.5

1.2

–0.700 –0.700 –0.700

–1.615 –1.615 –1.615

–1.595 –1.595 –1.595

3.8

Unit

Vdc

DL122 — Rev 6

3–41 MOTOROLAMECL Data

Page 3

MC10110

ELECTRICAL CHARACTERISTICS (continued)

@ Test Temperature V

TEST VOLTAGE VALUES (Volts)

IHmax

–30°C –0.890 –1.890 –1.205 –1.500 –5.2 +25°C –0.810 –1.850 –1.105 –1.475 –5.2 +85°C –0.700 –1.825 –1.035 –1.440 –5.2

ILmin

IHAminVILAmax

Characteristic Symbol

Power Supply Drain Current I Input Current I

Output Voltage Logic 1 V

Output Voltage Logic 0 V

Threshold Voltage Logic 1 V

Threshold Voltage Logic 0 V

Switching Times (50Ω Load) Pulse In Pulse Out –3.2 V +2.0 V Propagation Delay t

Rise Time (20 to 80%) t

Fall Time (20 to 80%) t

* Individually test each input using the pin connections shown. Each MECL 10,000 series circuit has been designed to meet the dc specifications shown in the test table, after thermal equilibrium has been

established. The circuit is in a test socket or mounted on a printed circuit board and transverse air flow greater than 500 linear fpm is maintained. Outputs are terminated through a 50-ohm resistor to –2.0 volts. Test procedures are shown for only one gate. The other gates are tested in the same manner.

inH

inL

OHA

OLA

5+2+

5–2–

5+3+

5–3–

5+4+

5–4–

4+ 2–

3–

4–

Under

Test

8 8 1, 15, 16 5, 6, 7 * 8 1, 15, 16 5, 6, 7 * 8 1, 15, 16

TEST VOLTAGE APPLIED TO PINS LISTED BELOW

IHmax

5 6 7

ILmin

IHAminVILAmax

5 6 7

5 5 5 5 5 5

5 5 5

2 2 3 3 4 4

2 3 4

(VCC)

8 8 8

8 8 8 8 8 8

8 8 8

Gnd

1, 15, 16 1, 15, 16 1, 15, 16

1, 15, 16 1, 15, 16 1, 15, 16 1, 15, 16 1, 15, 16 1, 15, 16

1, 15, 16 1, 15, 16 1, 15, 16

MOTOROLA MECL Data

3–42

DL122 — Rev 6

Page 4

OUTLINE DIMENSIONS

CERAMIC DIP PACKAGE

–A–

16 9

–B–

–T–

SEATING PLANE

16 PLD

0.25 (0.010) T

–A–

916

16 PL

0.25 (0.010) T

PLASTIC DIP PACKAGE

SEATING

–T–

PLANE

L SUFFIX

CASE 620–10

ISSUE V

16 PLJ

0.25 (0.010) T

P SUFFIX

CASE 648–08

ISSUE R

MC10110

NOTES:

1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982.

2. CONTROLLING DIMENSION: INCH.

3. DIMENSION L TO CENTER OF LEAD WHEN FORMED PARALLEL.

4. DIMENSION F MAY NARROW TO 0.76 (0.030) WHERE THE LEAD ENTERS THE CERAMIC BODY.

DIM MIN MAX MIN MAX

A 0.750 0.785 19.05 19.93 B 0.240 0.295 6.10 7.49 C ––– 0.200 ––– 5.08 D 0.015 0.020 0.39 0.50 E 0.050 BSC 1.27 BSC F 0.055 0.065 1.40 1.65 G 0.100 BSC 2.54 BSC H 0.008 0.015 0.21 0.38 K 0.125 0.170 3.18 4.31

NOTES:

1. DIMENSIONING AND TOLERANCING PER ANSI

2. CONTROLLING DIMENSION: INCH.

3. DIMENSION L TO CENTER OF LEADS WHEN

4. DIMENSION B DOES NOT INCLUDE MOLD FLASH.

5. ROUNDED CORNERS OPTIONAL.

L 0.300 BSC 7.62 BSC M 0 15 0 15

____

N 0.020 0.040 0.51 1.01

Y14.5M, 1982.

FORMED PARALLEL.

DIM MIN MAX MIN MAX

A 0.740 0.770 18.80 19.55 B 0.250 0.270 6.35 6.85 C 0.145 0.175 3.69 4.44 D 0.015 0.021 0.39 0.53 F 0.040 0.70 1.02 1.77 G 0.100 BSC 2.54 BSC H 0.050 BSC 1.27 BSC J 0.008 0.015 0.21 0.38 K 0.110 0.130 2.80 3.30 L 0.295 0.305 7.50 7.74 M 0 10 0 10 S 0.020 0.040 0.51 1.01

MILLIMETERSINCHES

____

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MC10110/D

DL122 — Rev 6

◊

3–43 MOTOROLAMECL Data

*MC10110/D*