Datasheet MC100LVEL39DW, MC100LVEL39DWR2, MC100EL39, MC100EL39DW, MC100EL39DWR2 Datasheet (Motorola)

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SEMICONDUCTOR TECHNICAL DATA

4–1

REV 2

 Motorola, Inc. 1996

3/96

÷

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  

The MC100LVEL39 is a low skew ÷2/4, ÷4/6 clock generation chip
designed explicitly for low skew clock generation applications. The
MC100EL39 is pin and functionally equivalent to the MC100LVEL39 but
is specified for operation at the standard 100K ECL voltage supply. The
internal dividers are synchronous to each other, therefore, the common
output edges are all precisely aligned. The device can be driven by either
a differential or single-ended LVECL or, if positive power supplies are
used, LVPECL input signal. In addition, by using the VBB output, a
sinusoidal source can be AC coupled into the device (see Interfacing
section of the ECLinPS Data Book DL140/D). If a single-ended input is
to be used, the VBB output should be connected to the CLK

input and
bypassed to ground via a 0.01µF capacitor. The VBB output is designed to
act as the switching reference for the input of the LVEL39 under
single-ended input conditions, as a result, this pin can only source/sink up
to 0.5mA of current.

The common enable (EN) is synchronous so that the internal dividers
will only be enabled/disabled when the internal clock is already in the
LOW state. This avoids any chance of generating a runt clock pulse on
the internal clock when the device is enabled/disabled as can happen
with an asynchronous control. An internal runt pulse could lead to losing
synchronization between the internal divider stages. The internal enable
flip-flop is clocked on the falling edge of the input clock, therefore, all
associated specification limits are referenced to the negative edge of the
clock input.

Upon startup, the internal flip-flops will attain a random state; therefore,
for systems which utilize multiple LVEL39s, the master reset (MR) input
must be asserted to ensure synchronization. For systems which only use
one LVEL39, the MR pin need not be exercised as the internal divider
design ensures synchronization between the ÷2/4 and the ÷4/6 outputs of
a single device.

• 50ps Output-to-Output Skew

• Synchronous Enable/Disable

• Master Reset for Synchronization

• 75kΩ Internal Input Pulldown Resistors

• >2000V ESD Protection

• Low Voltage V

EE

Range of –3.0 to –3.8V

CLK

Pinout: 20-Lead SOIC (Top View)

CLK MR V

CC

1718 16 15 14 13 12

43

5 6 7 8 9

Q0

11

10

Q1 Q1 Q2 Q2 Q3 Q3 V

EE

EN

1920

21

VCCQ0

DIVSELb V

BB

V

CC

NC DIVSELa

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DW SUFFIX

PLASTIC SOIC PACKAGE

CASE 751D-04

1

20

PIN FUNCTION

CLK Diff Clock Inputs
EN

Sync Enable
MR Master Reset
V

BB

Reference Output
Q0, Q

1

Diff ÷2/4 Outputs
Q2, Q

3

Diff ÷4/6 Outputs
DIVSEL Frequency Select Input

PIN DESCRIPTION

CLK

Z

ZZ

X

EN

L
H
X

MR

L
L

H

FUNCTION

Divide
Hold Q

0–3

Reset Q

0–3

FUNCTION TABLE

Z = Low-to-High Transition
ZZ = High-to-Low Transition

DIVSELa Q0, Q1 OUTPUTS

0 Divide by 2
1 Divide by 4

DIVSELb Q2, Q3 OUTPUTS

0 Divide by 4
1 Divide by 6

MC100LVEL39 MC100EL39

MOTOROLA ECLinPS and ECLinPS Lite

DL140 — Rev 3

4–2

CLK
CLK

EN

MR

DIVSELb

÷

2/4

Q0
Q0

Q1
Q1

÷

4/6

Q2
Q2

Q3
Q3

LOGIC DIAGRAM

R

R

DIVSELa

CLK

Q (

÷

2)

Q (

÷

4)

Q (

÷

6)

Figure 1. Timing Diagrams

MC100LVEL39
DC CHARACTERISTICS (VEE = –3.8V to –3.0; VCC = GND)

–40°C 0°C 25°C 85°C

Symbol Characteristic Min Typ Max Min Typ Max Min Typ Max Min Typ Max Unit

I

EE

Power Supply Current 50 59 50 59 50 59 54 61 mA

V

BB

Output Reference Voltage –1.38 –1.26 –1.38 –1.26 –1.38 –1.26 –1.38 –1.26 V

I

IH

Input High Current 150 150 150 150 µΑ

MC100LVEL39
AC CHARACTERISTICS (VEE = –3.8V to –3.0; VCC = GND)

–40°C 0°C 25°C 85°C

Symbol Characteristic Min Typ Max Min Typ Max Min Typ Max Min Typ Max Unit

f

MAX

Maximum Toggle Frequency 1000 1000 1000 1000 MHz

t

PLH

t

PHL

Propagation Delay CLK → Q (Diff)
to Output CLK → Q (S.E.)

MR → Q

760
710
600

960

1010

900

780
730
600

980

1030

900

800
750
610

1000
1050

910

850
800
630

1050
1100

930

ps

t

SKEW

Within-Device Skew

1

Q0 – Q

3

50 50 50 50 ps

Part-to-Part Q0 – Q3 (Diff) 200 200 200 200

t

S

Setup Time EN → CLK

DIVSEL → CLK

250
400

250
400

250
400

250
400

ps

t

H

Hold Time CLK → EN

CLK → Div_Sel

100
150

100
150

100
150

100
150

ps

MC100LVEL39 MC100EL39

4–3 MOTOROLAECLinPS and ECLinPS Lite

DL140 — Rev 3

MC100LVEL39 (continued)
AC CHARACTERISTICS (VEE = –3.8V to –3.0; VCC = GND)

–40°C 0°C 25°C 85°C

Symbol Characteristic Min Typ Max Min Typ Max Min Typ Max Min Typ Max Unit

V

PP

Minimum Input Swing CLK 250 250 250 250 mV

V

CMR

Common Mode Range

3

VPP < 500mV
VPP ≥ 500mV

–2.0
–1.8

–0.4
–0.4

–2.1
–1.9

–0.4
–0.4

–2.1
–1.9

–0.4
–0.4

–2.1
–1.9

–0.4
–0.4

V

t

RR

Reset Recovery Time 100 100 100 100 ps

t

PW

Minimum Pulse Width CLKMR500

700

500
700

500
700

500
700

ps

tr, t

f

Output Rise/Fall Times Q (20% – 80%) 280 550 280 550 280 550 280 550 ps

1. Skew is measured between outputs under identical transitions.

2. Minimum input swing for which AC parameters are guaranteed. The device will function reliably with differential inputs down to 100mV.

3. The CMR range is referenced to the most positive side of the differential input signal. Normal operation is obtained if the HIGH level falls within
the specified range and the peak-to-peak voltage lies between VPPmin and 1V. The lower end of the CMR range varies 1:1 with VEE. The
numbers in the spec table assume a nominal VEE = –3.3V. Note for PECL operation, the V

CMR

(min) will be fixed at 3.3V – |V

CMR

(min)|.

MC100EL39
DC CHARACTERISTICS (VEE = –4.2V to –5.46; VCC = GND)

–40°C 0°C 25°C 85°C

Symbol Characteristic Min Typ Max Min Typ Max Min Typ Max Min Typ Max Unit

I

EE

Power Supply Current 50 59 50 59 50 59 54 61 mA

V

BB

Output Reference Voltage –1.38 –1.26 –1.38 –1.26 –1.38 –1.26 –1.38 –1.26 V

I

IH

Input High Current 150 150 150 150 µΑ

MC100EL39
AC CHARACTERISTICS (VEE = –4.2V to –5.46; VCC = GND)

–40°C 0°C 25°C 85°C

Symbol Characteristic Min Typ Max Min Typ Max Min Typ Max Min Typ Max Unit

f

MAX

Maximum Toggle Frequency 1000 1000 1000 1000 MHz

t

PLH

t

PHL

Propagation Delay CLK → Q (Diff)
to Output CLK → Q (S.E.)

MR → Q

760
710
600

960

1010

900

780
730
600

980

1030

900

800
750
610

1000
1050

910

850
800
630

1050
1100

930

ps

t

SKEW

Within-Device Skew

1

Q0 – Q

3

50 50 50 50 ps

Part-to-Part Q0 – Q3 (Diff) 200 200 200 200

t

S

Setup Time EN → CLK

DIVSEL → CLK

250
400

250
400

250
400

250
400

ps

t

H

Hold Time CLK → EN

CLK → Div_Sel

100
150

100
150

100
150

100
150

ps

V

PP

Minimum Input Swing CLK 250 250 250 250 mV

V

CMR

Common Mode Range

3

VPP < 500mV
VPP ≥ 500mV

–3.2
–3.0

–0.4
–0.4

–3.3
–3.1

–0.4
–0.4

–3.3
–3.1

–0.4
–0.4

–3.3
–3.1

–0.4
–0.4

V

t

RR

Reset Recovery Time 100 100 100 100 ps

t

PW

Minimum Pulse Width CLKMR500

700

500
700

500
700

500
700

ps

tr, t

f

Output Rise/Fall Times Q (20% – 80%) 280 550 280 550 280 550 280 550 ps

1. Skew is measured between outputs under identical transitions.

2. Minimum input swing for which AC parameters are guaranteed. The device will function reliably with differential inputs down to 100mV.

3. The CMR range is referenced to the most positive side of the differential input signal. Normal operation is obtained if the HIGH level falls within
the specified range and the peak-to-peak voltage lies between VPPmin and 1V. The lower end of the CMR range varies 1:1 with VEE. The
numbers in the spec table assume a nominal VEE = –4.5V. Note for PECL operation, the V

CMR

(min) will be fixed at 5.0V – |V

CMR

(min)|.

MC100LVEL39 MC100EL39

MOTOROLA ECLinPS and ECLinPS Lite

DL140 — Rev 3

4–4

OUTLINE DIMENSIONS

DW SUFFIX

PLASTIC SOIC PACKAGE

CASE 751D–04

ISSUE E

MIN MINMAX MAX

MILLIMETERS INCHES

DIM

A
B
C
D
F
G

J
K
M
P
R

0.510

0.299

0.104

0.019

0.035

0.012

0.009
7

°

0.415

0.029

0.499

0.292

0.093

0.014

0.020

0.010

0.004
0

°

0.395

0.010

12.95

7.60

2.65

0.49

0.90

0.32

0.25
7

°

10.55

0.75

12.65

7.40

2.35

0.35

0.50

0.25

0.10
0

°

10.05

0.25

NOTES:

1. DIMENSIONING AND TOLERANCING PER
ANSI Y14.5M, 1982.

2. CONTROLLING DIMENSION: MILLIMETER.

3. DIMENSIONS A AND B DO NOT INCLUDE
MOLD PROTRUSION.

4. MAXIMUM MOLD PROTRUSION 0.150
(0.006) PER SIDE.

5. DIMENSION D DOES NOT INCLUDE
DAMBAR PROTRUSION. ALLOWABLE
DAMBAR PROTRUSION SHALL BE 0.13
(0.005) TOTAL IN EXCESS OF D DIMENSION
AT MAXIMUM MATERIAL CONDITION.

1.27 BSC 0.050 BSC

–A

–

–B

–

P 10 PL

1 10

1120

–T

–

D

20 PL

K

C

SEATING
PLANE

R X 45°

M

0.010 (0.25)

B

M M

0.010 (0.25) T A B

M

S S

G 18 PL

F

J

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MC100LVEL39/D

*MC100LVEL39/D*

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