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MC100EPT23
Dual Differential LVPECL to
LVTTL Translator
The MC100EPT23 is a dual differential LVPECL to LVTTL
translator. Because LVPECL (Positive ECL) levels are used only
+3.3V and ground are required. The small outline 8-lead SOIC
package and the dual gate design of the EPT23 makes it ideal for
applications which require the translation of a clock and a data signal.
The EPT23 is available in only the ECL 100K standard. Since there
are no L VPECL outputs or an external VBB reference, the EPT23 does
not require both ECL standard versions. The LVPECL inputs are
differential. Therefore, the MC100EPT23 can accept any standard
differential LVPECL input referenced from a VCC of +3.3V.
• 1.5ns T ypical Propagation Delay
• Minimum Operating Frequency > 275MHz
• Differential LVPECL Inputs
• Small Outline SOIC Package
• 24mA LVTTL Outputs
• Flow Through Pinouts
• Internal Input Resistors: Pulldown on D, Pulldown and Pullup on D
• Q Output will default LOW with inputs open or at GND
• ESD Protection: >1.2KV HBM, >150V MM
• Moisture Sensitivity Level 1, Indefinite Time Out of Drypack.
For Additional Information, See Application Note AND8003/D
• Flammability Rating: UL–94 code V–0 @ 1/8”,
Oxygen Index 28 to 34
• Transistor Count = 91 devices
D0
1
V
CC
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8
1
SO–8
D SUFFIX
CASE 751
MARKING DIAGRAM
8
KPT23
ALYW
1
*For additional information, see Application Note
AND8002/D
PIN DESCRIPTION
PIN
Q0, Q1
D0, D1, D0, D1 Differential L VPECL Inputs
V
CC
GND Ground
A = Assembly Location
L = Wafer Lot
Y = Year
W = Work Week
FUNCTION
LVTTL Outputs
Positive Supply
2
D0
LVPECL LVTTL
3
45
D1
Figure 1. 8–Lead Pinout and Logic Diagram
Semiconductor Components Industries, LLC, 1999
September, 1999 – Rev. 1.0
78Q0
6
Q1D1
GND
ORDERING INFORMATION
Device Package Shipping
MC100EPT23D SOIC 98 Units/Rail
MC100EPT23DR2 SOIC 2500 Tape & Reel
1 Publication Order Number:
MC100EPT23/D
Page 2
MC100EPT23
MAXIMUM RATINGS*
Symbol Parameter Value Unit
V
CC
V
I
I
out
T
A
T
stg
θ
JA
θ
JC
T
sol
* Maximum Ratings are those values beyond which damage to the device may occur.
DC CHARACTERISTICS (VCC = 3.3V ± 0.3V; GND = 0V; TA = –40°C to 85°C)
Symbol Characteristic Min Typ Max Unit
I
CCH
I
CCL
V
IH
V
IL
I
IH
I
IL
V
OH
V
OL
I
OS
V
IHCMR
NOTE: 100EP circuits are designed to meet the DC specifications shown in the above table after thermal equilibrium has been established. The
1. All values vary 1:1 with VCC.
2. All loading with 500 ohms to GND, CL = 20pF.
3. V
Power Supply Current (Outputs set to HIGH) 10 18 25 mA
Power Supply Current (Outputs set to LOW) 15 26 33 mA
Input HIGH Voltage (VCC = 3.3) (Note 1.) 2135 2420 mV
Input LOW Voltage (VCC = 3.3) (Note 1.) 1490 1825 mV
Input HIGH Current 150 µA
Input LOW Current D
Output HIGH Voltage (IOH = –3.0mA) (Note 2.) 2.4 V
Output LOW Voltage (IOL = 24mA) (Note 2.) 0.5 V
Output Short Circuit Current –180 –50 mA
Input HIGH Voltage Common Mode Range (Note 3.) 2.0 3.3 V
circuit is in a test socket or mounted on a printed circuit board and transverse airflow greater than 500lfpm is maintained.
min varies 1:1 with GND, max varies 1:1 with VCC.
IHCMR
Power Supply (GND = 0V) 0 to 3.8 VDC
Input Voltage (GND = 0V, VI not more positive than VCC) 0 to 3.8 VDC
Output Current Continuous
Surge
Operating Temperature Range –40 to +85 °C
Storage Temperature –65 to +150 °C
Thermal Resistance (Junction–to–Ambient) Still Air
500lfpm
Thermal Resistance (Junction–to–Case) 41 to 44 ± 5% °C/W
Solder Temperature (<2 to 3 Seconds: 245°C desired) 265 °C
D
50
100
190
130
mA
°C/W
0.5 µA
–150
AC CHARACTERISTICS (VCC = 3.3V ± 0.3V; GND = 0V)
–40°C 25°C 85°C
Symbol Characteristic Min Typ Max Min Typ Max Min Typ Max Unit
f
max
t
PLH
t
PHL
t
SK+ +
t
SK– –
t
SKPP
t
JITTER
V
PP
t
r
t
f
4. F
5. Reference (VCC = 3.3V ± 5%; GND = 0V)
6. Skews are measured between outputs under identical conditions.
7. 200mV input guarantees full logic swing at the output.
Maximum Toggle
Frequency (Note 4.)
,
Propagation Delay to
Output Differential (Note 5.)
Output–to–Output Skew++
Output–to–Output Skew– –
Part–to–Part Skew (Note 6.)
Cycle–to–Cycle Jitter TBD TBD TBD ps
Input Voltage Swing
(Differential) (Note 7.)
Output Rise/Fall Times
(20% – 80%) Q, Q
guaranteed for functionality only. VOL and VOH levels are guaranteed at DC only.
max
275 350 275 350 275 350 MHz
1.2
1.2
100 800 1200 100 800 1200 100 800 1200 mV
330 600 900 330 600 900 330 650 900 ps
1.5
1.5
60
25
500
1.8
1.8
1.2
1.2
1.5
1.5
60
25
500
1.8
1.8
1.3
1.2
1.7
1.5
60
25
500
2.2
1.8
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2
ns
ps
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MC100EPT23
P ACKAGE DIMENSIONS
SO–8
D SUFFIX
PLASTIC SOIC PACKAGE
CASE 751–06
ISSUE T
C
A
E
B
A1
D
58
0.25MB
1
H
4
e
M
h
X 45
_
q
C
A
SEATING
PLANE
0.10
L
B
SS
A0.25MCB
NOTES:
1. DIMENSIONING AND TOLERANCING PER ASME
Y14.5M, 1994.
2. DIMENSIONS ARE IN MILLIMETER.
3. DIMENSION D AND E DO NOT INCLUDE MOLD
PROTRUSION.
4. MAXIMUM MOLD PROTRUSION 0.15 PER SIDE.
5. DIMENSION B DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.127 TOTAL IN EXCESS
OF THE B DIMENSION AT MAXIMUM MATERIAL
CONDITION.
MILLIMETERS
DIM MIN MAX
A 1.35 1.75
A1 0.10 0.25
B 0.35 0.49
C 0.19 0.25
D 4.80 5.00
E
3.80 4.00
1.27 BSCe
H 5.80 6.20
h
0.25 0.50
L 0.40 1.25
0 7
q
__
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MC100EPT23
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without further notice to any products herein. SCILLC makes no warranty , representation or guarantee regarding the suitability of its products for any particular
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MC100EPT23/D
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