The MC100EPT23 is a dual differential LVPECL to LVTTL
translator. Because LVPECL (Positive ECL) levels are used only
+3.3V and ground are required. The small outline 8-lead SOIC
package and the dual gate design of the EPT23 makes it ideal for
applications which require the translation of a clock and a data signal.
The EPT23 is available in only the ECL 100K standard. Since there
are no L VPECL outputs or an external VBB reference, the EPT23 does
not require both ECL standard versions. The LVPECL inputs are
differential. Therefore, the MC100EPT23 can accept any standard
differential LVPECL input referenced from a VCC of +3.3V.
• 1.5ns T ypical Propagation Delay
• Minimum Operating Frequency > 275MHz
• Differential LVPECL Inputs
• Small Outline SOIC Package
• 24mA LVTTL Outputs
• Flow Through Pinouts
• Internal Input Resistors: Pulldown on D, Pulldown and Pullup on D
• Q Output will default LOW with inputs open or at GND
• ESD Protection: >1.2KV HBM, >150V MM
• Moisture Sensitivity Level 1, Indefinite Time Out of Drypack.
For Additional Information, See Application Note AND8003/D
• Flammability Rating: UL–94 code V–0 @ 1/8”,
Oxygen Index 28 to 34
• Transistor Count = 91 devices
D0
1
V
CC
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8
1
SO–8
D SUFFIX
CASE 751
MARKING DIAGRAM
8
KPT23
ALYW
1
*For additional information, see Application Note
AND8002/D
PIN DESCRIPTION
PIN
Q0, Q1
D0, D1, D0, D1Differential L VPECL Inputs
V
CC
GNDGround
A = Assembly Location
L = Wafer Lot
Y = Year
W = Work Week
FUNCTION
LVTTL Outputs
Positive Supply
2
D0
LVPECLLVTTL
3
45
D1
Figure 1. 8–Lead Pinout and Logic Diagram
Semiconductor Components Industries, LLC, 1999
September, 1999 – Rev. 1.0
78Q0
6
Q1D1
GND
ORDERING INFORMATION
DevicePackageShipping
MC100EPT23DSOIC98 Units/Rail
MC100EPT23DR2SOIC2500 Tape & Reel
1Publication Order Number:
MC100EPT23/D
Page 2
MC100EPT23
MAXIMUM RATINGS*
SymbolParameterValueUnit
V
CC
V
I
I
out
T
A
T
stg
θ
JA
θ
JC
T
sol
* Maximum Ratings are those values beyond which damage to the device may occur.
DC CHARACTERISTICS (VCC = 3.3V ± 0.3V; GND = 0V; TA = –40°C to 85°C)
SymbolCharacteristicMinTypMaxUnit
I
CCH
I
CCL
V
IH
V
IL
I
IH
I
IL
V
OH
V
OL
I
OS
V
IHCMR
NOTE: 100EP circuits are designed to meet the DC specifications shown in the above table after thermal equilibrium has been established. The
1. All values vary 1:1 with VCC.
2. All loading with 500 ohms to GND, CL = 20pF.
3. V
Power Supply Current (Outputs set to HIGH)101825mA
Power Supply Current (Outputs set to LOW)152633mA
Input HIGH Voltage (VCC = 3.3) (Note 1.)21352420mV
Input LOW Voltage (VCC = 3.3) (Note 1.)14901825mV
Input HIGH Current150µA
Input LOW CurrentD
Output HIGH Voltage (IOH = –3.0mA) (Note 2.)2.4V
Output LOW Voltage (IOL = 24mA) (Note 2.)0.5V
Output Short Circuit Current–180–50mA
Input HIGH Voltage Common Mode Range (Note 3.)2.03.3V
circuit is in a test socket or mounted on a printed circuit board and transverse airflow greater than 500lfpm is maintained.
min varies 1:1 with GND, max varies 1:1 with VCC.
IHCMR
Power Supply (GND = 0V)0 to 3.8VDC
Input Voltage (GND = 0V, VI not more positive than VCC)0 to 3.8VDC
Output CurrentContinuous
Surge
Operating Temperature Range–40 to +85°C
Storage Temperature–65 to +150°C
Thermal Resistance (Junction–to–Ambient)Still Air
500lfpm
Thermal Resistance (Junction–to–Case)41 to 44 ± 5%°C/W
Solder Temperature (<2 to 3 Seconds: 245°C desired)265°C
Cycle–to–Cycle JitterTBDTBDTBDps
Input Voltage Swing
(Differential) (Note 7.)
Output Rise/Fall Times
(20% – 80%) Q, Q
guaranteed for functionality only. VOL and VOH levels are guaranteed at DC only.
max
275350275350275350MHz
1.2
1.2
100800120010080012001008001200mV
330600900330600900330650900ps
1.5
1.5
60
25
500
1.8
1.8
1.2
1.2
1.5
1.5
60
25
500
1.8
1.8
1.3
1.2
1.7
1.5
60
25
500
2.2
1.8
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2
ns
ps
Page 3
MC100EPT23
P ACKAGE DIMENSIONS
SO–8
D SUFFIX
PLASTIC SOIC PACKAGE
CASE 751–06
ISSUE T
C
A
E
B
A1
D
58
0.25MB
1
H
4
e
M
h
X 45
_
q
C
A
SEATING
PLANE
0.10
L
B
SS
A0.25MCB
NOTES:
1. DIMENSIONING AND TOLERANCING PER ASME
Y14.5M, 1994.
2. DIMENSIONS ARE IN MILLIMETER.
3. DIMENSION D AND E DO NOT INCLUDE MOLD
PROTRUSION.
4. MAXIMUM MOLD PROTRUSION 0.15 PER SIDE.
5. DIMENSION B DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.127 TOTAL IN EXCESS
OF THE B DIMENSION AT MAXIMUM MATERIAL
CONDITION.
MILLIMETERS
DIM MINMAX
A1.351.75
A10.100.25
B0.350.49
C0.190.25
D4.805.00
E
3.804.00
1.27 BSCe
H5.806.20
h
0.250.50
L0.401.25
0 7
q
__
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3
Page 4
MC100EPT23
ON Semiconductor and are trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes
without further notice to any products herein. SCILLC makes no warranty , representation or guarantee regarding the suitability of its products for any particular
purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability ,
including without limitation special, consequential or incidental damages. “Typical” parameters which may be provided in SCILLC data sheets and/or
specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be
validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights nor the rights of others.
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PUBLICATION ORDERING INFORMATION
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Phone: 81–3–5487–8345
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For additional information, please contact your local Sales Representative.
MC100EPT23/D
4
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