Page 1
MC100EPT21
Differential LVPECL to
LVTTL Translator
The MC100EPT21 is a Differential LVPECL to LVTTL translator.
Because LVPECL (Positive ECL) levels are used only +3.3V and
ground are required. The small outline 8–lead SOIC package makes
the EPT21 ideal for applications which require the translation of a
clock or data signal.
The VBB output allows the EPT21 to also be used in a single–ended
input mode. In this mode the VBB output is tied to the D0
non–inverting buffer or the D0 input for an inverting buffer. If used,
the VBB pin should be bypassed to ground via a 0.01µF capacitator.
• 1.4ns Typical Propagation Delay
• 275MHz Fmax (Clock bit stream, not pseudo–random)
• Differential LVPECL inputs
• Small Outline SOIC Package
• 24mA TTL outputs
• Flow Through Pinouts
• Internal Input Resistors: Pulldown on D, Pulldown and Pullup on D
• Q Output will default LOW with inputs open or at GND
• ESD Protection: >1500V HBM, >100V MM
• V
BB
Output
• New Differential Input Common Mode Range
• Moisture Sensitivity Level 1, Indefinite T ime Out of Drypack.
For Additional Information, See Application Note AND8003/D
• Flammability Rating: UL–94 code V–0 @ 1/8”,
Oxygen Index 28 to 34
• T ransistor Count = 81 devices
1
NC
input for a
V
CC
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8
1
SO–8
D SUFFIX
CASE 751
MARKING DIAGRAM
8
KPT21
ALYW
1
*For additional information, see Application Note
AND8002/D
PIN DESCRIPTION
PIN
Q
D, D
V
CC
V
BB
GND Ground
A = Assembly Location
L = Wafer Lot
Y = Year
W = Work Week
FUNCTION
LVTTL Output
Differential LVPECL Input Pair
Positive Supply
Output Reference Voltage
2
D
LVTTL
3
LVPECL
VBB
Figure 1. 8–Lead Pinout (Top View) and Logic Diagram
Semiconductor Components Industries, LLC, 1999
September, 1999 – Rev. 1.0
45
78Q
6
NCD
GND
1 Publication Order Number:
MC100EPT21D SOIC 98 Units/Rail
MC100EPT21DR2 SOIC 2500 Tape & Reel
ORDERING INFORMATION
Device Package Shipping
MC100EPT21/D
Page 2
MC100EPT21
MAXIMUM RATINGS*
Symbol Parameter Value Unit
V
CC
V
I
I
out
I
BB
T
A
T
stg
θ
JA
θ
JC
T
sol
* Maximum Ratings are those values beyond which damage to the device may occur.
{
Use for inputs of same package only.
DC CHARACTERISTICS (VCC = 3.3V ± 0.3V; GND = 0V; TA = –40°C to 85°C)
Symbol Characteristic Min Typ Max Unit
I
CCH
I
CCL
V
IH
V
IL
I
IH
I
IL
V
OH
V
OL
I
OS
V
IHCMR
V
BB
NOTE: 100EP circuits are designed to meet the DC specifications shown in the above table after thermal equilibrium has been established. The
1. All values vary 1:1 with VCC.
2. All loading with 500 ohms to GND, CL = 20pF.
3. V
Power Supply Current (Outputs set to HIGH) 5.0 12 20 mA
Power Supply Current (Outputs set to LOW) 8.0 18 26 mA
Input HIGH Voltage (VCC = 3.3) (Note 1.) 2135 2420 mV
Input LOW Voltage (VCC = 3.3) (Note 1.) 1490 1825 mV
Input HIGH Current 150 µA
Input LOW Current D
Output HIGH Voltage (IOH = –3.0mA) (Note 2.) 2.4 V
Output LOW Voltage (IOL = 24mA) (Note 2.) 0.5 V
Output Short Circuit Current –130 –80 mA
Input HIGH Voltage Common Mode Range (Note 3.) 2.0 3.3 V
Output Voltage Reference 2.0 V
circuit is in a test socket or mounted on a printed circuit board and transverse airflow greater than 500lfpm is maintained.
min varies 1:1 with GND, max varies 1:1 with VCC.
IHCMR
Power Supply (GND = 0V) 0 to 3.8 VDC
Input Voltage (GND = 0V, VI not more positive than VCC) 0 to 3.8 VDC
Output Current Continuous
VBB Sink/Source Current
Operating Temperature Range –40 to +85 °C
Storage Temperature –65 to +150 °C
Thermal Resistance (Junction–to–Ambient) Still Air
Thermal Resistance (Junction–to–Case) 41 to 44 ± 5% °C/W
Solder Temperature (<2 to 3 Seconds: 245°C desired) 265 °C
{
Surge
500lfpm
D
50
100
± 0.5 mA
190
130
–150
mA
°C/W
0.5 µA
AC CHARACTERISTICS (VCC = 3.3V ± 0.3V; GND = 0V)
–40°C 25°C 85°C
Symbol Characteristic Min Typ Max Min Typ Max Min Typ Max Unit
f
max
t
PLH
t
PHL
t
SK++
t
SK– –
t
SKPP
t
JITTER
V
PP
t
r
t
f
4. F
5. Skews are measured between outputs under identical transitions.
Maximum Toggle
Frequency (Note 4.)
,
Propagation Delay to
Output Differential
Output–to–Output Skew++
Output–to–Output Skew– –
Part–to–Part Skew (Note 5.)
Cycle–to–Cycle Jitter TBD TBD TBD ps
Input Voltage Swing (Diff.) 150 800 1200 150 800 1200 150 800 1200 mV
Output Rise/Fall Times
(0.8V – 2.0V) Q, Q
guaranteed for functionality only. VOL and VOH levels are guaranteed at DC only.
max
275 350 275 350 275 350
1000
1000
330 500 900 330 500 900 330 500 900
1450
1400
60
25
500
1800
1800
1000
1000
1450
1400
60
25
500
1800
1800
1000
1000
1450
1400
60
25
500
1900
1900
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2
MHz
ps
ps
ps
Page 3
MC100EPT21
P ACKAGE DIMENSIONS
SO–8
D SUFFIX
PLASTIC SOIC PACKAGE
CASE 751–06
ISSUE T
C
A
A1
D
58
0.25MB
E
1
B
e
H
4
M
h
X 45
_
q
C
A
SEATING
PLANE
0.10
L
B
SS
A0.25MCB
NOTES:
1. DIMENSIONING AND TOLERANCING PER ASME
Y14.5M, 1994.
2. DIMENSIONS ARE IN MILLIMETER.
3. DIMENSION D AND E DO NOT INCLUDE MOLD
PROTRUSION.
4. MAXIMUM MOLD PROTRUSION 0.15 PER SIDE.
5. DIMENSION B DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.127 TOTAL IN EXCESS
OF THE B DIMENSION AT MAXIMUM MATERIAL
CONDITION.
MILLIMETERS
DIM MIN MAX
A 1.35 1.75
A1 0.10 0.25
B 0.35 0.49
C 0.19 0.25
D 4.80 5.00
E
3.80 4.00
1.27 BSCe
H 5.80 6.20
h
0.25 0.50
L 0.40 1.25
0 7
q
__
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MC100EPT21
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without further notice to any products herein. SCILLC makes no warranty , representation or guarantee regarding the suitability of its products for any particular
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MC100EPT21/D
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