Page 1
MC100EP139
Product Preview
÷
2/4,÷4/5/6 Clock
Generation Chip
The MC100EP139 is a low skew ÷2/4, ÷4/5/6 clock generation chip
designed explicitly for low skew clock generation applications. The
internal dividers are synchronous to each other, therefore, the common
output edges are all precisely aligned. The device can be driven by
either a differential or single–ended ECL or, if positive power supplies
are used, L VPECL input signals. In addition, by using the VBB output,
a sinusoidal source can be AC coupled into the device. If a
single–ended input is to be used, the VBB output should be connected
to the CLK
The common enable (EN) is synchronous so that the internal
dividers will only be enabled/disabled when the internal clock is
already in the LOW state. This avoids any chance of generating a runt
clock pulse on the internal clock when the device is enabled/disabled
as can happen with an asynchronous control. The internal enable
flip–flop is clocked on the falling edge of the input clock, therefore, all
associated specification limits are referenced to the negative edge of
the clock input.
Upon startup, the internal flip–flops will attain a random state;
therefore, for systems which utilize multiple EP139s, the master reset
(MR) input must be asserted to ensure synchronization. For systems
which only use one EP139, the MR pin need not be exercised as the
internal divider design ensures synchronization between the ÷2/4 and
the ÷4/5/6 outputs of a single device. All VCC and VEE pins must be
externally connected to power supply to guarantee proper operation.
• 50ps Output–to–Output Skew
• PECL mode: 3.0V to 5.5V V
• ECL mode: 0V V
• Synchronous Enable/Disable
• Master Reset for Synchronization of Multiple Chips
• Q Output will default LOW with inputs open or at V
• ESD Protection: >2KV HBM, >100V MM
• V
• New Differential Input Common Mode Range
• Moisture Sensitivity Level 2
For Additional Information, See Application Note AND8003/D
• Flammability Rating: UL–94 code V–0 @ 1/8”,
Oxygen Index 28 to 34
• Transistor Count = 758 devices
input and bypassed to ground via a 0.01µF capacitor.
with VEE = 0V
CC
with VEE = –3.0V to –5.5V
CC
Output
BB
EE
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TSSOP–20
DT SUFFIX
CASE 948E
MARKING DIAGRAM
KEP
139
ALYW
A = Assembly Location
L = Wafer Lot
Y = Y ear
W = Work Week
*For additional information, see Application Note
AND8002/D
ORDERING INFORMATION
Device Package Shipping
MC100EP139DT TSSOP 75 Units/Rail
MC100EP139DTR2 TSSOP 2500 Tape/Reel
MC100EP139DW SOIC 38 Units/Rail
MC100EP139DWR2 SOIC 2500 Tape/Reel
A = Assembly Location
WL = Wafer Lot
YY = Year
WW= Work Week
SO–20
DW SUFFIX
CASE 751D
MC100EP139
AWLYWW
This document contains information on a product under development. ON Semiconductor
reserves the right to change or discontinue this product without notice.
Semiconductor Components Industries, LLC, 1999
December, 1999 – Rev. 1
1 Publication Order Number:
MC100EP139/D
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MC100EP139
V
Q0
CC
V
CC
Q0
1920
21
EN
DIVSELb0
Figure 1. 20–Lead SOIC (Top View)
Warning: All VCC and VEE pins must be externally connected
to Power Supply to guarantee proper operation.
FUNCTION TABLES
CLK EN FUNCTION
Z
ZZ
X
Z = Low–to–High Transition
ZZ = High–to–Low Transition
DIVSELa Q0:1 OUTPUTS
0
1
DIVSELb0 Q2:3 OUTPUTS
0
1
0
1
L
H
X
Divide by 2
Divide by 4
DIVSELb1
MR
L
Divide
L
Hold Q0:3
H
Reset Q0:3
0
0
1
1
Divide by 4
Divide by 6
Divide by 5
Divide by 5
Q1 Q1 Q2 Q2 Q3 Q3 V
1718 16 15 14 13 12
43
56789
CLK
CLK MR V
V
BB
CC
DIVSELb1
PIN DESCRIPTION
PIN
CLK, CLK
EN ECL Sync Enable
MR
V
BB
Q0, Q1, Q0, Q1
Q2, Q3, Q2, Q3 ECL Diff ÷4/5/6 Outputs
DIVSELa
DIVSELb0 ECL Freq. Select Input B4/5/6
DIVSELb1 ECL Freq. Select Input B4/5/6
V
CC
V
EE
ECL Diff Clock Inputs
ECL Master Reset
ECL Reference Output
ECL Diff ÷2/4 Outputs
ECL Freq. Select Input B2/4
ECL Positive Supply
ECL Negative, 0 Supply
EE
11
10
DIVSELa
FUNCTION
DIVSELa
CLK
CLK
EN
MR
DIVSELb0
DIVSELb1
Figure 2. Logic Diagram
÷2/4
÷4/5/6
R
Q0
R
Q0
Q1
Q1
Q2
Q2
Q3
Q3
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CLK
Q (÷2)
Q (÷4)
Q (÷5)
Q (÷6)
CLK
RESET
Q (÷n)
MC100EP139
Figure 3. Timing Diagram
t
RR
Figure 4. Timing Diagram
MAXIMUM RATINGS*
Symbol Parameter Value Unit
V
EE
V
CC
V
I
V
I
I
out
I
BB
T
A
T
stg
θJA (DT Suffix) Thermal Resistance (Junction–to–Ambient) Still Air
θJC (DT Suffix) Thermal Resistance (Junction–to–Case) 23 to 41 ± 5% °C/W
θJA (DW Suffix) Thermal Resistance (Junction–to–Ambient) Still Air
θJC (DW Suffix) Thermal Resistance (Junction–to–Case) 33 to 35 ± 5% °C/W
T
sol
* Maximum Ratings are those values beyond which damage to the device may occur.
{
Use for inputs of same package only.
Power Supply (VCC = 0V) –6.0 to 0 VDC
Power Supply (VEE = 0V) 6.0 to 0 VDC
Input Voltage (VCC = 0V, VI not more negative than VEE) –6.0 to 0 VDC
Input Voltage (VEE = 0V, VI not more positive than VCC) 6.0 to 0 VDC
Output Current Continuous
VBB Sink/Source Current
Operating Temperature Range –40 to +85 °C
Storage Temperature –65 to +150 °C
Solder Temperature (<2 to 3 Seconds: 245°C desired) 265 °C
{
Surge
500lfpm
500lfpm
50
100
± 0.5 mA
140
100
90
60
mA
°C/W
°C/W
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MC100EP139
DC CHARACTERISTICS, ECL/LVECL (VCC = 0V, VEE = –5.5V to –3.0V) (Note 3.)
–40°C 25°C 85°C
Symbol Characteristic Min Typ Max Min Typ Max Min Typ Max Unit
IEE
V
OH
V
OL
V
IH
V
IL
I
IH
I
IL
NOTE: 10EP circuits are designed to meet the DC specifications shown in the above table after thermal equilibrium has been established. The
1. VCC = 0V, VEE = V
2. All loading with 50 ohms to VCC –2.0 volts.
3. Input and output parameters vary 1:1 with VCC.
Power Supply Current
(Note 1.)
Output HIGH Voltage
(Note 2.)
Output LOW Voltage
(Note 2.)
Input HIGH Voltage Single Ended –1022 –1022 –1022 mV
Input LOW Voltage Single Ended –1642 –1642 –1642 mV
Input HIGH Current 150 150 150 µA
Input LOW Current CLK
circuit is in a test socket or mounted on a printed circuit board and transverse airflow greater than 500lfpm is maintained.
EEmin
to V
CLK
, all other pins floating.
EEmax
DC CHARACTERISTICS, LVPECL (VCC = 3.3V ± 0.3V, VEE = 0V) (Note 6.)
Symbol Characteristic Min Typ Max Min Typ Max Min Typ Max Unit
IEE
V
OH
V
OL
V
IH
V
IL
I
IH
I
IL
NOTE: 10EP circuits are designed to meet the DC specifications shown in the above table after thermal equilibrium has been established. The
4. VCC = 3.0V, VEE = 0V, all other pins floating.
5. All loading with 50 ohms to VCC –2.0 volts.
6. Input and output parameters vary 1:1 with VCC.
Power Supply Current
(Note 4.)
Output HIGH Voltage
(Note 5.)
Output LOW Voltage
(Note 5.)
Input HIGH Voltage Single Ended 2277 2277 2277 mV
Input LOW Voltage Single Ended 1657 1657 1657 mV
Input HIGH Current 150 150 150 µA
Input LOW Current CLK
CLK
circuit is in a test socket or mounted on a printed circuit board and transverse airflow greater than 500lfpm is maintained.
70 85 100 70 90 105 75 95 110 mA
–1250 –1100 –895 –1250 –1100 –895 –1250 –1 100 –895 mV
–1995 –1850 –1650 –1995 –1850 –1650 –1995 –1850 –1650 mV
0.5
–150
–40°C 25°C 85°C
70 83 100 70 87 105 75 90 110 mA
2050 2200 2405 2050 2200 2405 2050 2200 2405 mV
1305 1450 1650 1305 1450 1650 1305 1450 1650 mV
0.5
–150
0.5
–150
0.5
–150
0.5
–150
0.5
–150
µA
µA
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MC100EP139
DC CHARACTERISTICS, PECL (VCC = 5.0V ± 0.5V, VEE = 0V) (Note 9.)
–40°C 25°C 85°C
Symbol Characteristic Min Typ Max Min Typ Max Min Typ Max Unit
IEE
V
OH
V
OL
V
IH
V
IL
I
IH
I
IL
NOTE: 10EP circuits are designed to meet the DC specifications shown in the above table after thermal equilibrium has been established. The
7. VCC = 5.0V, VEE = 0V, all other pins floating.
8. All loading with 50 ohms to VCC –2.0 volts.
9. Input and output parameters vary 1:1 with VCC.
Power Supply Current
(Note 7.)
Output HIGH Voltage
(Note 8.)
Output LOW Voltage
(Note 8.)
Input HIGH Voltage Single Ended 3977 3977 3977 mV
Input LOW Voltage Single Ended 3357 3357 3357 mV
Input HIGH Current 150 150 150 µA
Input LOW Current CLK
CLK
circuit is in a test socket or mounted on a printed circuit board and transverse airflow greater than 500lfpm is maintained.
AC CHARACTERISTICS (VCC = 3.0V to 5.5V; VEE = 0V) or (VCC = 0V; VEE = –3.0V to –5.5V)
Symbol Characteristic Min Typ Max Min Typ Max Min Typ Max Unit
f
max
t
PLH
t
PHL
t
SKEW
t
JITTER
t
r
t
f
t
s
t
h
V
pp
t
rr
t
pw
Maximum Toggle
Frequency (Note 10.)
,
Propagation Delay CLK, Q(DIFF)
Device Skew Q, Q
Part–to–Part (Note 11.)
Cycle–to–Cycle Jitter TBD TBD TBD ps
Output Rise and Fall Times Q, Q
(20% – 80%)
Setup Time EN, CLK
Hold Time CLK, EN
Input Voltage Swing (Diff) 300 800 1200 300 800 1200 300 800 1200 mV
Reset Recovery Time 100 ps
Minimum Pulse Width CLKMR550 450 550 450 550 450 ps
CLK, Q(SE)
MR, Q
DIVSEL, CLK
CLK, DIVSEL
70 85 100 70 90 105 75 95 110 mA
3750 3900 4105 3750 3900 4105 3750 3900 4105 mV
3005 3150 3350 3005 3150 3350 3005 3150 3350 mV
0.5
–150
–40°C 25°C 85°C
1.0 1.2 1.0 1.2 1.0 1.2 GHz
550 700 800 600 750 900 675 825 975 ps
110 180 250 125 190 275 150 215 300 ps
200
400
100
150
120 200
50 100
0.5
–150
400
150
0.5
–150
50
200
120 200
400
50 100
150
µA
ps
120 ps
50 ps
10.F
11.Skew is measured between outputs under identical transitions.
guaranteed for functionality only. VOL and VOH levels are guaranteed at DC only.
max
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MC100EP139
P ACKAGE DIMENSIONS
TSSOP–20
DT SUFFIX
20 PIN PLASTIC TSSOP PACKAGE
CASE 948E–02
ISSUE A
L
U0.15 (0.006) T
2X
L/2
PIN 1
IDENT
U0.15 (0.006) T
C
0.100 (0.004)
–T–
20X REFK
S
0.10 (0.004) V
M
S
U
T
1120
B
–U–
110
S
A
–V–
G
H
SEATING
PLANE
D
S
JJ1
N
N
DETAIL E
K
K1
SECTION N–N
0.25 (0.010)
M
F
DETAIL E
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSION A DOES NOT INCLUDE MOLD
FLASH, PROTRUSIONS OR GATE BURRS. MOLD
FLASH OR GATE BURRS SHALL NOT EXCEED
0.15 (0.006) PER SIDE.
4. DIMENSION B DOES NOT INCLUDE
INTERLEAD FLASH OR PROTRUSION.
INTERLEAD FLASH OR PROTRUSION SHALL NOT
EXCEED 0.25 (0.010) PER SIDE.
5. DIMENSION K DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.08 (0.003) TOTAL IN
EXCESS OF THE K DIMENSION AT MAXIMUM
MATERIAL CONDITION.
6. TERMINAL NUMBERS ARE SHOWN FOR
REFERENCE ONLY.
7. DIMENSION A AND B ARE TO BE
DETERMINED AT DATUM PLANE –W–.
MILLIMETERS
–W–
DIMAMIN MAX MIN MAX
B 4.30 4.50 0.169 0.177
C 1.20 0.047
D 0.05 0.15 0.002 0.006
F 0.50 0.75 0.020 0.030
G 0.65 BSC 0.026 BSC
H 0.27 0.37 0.011 0.015
J 0.09 0.20 0.004 0.008
J1 0.09 0.16 0.004 0.006
K 0.19 0.30 0.007 0.012
K1 0.19 0.25 0.007 0.010
L 6.40 BSC 0.252 BSC
M 0 8 0 8
6.60 0.260
6.40 0.252
––– –––
____
INCHES
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MC100EP139
P ACKAGE DIMENSIONS
SO–20
DW SUFFIX
20 PIN PLASTIC SOIC PACKAGE
CASE 751D–05
ISSUE F
H10X
M
B
M
0.25
D
20
1
B20X
M
SAS
T
18X
0.25
e
A
11
_
E
10
h X 45
B
B
A
SEATING
PLANE
A1
T
q
NOTES:
1. DIMENSIONS ARE IN MILLIMETERS.
2. INTERPRET DIMENSIONS AND TOLERANCES
PER ASME Y14.5M, 1994.
3. DIMENSIONS D AND E DO NOT INCLUDE MOLD
PROTRUSION.
4. MAXIMUM MOLD PROTRUSION 0.15 PER SIDE.
5. DIMENSION B DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE PROTRUSION SHALL
BE 0.13 TOTAL IN EXCESS OF B DIMENSION AT
MAXIMUM MATERIAL CONDITION.
MILLIMETERS
DIM MIN MAX
A 2.35 2.65
A1 0.10 0.25
B 0.35 0.49
C 0.23 0.32
D 12.65 12.95
E 7.40 7.60
e 1.27 BSC
H 10.05 10.55
L
C
h 0.25 0.75
L 0.50 0.90
q
0 7
__
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MC100EP139
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without further notice to any products herein. SCILLC makes no warranty , representation or guarantee regarding the suitability of its products for any particular
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MC100EP139/D
8
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