Datasheet MC10E446FN, MC100E446FN, MC100E446FNR2, MC10E446FNR2 Datasheet (Motorola)

NCNCMODED1D0

V

CCO

CL/4

CL/4V

CCO

CL/8CL/8V

CCO

NC
NC
V

CC

SOUT
SOUT
V

CCO

NC

CLK
CLK
V

BB

V

EE

SIN
SIN

SYNC

18
17
16
15
14
13
12

19202122232425

111098765

26
27
28

1
2
3
4

D3D2



SEMICONDUCTOR TECHNICAL DATA

2–1

REV 2

 Motorola, Inc. 1996

7/96

  

The MC10E/100E446 is an integrated 4-bit parallel to serial data

converter. The device is designed to operate for NRZ data rates of up to

1.3Gb/s. The chip generates a divide by 4 and a divide by 8 clock for both
4-bit conversion and a two chip 8-bit conversion function. The conversion
sequence was chosen to convert the parallel data into a serial stream
from bit D0 to D3. A serial input is provided to cascade two E446 devices
for 8 bit conversion applications. Note that the serial output data clocks off
of the negative input clock transition.

• On Chip Clock ÷4 and ÷8

• 1.5 Gb/s Typical Data Rate Capability

• Differential Clock and Serial Inputs

• V

BB

Output for Single-ended Input Applications

• Asynchronous Data Synchronization

• Mode Select to Expand to 8 Bits

• Internal 75kΩ Input Pulldown Resistors

• Extended 100E V

EE

Range of -4.2V to -5.46V

The SYNC input will asynchronously reset the internal clock circuitry.
This pin allows the user to reset the internal clock conversion unit and
thus select the start of the conversion process.

The MODE input is used to select the conversion mode of the device.
With the MODE input LOW, or open, the device will function as a 4-bit
converter. When the mode input is driven HIGH the internal load clock will
change on every eighth clock cycle thus allowing for an 8-bit conversion scheme using two E446’s. When cascaded in an 8-bit
conversion scheme the devices will not operate at the 1.3Gb/s data rate of a single device. Refer to the applications section of
this data sheet for more information on cascading the E446.

For lower data rate applications a VBB reference voltage is supplied for single-ended inputs. When operating at clock rates
above 500MHz differential input signals are recommended. For single-ended inputs the VBB pin is tied to the inverting differential
input and bypassed via a 0.01µF capacitor. The VBB provides the switching reference for the input differential amplifier . The V

BB

can also be used to AC couple an input signal, for more information on AC coupling refer to the interfacing section of the design
guide in the ECLinPS data book.

PIN NAMES

Pin Function

SIN
D0 – D3
SOUT, SOUT
CLK, CLK
CL/4, CL/4
CL/8, CL/8
MODE
SYNC

Differential Serial Data Input
Parallel Data Inputs
Differential Serial Data Output
Differential Clock Inputs
Differential ÷4 Clock Output
Differential ÷8 Clock Output
Conversion Mode 4-Bit/8-Bit
Conversion Synchronizing Input

FUNCTION TABLES

Mode Conversion

L

H

4-Bit
8-Bit





4-BIT PARALLEL/

SERIAL CONVERTER

FN SUFFIX

PLASTIC PACKAGE

CASE 776-02

Pinout: 28-Lead PLCC (Top View)

MC10E446 MC100E446

MOTOROLA ECLinPS and ECLinPS Lite

DL140 — Rev 4

2–2

LOGIC DIAGRAM

QD

SIN

SOUT
SOUT

CL/4
CL/4

0

1

SIN

CLK
CLK

D3

CLK

QD

0

1

D2

CLK

QD

0

1

D1

CLK

QD

0

1

D0

CLK

0 1

R

÷

4

R

÷

8

CL/8
CL/8

Mode

SYNC

Delay

LOAD PULSE
GENERATOR

MC10E446 MC100E446

2–3 MOTOROLAECLinPS and ECLinPS Lite

DL140 — Rev 4

DC CHARACTERISTICS (VEE = V

EE(min)

to V

EE(max)

; VCC = V

CCO

= GND)

0°C 25°C 85°C

Symbol Characteristic Min Typ Max Min Typ Max Min Typ Max Unit Condition

I

IH

Input HIGH Current 150 150 150 µA

V

OH

Output HIGH Voltage

10E (SOUT Only)

100E (SOUT Only)

–1020
–1025

–790
–830

–980

–1025

–760
–830

–910

–1025

–670
–830

V

1
1

V

BB

Output Reference Voltage 10E

100E

–1.38
–1.38

–1.27
–1.26

–1.35
–1.38

–1.25
–1.26

–1.31
–1.38

–1.19
–1.26

V

I

EE

Power Supply Current 10E

100E

126
126

151
151

126
126

151
151

126
145

151
174

mA

1. The maximum VOH limit was relaxed from standard ECL due to the high frequency output design. All other outputs are specified with the standard

10E and 100E VOH levels.

AC CHARACTERISTICS (VEE = V

EE(min)

to V

EE(max)

; VCC = V

CCO

= GND)

0°C 25°C 85°C

Symbol Characteristic Min Typ Max Min Typ Max Min Typ Max Unit Condition

F

MAX

Max Conversion Frequency 1.3 1.6 1.3 1.6 1.3 1.6 Gb/s

NRZ

t

PLH

t

PHL

Propagation Delay to Output

CLK to SOUT

1

CLK to CL/4
CLK to CL/8

SYNC to CL/4, CL/8

1020

650
800
650

1200

850

1050

850

1480
1050
1300
1100

1020

650
800
650

1200

850

1050

850

1480
1050
1300
1100

1020

650
800
650

1200

850

1050

850

1480
1050
1300
1100

ps

t

s

Setup Time

2

SIN, Dn -200 -450 -200 –450 –200 –450 ps

t

h

Hold Time

2

SIN, Dn 900 650 900 650 900 650 ps

t

RR

Reset Recovery Time SYNC 500 300 500 300 500 300 ps

t

PW

Min Pulse Width CLK, MR 300 300 300 ps

t

r

t

f

Rise/Fall Times SOUT

Other

100
200

225
425

350
650

100
200

225
425

350
650

100
200

225
425

350
650

ps 20% - 80%

1. Propagation delays measured from negative going clock edge.

2. Relative to negative clock edge.

Timing Diagrams

Timing Diagram A. 4:1 Parallel to Serial Conversion

D0–1
D1–1
D2–1
D3–1

D0–2
D1–2
D2–2
D3–2

D0–1 D1–1 D2–1 D3–1 D0–2 D1–2 D2–2 D3–2

CLK

RESET

D0
D1
D2
D3

SOUT

CL/4
CL/8

MC10E446 MC100E446

MOTOROLA ECLinPS and ECLinPS Lite

DL140 — Rev 4

2–4

Applications Information

The MC10E/100E446 is an integrated 4:1 parallel to serial
converter. The chip is designed to work with the E445 device
to provide both transmission and receiving of a high speed
serial data path. The E446 can convert 4 bits of data into a

1.3Gb/s NRZ data stream. The device features a SYNC input
which allows the user to reset the internal clock circuitry and
restart the conversion sequence (see timing diagram A).

The E446 features a differential serial input and internal
divide by 8 circuitry to facilitate the cascading of two devices
to build a 8:1 multiplexer. Figure 1 illustrates the architecture
for a 8:1 multiplexer using two E446’s; the timing diagram for
this configuration can be found on the following page. Notice
the serial outputs (SOUT) of the lower order converter feed
the serial inputs of the the higher order device. This feed
through of the serial inputs bounds the upper end of the
frequency of operation. The clock to serial output
propagation delay plus the setup time of the serial input pins
must fit into a single clock period for the cascade architecture
to function properly. Using the worst case values for these
two parameters from the data sheet, TPD CLK to SOUT =
1480ps and tS for SIN = –200ps, yields a minimum period of
1280ps or a clock frequency of 780MHz.

The clock frequency is somewhat lower than that of a
single converter, to increase this frequency some games can
be played with the clock input of the higher order E446. By
delaying the clock feeding E446A relative to the clock of
E446B the frequency of operation can be increased.

Q3Q7Q2Q6Q1Q5Q0

Q4

SOUT
SOUT

E446B

Q3Q3Q2Q2Q1Q1Q0

Q0

SIN
SIN

E446A

CLK
CLK

1000ps

1600ps

600ps

CLOCK

Tpd CLK
to SOUT

Figure 1. Cascaded 8:1 Converter Architecture

SOUT
SOUT

1000ps

Serial

Data

Parallel Data

Timing Diagram B. 8:1 Parallel to Serial Conversion

D0–1
D1–1
D2–1
D3–1

D0–2
D1–2
D2–2
D3–2

D0–1 D1–1 D2–1 D3–1 D4–1 D5–1 D6–1 D7–1

CLK

RESET

D0
D1
D2
D3

SOUT

CL/4
CL/8

D4–1
D5–1
D6–1
D7–1

D4–2
D5–2
D6–2
D7–2

D4 (D0B)

D5 (D1B)

D6 (D2B)

D7 (D3B)

D0–2

MC10E446 MC100E446

2–5 MOTOROLAECLinPS and ECLinPS Lite

DL140 — Rev 4

OUTLINE DIMENSIONS

FN SUFFIX

PLASTIC PLCC PACKAGE

CASE 776–02

ISSUE D

0.007 (0.180) T L

–M

SNSM

0.007 (0.180) T L

–M

SNSM

0.007 (0.180) T L

–M

SNSM

0.010 (0.250) T L

–M

SNSS

0.007 (0.180) T L

–M

SNSM

0.010 (0.250) T L

–M

SNSS

0.007 (0.180) T L

–M

SNSM

0.007 (0.180) T L

–M

SNSM

0.004 (0.100)

SEATING
PLANE

-T-

12.32

12.32

4.20

2.29

0.33

0.66

0.51

0.64

11.43

11.43

1.07

1.07

1.07
—
2

°

10.42

1.02

12.57

12.57

4.57

2.79

0.48

0.81
—
—

11.58

11.58

1.21

1.21

1.42

0.50

10

°

10.92
—

1.27 BSC

A
B
C
E
F
G
H
J
K
R
U
V
W
X
Y

Z
G1
K1

MIN MINMAX MAX

INCHES MILLIMETERS

DIM

NOTES:

1. DATUMS -L-, -M-, AND -N- DETERMINED
WHERE TOP OF LEAD SHOULDER EXITS
PLASTIC BODY AT MOLD PARTING LINE.

2. DIM G1, TRUE POSITION TO BE MEASURED
AT DATUM -T-, SEATING PLANE.

3. DIM R AND U DO NOT INCLUDE MOLD FLASH.
ALLOWABLE MOLD FLASH IS 0.010 (0.250)
PER SIDE.

4. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.

5. CONTROLLING DIMENSION: INCH.

6. THE PACKAGE TOP MAY BE SMALLER THAN
THE PACKAGE BOTTOM BY UP TO 0.012
(0.300). DIMENSIONS R AND U ARE
DETERMINED AT THE OUTERMOST
EXTREMES OF THE PLASTIC BODY
EXCLUSIVE OF MOLD FLASH, TIE BAR
BURRS, GATE BURRS AND INTERLEAD
FLASH, BUT INCLUDING ANY MISMATCH
BETWEEN THE TOP AND BOTTOM OF THE
PLASTIC BODY.

7. DIMENSION H DOES NOT INCLUDE DAMBAR
PROTRUSION OR INTRUSION. THE DAMBAR
PROTRUSION(S) SHALL NOT CAUSE THE H
DIMENSION TO BE GREATER THAN 0.037
(0.940). THE DAMBAR INTRUSION(S) SHALL
NOT CAUSE THE H DIMENSION TO BE
SMALLER THAN 0.025 (0.635).

VIEW S

B

U

Z

G1

X

VIEW D-D

H

K

F

VIEW S

G

C

Z

A

R

E

J

0.485

0.485

0.165

0.090

0.013

0.026

0.020

0.025

0.450

0.450

0.042

0.042

0.042
—
2

°

0.410

0.040

0.495

0.495

0.180

0.110

0.019

0.032
—
—

0.456

0.456

0.048

0.048

0.056

0.020

10

°

0.430
—

0.050 BSC

-N-

Y BRK

D

D

W

-M-

-L-

28 1

V

G1

K1

MC10E446 MC100E446

MOTOROLA ECLinPS and ECLinPS Lite

DL140 — Rev 4

2–6

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specifically disclaims any and all liability , including without limitation consequential or incidental damages. “Typical” parameters which may be provided in Motorola
data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals”
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MC10E446/D

*MC10E446/D*

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