Datasheet MC10E195FNR2, MC100E195FNR2 Datasheet (MOTOROLA)



SEMICONDUCTOR TECHNICAL DATA

Order this document

by MC10E195/D

  

The MC10E/100E195 is a programmable delay chip (PDC) designed
primarily for clock de-skewing and timing adjustment. It provides variable
delay of a differential ECL input transition.

The delay section consists of a chain of gates organized as shown in
the logic symbol. The first two delay elements feature gates that have
been modified to have delays 1.25 and 1.5 times the basic gate delay of
approximately 80 ps. These two elements provide the E195 with a
digitally-selectable resolution of approximately 20 ps. The required
device delay is selected by the seven address inputs D[0:6], which are
latched on chip by a high signal on the latch enable (LEN) control.

Because the delay programmability of the E195 is achieved by purely
differential ECL gate delays the device will operate at frequencies of >1.0
GHz while maintaining over 600 mV of output swing.

The E195 thus offers very fine resolution, at very high frequencies, that
is selectable entirely from a digital input allowing for very accurate system
clock timing.

An eighth latched input, D7, is provided for cascading multiple PDC’s
for increased programmable range. The cascade logic allows full control
of multiple PDC’s, at the expense of only a single added line to the data
bus for each additional PDC, without the need for any external gating.

• 2.0ns Worst Case Delay Range

• ≈20ps/Delay Step Resolution

• >1.0GHz Bandwidth

• On Chip Cascade Circuitry

• Extended 100E V

• 75KΩ Input Pulldown Resistors

PIN NAMES

Pin Function

IN/IN
EN
D[0:7]
Q/Q
LEN
SET MIN
SET MAX
CASCADE

Range of –4.2 to –5.46V

EE

Signal Input
Input Enable
Mux Select Inputs
Signal Output
Latch Enable
Min Delay Set
Max Delay Set
Cascade Signal





PROGRAMMABLE

DELAY CHIP

FN SUFFIX

PLASTIC PACKAGE

CASE 776-02

D2

D3 D4 D5 D6 D7 NC

25 24 23 22 21 20 19

D1

26

D0

27

LEN

28

V

EE

1

IN

2

IN

3

V

4

BB

567891011

NC NC EN

Pinout:

28-Lead PLCC

(Top View)

SET MIN

SET MAX

18

NC

17

NC

16

V

CC

15

V

CCO

14

Q

13

Q

12

V

CCO

CASCADE

CASCADE

V

BB

1

* 1.25

110

* 1.5

IN
IN

EN

LEN

SET MIN

SET MAX

* DELAYS ARE 25% OR 50% LONGER THAN

* STANDARD (STANDARD ≈ 80 PS)

04/99

0

1

D0 D1 D2 D3 D4 D5 D6 D7

 Motorola, Inc. 1999

LOGIC DIAGRAM – SIMPLIFIED

0

1

111

2–1

0

1

7 BIT LATCH

4 GATES 8 GATES 16 GATES

0

1

0

1

LEN Q

LATCH

D

REV 3

0

1

CASCADE

0

1

1

Q
Q

CASCADE
CASCADE

MC10E195 MC100E195

DC CHARACTERISTICS (VEE = VEE(min) to VEE(max); VCC = V

0°C 25°C 85°C

Symbol Characteristic Min Typ Max Min Typ Max Min Typ Max Unit Condition

I
I

IH
EE

Input HIGH Current 150 150 150 µA
Power Supply Current

10E
100E

130
130

156
156

AC CHARACTERISTICS (VEE = VEE(min) to VEE(max); VCC = V

0°C 25°C 85°C

Symbol Characteristic Min Typ Max Min Typ Max Min Typ Max Unit Notes

t

PLH

t

PHL

t

RANGE

∆t Step Delay

Lin Linearity D1 D0 D1 D0 D1 D0 7
t

SKEW

t

s

t

h

t

R

t

jit

t

r

t

f

1. Duty cycle skew guaranteed only for differential operation measured from the cross point of the input to the cross point of the output.

2. This setup time defines the amount of time prior to the input signal the delay tap of the device must be set.

3. This setup time is the minimum time that EN

±75 mV to that IN/IN

4. This hold time is the minimum time that EN

greater than ±75 mV to that IN/IN transition.

5. This release time is the minimum time that EN

the specified IN to Q propagation delay and transition times.

6. Specification limits represent the amount of delay added with the assertion of each individual delay control pin. The various combinations of

asserted delay control inputs will typically realize D0 resolution steps across the specified programmable range.

7. The linearity specification guarantees to which delay control input the programmable steps will be monotonic (i.e. increasing delay steps for

increasing binary counts on the control inputs Dn). Typically the device will be monotonic to the D0 input, however under worst case conditions
and process variation, delays could decrease slightly with increasing binary counts when the D0 input is the LSB. With the D1 input as the LSB
the device is guaranteed to be monotonic over all specified environmental conditions and process variation.

8. The jitter of the device is less than what can be measured without resorting to very tedious and specialized measurement techniques.

Propagation Delay

IN to Q; Tap = 0
IN to Q; Tap = 127
EN

to Q; Tap = 0

D7 to CASCADE

Programmable Range

tPD (max) – tPD (min)

D0 High
D1 High
D2 High
D3 High
D4 High
D5 High
D6 High

Duty Cycle Skew

t

PHL–tPLH

Setup Time

D to LEN
D to IN
EN

to IN

Hold Time

LEN to D
IN to EN

Release Time

EN

to IN
SET MAX to LEN
SET MIN to LEN

Jitter <5.0 <5.0 <5.0 ps 8
Output Rise/Fall Time

20–80% (Q)
20–80% (CASCADE)

transition.

1210

1360

1510

3200

3570

1250

1450

300

450

2000 2175 2050 2240 2375 2580

17

55
115
250
505

1000

200
800
200

5000250 5000250 5000250

300
800
800

125
300

must remain asserted after a negative going IN or positive going IN to prevent an output response

34

68
136
272
544

1088

±30 ±30 ±30

0 200

225
450

must be asserted prior to the next transition of IN/IN to prevent an output response greater than

must be deasserted prior to the next IN/IN transition to ensure an output response that meets

3970
1650

700

105
180
325
620

1190

325
650

1240
3270
1275

300

55
115
250
515

1030

800
200

300
800
800

125
300

= GND)

CCO

130
130

CCO

1390
3630
1475

450

17.5

140
280
560

1120

225
450

156
156

= GND)

1540
4030
1675

700

35
70

105
180
325
620

1220

0 200

325
650

1440
3885
1350

300

65
140
305
620

1240

800
200

300
800
800

125
300

130
150

1590
4270
1650

450

21
42

84
168
336
672

1344

0

225
450

156

mA

179

ps
1765
4710
1950

700

ps

ps 6

120
205
380
740

1450

ps

1

ps

2
3

ps

4

ps

5

ps

325
650

MOTOROLA ECLinPS and ECLinPS Lite

2–2

DL140 — Rev 4

A7

MC10E195 MC100E195

ADDRESS BUS (A0–A6)

INPUT

D2D3D4D5D6

D1
D0
LEN
V

EE

IN
IN
V

BB

E195

Chip #1

EN

SET MIN

SET MAX

CASCADE

D7

V

CC

V

CCO

V

CCO

CASCADE

Figure 1. Cascading Interconnect Architecture

Cascading Multiple E195’s

To increase the programmable range of the E195 internal
cascade circuitry has been included. This circuitry allows for
the cascading of multiple E195’s without the need for any
external gating. Furthermore this capability requires only one
more address line per added E195. Obviously cascading
multiple PDC’s will result in a larger programmable range
however this increase is at the expense of a longer minimum
delay .

Figure 1 illustrates the interconnect scheme for cascading
two E195’s. As can be seen, this scheme can easily be
expanded for larger E195 chains. The D7 input of the E195 is
the cascade control pin. With the interconnect scheme of
Figure 1 when D7 is asserted it signals the need for a larger
programmable range than is achievable with a single device.

An expansion of the latch section of the block diagram is
pictured below. Use of this diagram will simplify the
explanation of how the cascade circuitry works. When D7 of
chip #1 above is low the cascade output will also be low while
the cascade bar output will be a logical high. In this condition
the SET MIN pin of chip #2 will be asserted and thus all of the
latches of chip #2 will be reset and the device will be set at its
minimum delay. Since the RESET and SET inputs of the
latches are overriding any changes on the A0–A6 address bus
will not affect the operation of chip #2.

D2D3D4D5D6

D1
D0
LEN
V

EE

Q
Q

IN
IN
V

BB

E195

Chip #2

EN

SET MIN

SET MAX

CASCADE

D7

V

V

CCO

V

CCO

CASCADE

CC

Q
Q

OUTPUT

Chip #1 on the other hand will have both SET MIN and SET
MAX de-asserted so that its delay will be controlled entirely by
the address bus A0–A6. If the delay needed is greater than
can be achieved with 31.75 gate delays (1111111 on the
A0–A6 address bus) D7 will be asserted to signal the need to
cascade the delay to the next E195 device. When D7 is
asserted the SET MIN pin of chip #2 will be de-asserted and
the delay will be controlled by the A0–A6 address bus. Chip #1
on the other hand will have its SET MAX pin asserted resulting
in the device delay to be independent of the A0–A6 address
bus.

When the SET MAX pin of chip #1 is asserted the D0 and D1
latches will be reset while the rest of the latches will be set. In
addition, to maintain monotonicity an additional gate delay is
selected in the cascade circuitry. As a result when D7 of chip
#1 is asserted the delay increases from 31.75 gates to 32
gates. A 32 gate delay is the maximum delay setting for the
E195.

To expand this cascading scheme to more devices one
simply needs to connect the D7 input and CASCADE outputs
of the current most significant E195 to the new most significant
E195 in the same manner as pictured in Figure 1. The only
addition to the logic is the increase of one line to the address
bus for cascade control of the second PDC.

BIT 0 BIT 1 BIT 2 BIT 3 BIT 4 BIT 5 BIT 6 BIT 7

D0 Q0

LEN
Reset Reset

SET MIN

SET MAX

DL140 — Rev 4

TO SELECT MULTIPLEXERS

D1 Q1 D2 Q2 D3 Q3 D4 Q4 D5 Q5

LEN LEN LEN LEN LEN LEN LEN
Reset Reset Reset Reset Reset Reset Reset Reset Reset Reset Reset Reset Reset Reset

D6 Q6 D7 Q7

Figure 2. Expansion of the Latch Section of the E195 Block Diagram

2–3 MOTOROLAECLinPS and ECLinPS Lite

CASCADE
CASCADE

MC10E195 MC100E195

-N-

-L-

28 1

OUTLINE DIMENSIONS

FN SUFFIX

PLASTIC PLCC PACKAGE

CASE 776–02

ISSUE D

SNSM

G1

–M

SNSM

–M

0.010 (0.250) T L

–M

SNSS

0.007 (0.180) T L

Y BRK

B

0.007 (0.180) T L

U

D

Z

-M-

D

W

V

X

VIEW D-D

Z

C

G

G1

0.010 (0.250) T L

0.007 (0.180) T L

A

0.007 (0.180) T L

R

E

0.004 (0.100)

SEATING

-T-

J

PLANE

VIEW S

SNSS

–M

NOTES:

1. DATUMS -L-, -M-, AND -N- DETERMINED
WHERE TOP OF LEAD SHOULDER EXITS
PLASTIC BODY AT MOLD PARTING LINE.

2. DIM G1, TRUE POSITION TO BE MEASURED
AT DATUM -T-, SEATING PLANE.

3. DIM R AND U DO NOT INCLUDE MOLD FLASH.
ALLOWABLE MOLD FLASH IS 0.010 (0.250)
PER SIDE.

4. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.

5. CONTROLLING DIMENSION: INCH.

6. THE PACKAGE TOP MAY BE SMALLER THAN
THE PACKAGE BOTTOM BY UP TO 0.012
(0.300). DIMENSIONS R AND U ARE
DETERMINED AT THE OUTERMOST
EXTREMES OF THE PLASTIC BODY
EXCLUSIVE OF MOLD FLASH, TIE BAR
BURRS, GATE BURRS AND INTERLEAD
FLASH, BUT INCLUDING ANY MISMATCH
BETWEEN THE TOP AND BOTTOM OF THE
PLASTIC BODY.

7. DIMENSION H DOES NOT INCLUDE DAMBAR
PROTRUSION OR INTRUSION. THE DAMBAR
PROTRUSION(S) SHALL NOT CAUSE THE H
DIMENSION TO BE GREATER THAN 0.037
(0.940). THE DAMBAR INTRUSION(S) SHALL
NOT CAUSE THE H DIMENSION TO BE
SMALLER THAN 0.025 (0.635).

–M

–M

SNSM

SNSM

H

0.007 (0.180) T L

–M

SNSM

K1

K

SNSM

0.007 (0.180) T L

F

–M

VIEW S

INCHES MILLIMETERS

MIN MINMAX MAX

DIM

G1
K1

A

0.485

B

0.485

C

0.165

E

0.090

F

0.013

G

0.050 BSC

H

0.026

J

0.020

K

0.025

R

0.450

U

0.450

V

0.042

W

0.042

X

0.042

Y

—

°

Z

2

0.410

0.040

0.495

0.495

0.180

0.110

0.019

0.032
—
—

0.456

0.456

0.048

0.048

0.056

0.020

10

0.430
—

12.32

12.57

12.32

12.57

4.20

4.57

2.29

2.79

0.33

0.48

1.27 BSC

0.66

0.81

0.51

—

0.64

—

11.43

11.58

11.43

11.58

1.07

1.21

1.07

1.21

1.07

1.42

—

0.50

°

°

2

1.02

10

10.92
—

°

10.42

MOTOROLA ECLinPS and ECLinPS Lite

2–4

DL140 — Rev 4

MC10E195 MC100E195

Motorola reserves the right to make changes without further notice to any products herein. Motorola makes no warranty , representation or guarantee regarding
the suitability of its products for any particular purpose, nor does Motorola assume any liability arising out of the application or use of any product or circuit, and
specifically disclaims any and all liability, including without limitation consequential or incidental damages. “T ypical” parameters which may be provided in Motorola
data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals”
must be validated for each customer application by customer’s technical experts. Motorola does not convey any license under its patent rights nor the rights of
others. Motorola products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other
applications intended to support or sustain life, or for any other application in which the failure of the Motorola product could create a situation where personal injury
or death may occur. Should Buyer purchase or use Motorola products for any such unintended or unauthorized application, Buyer shall indemnify and hold Motorola
and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees
arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that
Motorola was negligent regarding the design or manufacture of the part. Motorola and are registered trademarks of Motorola, Inc. Motorola, Inc. is an Equal
Opportunity/Affirmative Action Employer.

How to reach us:
USA/EUROPE/Locations Not Listed: Motorola Literature Distribution; JAPAN: Motorola Japan Ltd.; SPD, Strategic Planning Office, 141,

P.O. Box 5405, Denver , Colorado 80217. 1–303–675–2140 or 1–800–441–2447 4–32–1 Nishi–Gotanda, Shinagawa–ku, Tokyo, Japan. 81–3–5487–8488

Customer Focus Center: 1–800–521–6274
Mfax: [e-mail] – TOUCHTONE 1–602–244–6609 ASIA/PACIFIC: Motorola Semiconductors H.K. Ltd.; Silicon Harbour Centre,

Motorola Fax Back System – US & Canada ONLY 1–800–774–1848 2, Dai King Street, Tai Po Industrial Estate, Tai Po, N.T., Hong Kong.

– http://sps.motorola.com/mfax/ 852–26629298

HOME PAGE: http://motorola.com/sps/

◊

Mfax is a trademark of Motorola, Inc.

MC10E195/D

2–5 MOTOROLAECLinPS and ECLinPS Lite

DL140 — Rev 4