Datasheet MB90210 Datasheet (FUJITSU)

查询MB90214供应商

FUJITSU SEMICONDUCTOR

DATA SHEET

DS07-13501-6E

16-bit Proprietary Microcontroller

CMOS

F2MC-16F MB90210 Series

MB90214/P214A/P214B/W214A/W214B/V210

■ OUTLINE

The MB90210 series is a line of 16-bit microcontrollers particularly suitable for system control of video cameras,

2

VTRs, and copiers. The F
enhanced instructions for high-level languages and supporting extended addressing modes.

MC-16F CPU integrated in this s eries is based on the F2MC*-16, while providing

The MB90210 series incorporates a variety of peripheral resources such as a PWC timer with 4 channels, a 10­bit A/D converter with 8 channels, UART serial ports with 3 channels (1 channel for CTS and 1 channel for dual
input/output pin switching), 16-bit reload timers with 8 channels, and an 8-bit PPG timer with 1 channel.

MB90P214B/W214B is under development.

2

MC stands for FUJITSU Flexible Microcontroller.

*: F

■ PACKAGE

80-pin Plastic QFP

80-pin Ceramic QFP

(FPT-80P-M06)

(FPT-80C-C02)

MB90210 Series

■ FEATURES

F2MC-16F CPU

• Minimum execution time: 62.5 ns/16-MHz oscillation (using a duty control system)

• Instruction sets optimized for controllers
Upward object-compatible with the F
Various data types (bit, byte, word, and long-word)
Instruction cycle improved to speed up operation
Extended addressing modes: 25 types
High coding efficiency
Access method (bank access with linear pointer)
Enhanced multiplication and division instructions (with signed instructions added)
Higher-precision operation using a 32-bit accumulator

• Extended intelligent I/O service (Automatic transfer function independent of instructions) access area
expanded to 64 Kbytes

• Enhanced instruction set applicable to high-level language (C) and multitasking
System stack pointer
Enhanced pointer-indirect instructions
Barrel shift instruction
Stack check function

• Increased execution speed: 8-byte instruction queue

• Powerful interrupt functions: 8 levels and 29 sources

2

MC-16(H)

Integrated Peripheral Resources

• ROM : 64 Kbytes (MB90214)
EPROM : 64 Kbytes (MB90W214A/W214B)
OTPROM: 64Kbytes (MB90P214A/P214B)

• RAM: 3 Kbytes (MB90214)

4 Kbytes (MB90P214A/P214B/W214A/W214B/V210)

• General-purpose ports: max. 65 channels

• PWC timer with time measurement function: 4 channels

• 10-bit A/D converter: 8 channels

• UART: 3 channels

• Including: 1 channel with CTS function

1 channel with I/O pin switching function

• 16-bit reload timer
Toggled output, external clock, and gate functions: 4 channels

External clock and gate functions: 4 channels

• 8-bit PPG timer: 1 channel

• DTP/External-interrupt inputs: 4 channels

• Write-inhibit RAM: 256 bytes (MB90V210: 512 bytes)

• Timebase counter: 18 bits

• Clock gear function

• Low-power consumption mode
Sleep mode
Stop mode
Hardware standby mode

2

MB90210 Series

Product Description

• MB90214 is a mask ROM product.

• MB90P214A/P214B are OTPROM products.

• MB90W214A/W214B are EPROM products. ES only.

• Operating temperature of MB90P214A/W214A is –40°C to +85°C. (Howev er, the A C characteristics is assured
in –40°C to +70°C)

• MB90V210 is a evaluation device for the program development. ES only.

3

MB90210 Series

■ PRODUCT LINEUP

Part numb er

Item

Classification Mask ROM product OTPROM product EPROM product For evaluation
ROM size 64 Kbytes 64 Kbytes 64 Kbytes —
RAM size 3 Kbytes 4 Kbytes 4 Kbytes 4 Kbytes
CPU functions The number of instructions: 412

Ports I/O ports (N-ch open-drain): 8

PWC timer Number of channels: 4

10-bit
A/D converter

MB90214

Instruction bit length: 8 or 16 bits
Instruction length: 1 to 7 bytes
Data bit length: 1, 4, 8, 16, or 32 bits
Minimum execution time: 62.5 ns/16 MHz
Interrupt processing time: 1.0 µs/16 MHz (min.)

I/O ports (CMOS): 57
Total: 65

16-bit reload timer operation (operating clock cycle: 0.25 µs to 1.31 ms)

16-bit pulse-width count operation (Allowing continuous/one-shot measurement, H/L width

measurement, inter-edge measurement, and divided-frequency measurement)

Single conversion mode (conversion for each input channel)

Scan conversion mode (continuous conversion for up to 8 consecutive channels)

Continuous conversion mode (repeated conversion for a selected channel)

Stop conversion mode (conversion every fixed cycle)

MB90P214A
MB90P214B

Resolution: 10 or 8 bits, Number of inputs: 8

MB90W214A
MB90W214B

MB90V210

UART Number of channels: 3

(1 channel with CTS function; 1 channel with I/O pin switching function)

Clock-synchronous trans fer mode

(full-duplex double buffering, 7- to 9-bit data length, 2400 to 62500 bps)

Asynchronous transfer mode

(full-duplex double buffering, 7- to 9-bit data length, 2400 to 62500 bps)

Timer Number of channels: 4 channels × 2 types

16-bit reload timer operation (operating clock cycle: 0.25 µs to 1.05 s)

8-bit PPG timer Number of channels: 1

8-bit PPG operation (operating clock cycle: 0.25 µs to 6 s)

DTP/External
interrupt

Write-inhibit RAM RAM size: 256 bytes (MB90V210: 512 bytes)

Standby mode Stop mode (activated by software or hardware) and sleep mode
Gear function Machine clock operating frequency switching: 16, 8, 4, or 1 MHz (at 16 MHz oscillation)
Package FPT-80P-M06 FPT-80C-C02 PGA-256C-A02

External interrupt mode (allowing interrupts to activate at four different request levels)

Simple DMA start mode (allowing extended I

RAM write-protectable with WI

Number of inputs: 4

2

OS to activate at two different request levels)

pin

4

MB90210 Series

■ DIFFERENCES BETWEEN MB90214 (MASK ROM PRODUCT) AND MB90P214A/P214B/

W214A/W214B

Part numb er

Item

ROM Mask ROM

Pin function
43 pins

Note: MB90V210, device used for evaluation, is not warranted for electrical specifications.

MB90214

64 Kbytes

MD2 pin MD2/V

MB90P214A
MB90P214B

OTPROM
64 Kbytes

PP pin

MB90W214A
MB90W214B

EPROM

64 Kbytes

5

MB90210 Series

■ PIN ASSIGNMENT

X0

VSSRST

6463626160595857565554535251504948474645444342

P57/WI

P56/RD

P55/WRL

P54/WRH/CTS0/INT3

P53/HRQ

P52/HAK

P51/RDY

P50/CLK

(Top view)

P82/INT2/ATG

P81/INT1

P80/INT0

P75/SOD0

P74/SID0

P73/SCK0

P72/SOD1

P71/SID1

P70/SCK1

HST

MD2

MD1

MD0

41

X1

CC

V
P00/D00
P01/D01
P02/D02
P03/D03
P04/D04
P05/D05
P06/D06
P07/D07
P10/D08

P11/D09
P12/D10
P13/D11
P14/D12
P15/D13

65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80

123456789

P17D15

P16D14

P20A00/TIN0

P23/A03/TIN3

P24/A04/TIN4

P21/A01/TIN1

P25/A05/TIN5

P22/A02/TIN2

101112131415161718192021222324

SS

PPG

I D3

K2

I D2

P30/A08

P26/A06/TIN6

P27/A07/TIN7

P32/A10/TOUT0

P36/A14/SCK3

P37/A15/S

P33/A11/TOUT1

P34/A12/TOUT2

P40/A16/SOD3

P35/A13/TOUT3

P41/A17/SC

P42/A18/S

31/A09/
P

V

(FPT-80P-M06)
(FPT-80C-C02)

40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25

OD2

PWC0/POUT0

P43/A19/S

P44/A20/

P67/AN7
P66/AN6
P65/AN5
P64/AN4
P63/AN3
P62/AN2

SS

V
P61/AN1
P60/AN0

SS

AV
AVRL
AVRH

CC

AV
PWC3/P47/A23/POUT3
PWC2/P46/A22/POUT2
PWC1/P45/A21/POUT1

6

■ PIN DESCRIPTION

MB90210 Series

Pin no.

QFP*

64,

65
62 RST
66 V

11,
34,

63

67 to 74 P00 to P07 B General-purpose I/O ports

75 to 80,

1,

2

3 to 6 P20 to P23 E General-purpose I/O ports

7 to 10 P24 to P27 E General-purpose I/O ports

12 P30 E General-purpose I/O port

Pin name

X0,
X1

CC

SS

V

D00 to D07 I/O pins for the lower eight bits of external data bus

P10 to P15,
P16,
P17

D08 to D13,
D14,
D15

A00 to A03 Output pins for external address buses A00 to A03

TIN0 to TIN3 16-bit reload timer 1 (ch.0 to ch.3) input pins

A04 to A07 Output pins for external address buses A04 to A07

TIN4 to TIN7 16-bit reload timer 2 (ch.4 to ch.7) input pins

A08 Output pin for external address bus A08

Circuit

type

A Crystal oscillator pins (16 MHz)

H External reset request input pin

Power supply
Power supply

B General-purpose I/O ports

Digital circuit power supply pin
Digital circuit grounding level

These ports are available only in the single-chip mode.

These pins are available in an external-bus mode.

These ports are available in the single-chip mode and in an
external-bus mode with the 8-bit data bus specified.

I/O pins for the upper eight bits of external data bus
These pins are available in an external-bus mode with the 16-bit

data bus specified.

These ports are available only in the single-chip mode.

These pins are available in an external-bus mode.

These pins are available when the 16-bit reload timer 1 (ch.0 to
ch.3) input specification is “enabled”. The data on the pin is read
as the 16-bit reload timer 1 (ch.0 to ch.3) input (TIN0 to TIN3).

These ports are available only in the single-chip mode.

These pins are available in an external-bus mode.

These pins are available when the 16-bit reload timer 2 (ch.4 to
ch.7) input specification is “enabled”. The data on the pin is read
as the 16-bit reload timer 2 (ch.4 to ch.7) input (TIN4 to TIN7).

This port is available in the single-chip mode or when the middle
address control register setting is “port.”

This pin is available in an external-bus mode and when the middle
address control register set to “address.”

Function

* :FPT-80P-M06, FPT-80C-C02

(Continued)

7

MB90210 Series

Pin no.

Pin name

QFP*

13 P31 E General-purpose I/O port

A09 Output pin for external address bus A09

PPG PPG timer output pin

14 to 17 P32 to P35 E General-purpose I/O ports

A10 to A13 Output pins for external address buses A10 to A13

Circuit

type

This port is available in the single-chip mode or when the middle
address control register setting is “port”, with the 8-bit PPG
output is disabled.

This pin is available in an external-bus mode and when the middle
address control register setting is “address.”

This pin is available when the PPG operation mode control
register specification is the PPG output pin.

These ports are available in the single-chip mode or when the
middle address control register setting is “port”, with the 16-bit
reload timer 1 (ch.0 to ch.3) output is disabled.

These pins are available in an external-bus mode and when the
middle address control register setting is “address.”

Function

TOUT0 to TOUT3 16-bit reload timer 1 (ch.0 to ch.3) output pin

These pins are available when the 16-bit reload timer 1 (ch.0 to
ch.3) is output operation.

18 P36 E General-purpose I/O port

This port is available when the UART (ch.2) clock output is
disabled either in the single-chip mode or when the middle
address control register setting is “port.”

A14 Output pin for external address bus A14

This pin is available when the UART (ch.2) clock output is
disabled in an external-bus mode and when the middle address
control register setting is “address.”

SCK3 UART (ch.2) clock output pin (SCK3)

This pin is available when the UART (ch.2) clock output is
enabled.
UART (ch.2) external clock input pin (SCK3)
This pin is available when the port is in input mode and the UART
(ch.2) specification is external clock mode.

19 P37 E General-purpose I/O port

This port is available in the single-chip mode or when the middle
address control register setting is “port.”

A15 Output pin for external address bus A15

This pin is available in an external-bus mode and when middle
address control register setting is “address.”

SID3 UART (ch.2) serial data input pin (SID3)

* :FPT-80P-M06, FPT-80C-C02

8

Since this input is used whenever the SID3 is in input operation,
the output by any other function must be suspended unless the
output is intentionally performed.

(Continued)

Pin no.

Pin name

QFP*

20 P40 E General-purpose I/O port

A16 Output pin for external address bus A16

SOD3 UART (ch.2) serial data output pin (SOD3)

21 P41 E General-purpose I/O port

A17 Output pin for external address bus A17

SCK2 UART (ch.2) clock output pin (SCK2)

Circuit

type

This port is available when the UART (ch.2) serial data output
from SOD3 is disabled either in the single-chip mode or when the
upper address control register setting is “port.”

This pin is available when the UART (ch.2) serial data output
from SOD3 is disabled in an external-bus mode and when the
upper address control register setting is “address.”

This pin is available when the UART (ch.2) serial data output is
enabled.

This port is available when the UART (ch.2) clock output is
disabled either in the single-chip mode or when the upper
address control register setting is “port.”

This pin is available when the UART (ch.2) clock output is
disabled in an external-bus mode and when the upper address
control register setting is “address.”

This pin is available when the UART (ch.2) clock output is
enabled.
UART (ch.2) external clock input pin (SCK2)
This pin is available when the port is in input mode and the UART
(ch.2) specification is external clock mode.

MB90210 Series

Function

22 P42 E General-purpose I/O port

This port is available in the single-chip mode or when the upper
address control register setting is “port.”

A18 Output pin for external address bus A18

This pin is available in an external-bus mode and when the upper
address control register setting is “address.”

SID2 UART (ch.2) serial data input pin (SID2)

Since this input is used whenever the SID2 is in input operation,
the output by any other function must be suspended unless the
output is intentionally performed.

23 P43 E General-purpose I/O port

This port is available when the UART (ch.2) serial data output
from SOD2 is disabled either in the single-chip mode or when the
upper address control register setting is “port.”

A19 Output pin for external address bus A19

This pin is available when the UART (ch.2) serial data output
from SOD2 is disabled in an external-bus mode and when the
upper address control register setting is “address.”

SOD2 UART (ch.2) serial data output pin (SOD2)

This pin is available when the UART (ch.2) serial data output
from SOD2 is enabled.

* :FPT-80P-M06, FPT-80C-C02

(Continued)

9

MB90210 Series

Pin no.

Pin name

QFP*

24 PWC0 E PWC timer input pin

POUT0 PWC timer output pin

25 P45 E General-purpose I/O port

A21 Output pin for external address bus A21

PWC1 PWC timer data sample input pin

POUT1 PWC timer output pin

26 P46 E General-purpose I/O port

A22 Output pin for external address bus A22

PWC2 PWC timer input pin

POUT2 PWC timer output pin

27 P47 E General-purpose I/O port

A23 Output pin for external address bus A23

PWC3 PWC timer input pin

POUT3 PWC timer output pin

Circuit

type

Since this input is used whenever the PWC0 timer is in input
operation, the output by any other function must be suspended
unless the output is intentionally performed.

This pin is available when the PWC0 is output operation.

This port is available in the single-chip mode or when the upper
address control register setting is “port.”

This pin is available in an external-bus mode and when the upper
address control register setting is “address.”

Since this input is used whenever the PWC1 timer is in input
operation, the output by any other function must be suspended
unless the output is intentionally performed.

This pin is available when the PWC1 is output operation.

This port is available in the single-chip mode or when the upper
address control register setting is “port.”

This pin is available in an external-bus mode and when the upper
address control register setting is “address.”

Since this input is used whenever the PWC2 timer is in input
operation, the output by any other function must be suspended
unless the output is intentionally performed.

This pin is available when the PWC2 is output operation.

This port is available in the single-chip mode or when the upper
address control register setting is “port.”

This pin is available in an external-bus mode and when the upper
address control register setting is “address.”

Since this input is used whenever the PWC3 timer is in input
operation, the output by any other function must be suspended
unless the output is intentionally performed.

This pin is available when the PWC3 is output operation.

Function

* :FPT-80P-M06, FPT-80C-C02

10

(Continued)

Pin no.

Pin name

QFP*

54 P50 E General-purpose I/O port

CLK CLK output pin

55 P51 E General-purpose I/O port

RDY Ready signal input pin

56 P52 E General-purpose I/O port

Circuit

type

This port is available in the single-chip mode and when the CLK
output is disabled.

This pin is available in an external-bus mode with the CLK output
enabled.

This port is available in the single-chip mode or when the ready
function is disable.

This pin is available in an external-bus mode and when the ready
function is enabled.

This port is available in the single-chip mode or when the hold
function is disabled.

MB90210 Series

Function

HAK

57 P53 E General-purpose I/O port

HRQ Hold request input pin

58 P54 D General-purpose I/O port

CTS0 UART (ch.0) clear-to-send input pin

Hold acknowledge output pin
This pin is available in an external-bus mode and when the hold

function is enabled.

This port is available in the single-chip mode or when the hold
function is disabled in an external-bus mode.

This pin is available in an external-bus mode and when the hold
function is enabled.
Since this input is used during this operation at any time, the
output by any other function must be suspended unless the
output is intentionally performed.

This port is available in the single-chip mode, in the external bus
8-bit mode, or when the WRH
When these pins are open in input mode, through current may
leak in stop mode/reset mode, be sure to fix these pins to V
level to use these pins in input mode.

Since this input is used whenever the UART (ch.0) CTS function
is enabled, the output by any other function must be suspended
unless the output is intentionally performed.
When these pins are open in input mode, through current may
leak in stop mode/reset mode, be sure to fix these pins to V
level to use these pins in input mode.

pin output is disabled.

CC/VSS

CC/VSS

WRH

* :FPT-80P-M06, FPT-80C-C02

Write strobe output pin for the upper eight bits of data bus
This pin is available in the external bus 16-bit mode with the
WRH

pin output enabled in an external-bus mode.

(Continued)

11

MB90210 Series

Pin no.

Pin name

QFP*

58 INT3 D External interrupt request input pin

59 P55 E General-purpose I/O port

Circuit

type

Since this input is used whenever external interrupts are enabled,
the output by any other function must be suspended unless the
output is intentionally performed.
When these pins are open in input mode, through current may
leak in stop mode/reset mode, be sure to fix these pins to V
level to use these pins in input mode.

This port is available in the single-chip mode or when the WRL
pin output is disabled.

Function

CC/VSS

WRL

Write strobe output pin for the lower eight bits of data bus
This pin is available in an external-bus mode and when the WRL
pin output is enabled.

60 P56 E General-purpose I/O port

This port is available in the single-chip mode.

RD

Data bus read strobe output pin
This pin is available in an external-bus mode.

61 P57 D General-purpose I/O port

This port is always available.
When these pins are open in input mode, through current may
leak in stop mode/reset mode, be sure to fix these pins to V
level to use these pins in input mode.

WI

RAM write disable request input
Since this input is used during this operation at any time, the
output by any other function must be suspended unless the
output is intentionally performed.
When these pins are open in input mode, through current may
leak in stop mode/reset mode, be sure to fix these pins to V
level to use these pins in input mode.

32,
33,

35 to 40

P60,
P61,
P62 to P67

AN0,
AN1,
AN2 to AN7

C Open-drain I/O ports

These ports are available when the analog input enable register
setting is “port.”

10-bit A/D converter analog input pins
These pins are available when the analog input enable register

setting is “analog input.”

CC/VSS

CC/VSS

41 to 43 MD0 to MD2 F Operation mode select signal input pins

Connect these pins directly to V

44 HST

G Hardware standby input pin

45 P70 E General-purpose I/O port

This port is available when the UART (ch.1) clock output is
disabled.

* :FPT-80P-M06, FPT-80C-C02

12

CC or VSS.

(Continued)

Pin no.

Pin name

QFP*

45 SCK1 E UART (ch.1) clock output pin

46 P71 E General-purpose I/O port

SID1 UART (ch.1) serial data input pin

47 P72 E General-purpose I/O port

Circuit

type

This pin is available when the UART (ch.1) clock output is
enabled.
UART (ch.1) external clock input pin
This pin is available when the port is in input mode and the UART
(ch.1) specification is external clock mode.

This port is always available.

Since this input is used whenever the UART (ch.1) is in input
operation, the output by any other function must be suspended
unless the output is intentionally performed.

This port is available when the UART (ch.1) serial data output is
disabled.

MB90210 Series

Function

SOD1 UART (ch.1) serial data output pin

This pin is available when the UART (ch.1) serial data output is
enabled.

48 P73 E General-purpose I/O port

This port is available when the UART (ch.0) clock output is
disabled.

SCK0 UART (ch.0) clock output pin

This pin is available when the UART (ch.0) clock output is
enabled.
UART (ch.0) external clock input pin
This pin is available when the port is in input mode and the UART
(ch.0) specification is external clock mode.

49 P74 E General-purpose I/O port

This port is always available.

SID0 UART (ch.0) serial data input pin

Since this input is used whenever the UART (ch.0) is in input
operation, the output by any other function must be suspended
unless the output is intentionally performed.

50 P75 E General-purpose I/O port

This port is available when the UART (ch.0) serial data output is
disabled.

SOD0 UART (ch.0) serial data output pin

This pin is available when the UART (ch.0) serial data output is
enabled.

51,

52

P80,
P81

D General-purpose I/O port

This port is always available.
When these pins are open in input mode, through current may
leak in stop mode/reset mode, be sure to fix these pins to V
level to use these pins in input mode.

CC/VSS

* :FPT-80P-M06, FPT-80C-C02

(Continued)

13

MB90210 Series

(Continued)

Pin no.

QFP*

51,

52

Pin name

INT0,
INT1

Circuit

type

D External interrupt request input pin

Since this input is used whenever external interrupts are enabled,
the output by any other function must be suspended unless the
output is intentionally performed.
When these pins are open in input mode, through current may
leak in stop mode/reset mode, be sure to fix these pins to V
level to use these pins in input mode.

53 P82 D General-purpose I/O port

This port is always available.
When these pins are open in input mode, through current may
leak in stop mode/reset mode, be sure to fix these pins to V
level to use these pins in input mode.

INT2 External interrupt request input pin

Since this input is used whenever external interrupts are enabled,
the output by any other function must be suspended unless the
output is intentionally performed.
When these pins are open in input mode, through current may
leak in stop mode/reset mode, be sure to fix these pins to V
level to use these pins in input mode.

ATG

10-bit A/D converter trigger input pin
When these pins are open in input mode, through current may
leak in stop mode/reset mode, be sure to fix these pins to V
level to use these pins in input mode.

28 AV

CC

Power supply

Analog circuit power supply pin
This power supply must be turned on or off with a potential equal
to or higher than AV

29 AVRH

Power supply

Be sure that AV
Analog circuit reference voltage input pin

CC= VCC before use and during operation.

This pins must be turned on or off with a potential equal to or

higher than AVRH applied to AV
30 AVRL
31 AV

SS

Power supply
Power supply

Analog circuit reference voltage input pin

Analog circuit grounding level

Function

CC/VSS

CC/VSS

CC/VSS

CC/VSS

CC applied to VCC.

CC.

* :FPT-80P-M06, FPT-80C-C02

14

MB90210 Series

■ I/O CIRCUIT TYPE

Type Circuit Remarks

A • Oscillation feedback resistor: Approx.1 MΩ

X1

MB90214
MB90P214B

X0

Standby control

X1

MB90W214B

• Oscillation feedback resistor: Approx.1 MΩ
MB90P214A
MB90W214A

X0

Standby control

B • CMOS-level I/O

R

Digital output

Standby control provided
MB90214: With or without pull-up/pull-down

reisistor optional

R

R

Digital output

Digital input

MB90P214A/P214B: Without pull-up/pull-down

resistor

MB90W214A/W214B: Without pull-up/pull-down

resistor

Standby control

C • N-ch open-drain output

• CMOS-level hysteresis input
A/D control provided

R

Digital output

A/D input
Digital input

D • CMOS-level output

R

Digital output

• CMOS-level hysteresis input
Standby control not provided
MB90214: With or without pull-up/pull-down

reisistor optional

R

R

Digital output

Digital input

MB90P214A/P214B: Without pull-up/pull-down

resistor

MB90W214A/W214B: Without pull-up/pull-down

resistor

(Continued)

15

MB90210 Series

(Continued)

Type Circuit Remarks

E • CMOS-level output

R

Digital output

R

R

Digital output

Digital input

F • CMOS-level input with no standby control

R

Digital input

• CMOS-level hysteresis input
Standby control provided
MB90214: With or without pull-up/pull-down

reisistor optional

MB90P214A/P214B: Without pull-up/pull-down

resistor

MB90W214A/W214B: Without pull-up/pull-down

resistor

Mask ROM products only:
MD2: With pull-down resistor
MD1: With pull-up resistor
MD0: With pull-down resistor

• COMS-level input with no standby control
MD2 of OTPROM products/EPROM products

R

Digital input
VPP power supply

only

G • CMOS-level hysteresis input

Standby control not provided

• With input analog filter (40 ns Typ.)

R

Analog filter

H • CMOS-level hysteresis input

Pull-up
resistor

Digital input

Standby control not provided

• With input analog filter (40 ns Typ.)

R

• With pull-up resistor
MB90214: With or without pull-up/pull-down

resistor optional

R

Analog filter

Digital input

MB90P214A/W214A/P 214B /W214 B:

With pull-up resistor

: P-type transistor

: N-type transistor

Note: The pull-up and pull-down resistors are always connected, regardless of the state.

16

MB90210 Series

■ HANDLING DEVICES

1. Preventing Latchup

CMOS ICs may c ause latch up when a voltag e higher t han VCC or lower th an VSS is appl ied to i nput or ou tput
pins, or when a voltage exceeding the rating is applied between V

If latch-up occurs, the power supply current increases rapidly, sometimes resulting in thermal breakdown of the
device. Use meticulous care not to let any voltage exceed the maximum rating.

CC and VSS.

Also, take care to prevent the analog power supply (AV
power supply (V

CC) when the analog system power supply is turned on and off.

CC and A VRH) and analog input from exceeding the digital

2. Treatment of Unused Input Pins

Leaving unused input pins open could cause malfunctions. They should be connected to a pull-up or pull-down
resistor .

3. Treatment of Pins when A/D is not Used

Connect to be AVCC = AVRH = VCC and AVSS = AVRL = VSS even if the A/D converter is not in use.

4. Precautions when Using an External Clock

To reset the internal c ircuit properly by the Lo w-level input to the RST pin , the “L” level input to th e RST pin
must be maintained for at least five machine cycles. Pay attention to it if the chip uses external clock input.

5. VCC and VSS Pins

Apply equal potential to the VCC and VSS pins.

6. Supply Voltage Variation

The operation assurance range for the VCC supply voltage is as given in the ratings. Howev er, sudden changes
in the supply voltage can cause miso peration, even if the voltage remains within the rated range. Therefore, it
is impor tant to su pply a stable voltage to t he IC. The recommende d power supply co ntrol guideli nes are that
the commercial frequency (50 to 6 0 Hz) ripple var iation (P-P value) on V
standard V

CC value and that the transient rate of change during sudden changes, such as during power supply

switching, should be less than 0.1 V/ms.

CC should be less than 10% of the

7. Notes on Using an External Clock

When using an external clock, drive the X0 pin as illustrated below. When an external clock is used, oscillation
stabilization time is required even for power-on reset and wake-up from stop mode.

• Use of External Clock

MB90210

X0

X1

Note: When using an external clock, be sure to input external clock more than 6 machine cycles after

setting the HST pin to “L” to transfer to the hardware standby mode.

17

MB90210 Series

8. Power-on Sequence for A/D Converter Power Supplies and Analog Inputs

Be sure to turn on the digital power supply (VCC) before applying voltage to the A/D conver ter power supplies
(AV

CC, AVRH, and AVRL) and analog inputs (AN0 to AN7).

When turning power supplies off, turn off the A/D converter power supplies (A V
inputs (AN0 to AN7) first, then the digital power supply (V

When turning AVRH on or off, be careful not to let it exceed AV

CC).

CC.

CC, A VRH, and A VRL) and analog

18

MB90210 Series

■ PROGRAMMING FOR MB90P214A/P214B/W214A/W214B

In EPROM mode, the MB9 0P214A/P214B/W214A/W214B func tions equivalent to the MBM27C1000. This
allows the EPROM to be programmed with a general-pur pose EPROM programmer by using the dedicated
socket adapter (do not use the electronic signature mode).

1. Program Mode

When shipped from Fujitsu, an d after eac h erasure, all bits (64 K × 8 bits) in the MB9 0P214A /P214 B/W214 A/
W214B are in the “1” sta te. Data is written to the ROM by selectively programming “0’s” into the desired bit
locations. Bits cannot be set to “1” electrically.

2. Programming Procedure

(1) Set the EPROM programmer to MBM27C1000.
(2) Load program data into the EPROM programmer at 10000

H to 1FFFFH.

Note that ROM addresses FF0000
W214B series assign to 10000

FFFFFFH

FF0000

H

Operation mode EPROM mode

* : Be sure to set the programming, the start address and the stop address on the EPROM programmer to 10000H/1FFFFH.

H to FFFFFFH in the operation mode in the MB90P214A/P214B/W214A/

H to 1FFFFH in the EPROM mode (on the EPROM programmer).

H*

1FFFF

10000H*

(Corresponding addresses on the EPROM mode)

(3) Mount the MB90P214A/P214B/W214A/W214B on the adapter socket, then fit the adapter socket onto the

EPROM programmer. When mounting the device and the adapter socket, pay attention to their mounting

orientations.
(4) Start programming the program data to the device.
(5) If programming has not successfully resulted, connect a capacitor of approx. 0.1 µF between V

between V

PP and GND.

CC and GND,

(6) Since the MB90P214A and MB90W214A have CMOS-level input, programming to them may be impossible

depending on the output level of the general-purpose programmer. In that case, connect a pull-up resistor

to the adapter socket side.

Note: The mask ROM products (MB90214) d oes not sup por t EPROM mo de. Data cannot , therefore, be read by

the EPROM programmer.

19

MB90210 Series

3. EPROM Programmer Socket Adapter and Recommended Programmer Manufacturer

Part No. MB90P214B
Package QFP-80
Compatible socket adapter

Sun Hayato Co., Ltd.
Recommended

programmer
manufacturer
and programmer
name

Inquiry: Sun Hayato Co., Ltd.: TEL: [phone]

Advantest Corp.: TEL: Except JAPAN (81)-3-3930-4111

Advantest corp.

FAX: [phone]

R4945A

(main unit)

R49451A
(adapter)

+

ROM-80QF-32DP-16F

Recommended

4. Erase Procedure

Data written in the MB90W214A/W214B are erased (from “0” to “1”) by exposing the chip to ultraviolet rays with
a wavelength of 2,537 Å through the translucent cover.

2

Recommended irradiati on dosage for exposure is 10 Wsec/cm
with a commercial ultraviolet lamp positioned 2 to 3 cm above the package (when the package surface
illuminance is 1200 µW/cm

If the ultraviolet lamp has a filter, remove the filter before exposure. Attaching a mirrored plate to the la mp
increases the illuminance by a factor of 1.4 to 1.8, thus shortening the required erasure time. If the translucent
par t of the package is stained with oil o r adhesive, transmiss ion of ultraviolet rays is de graded, resulting in a
longer erasure time. In that case, clean the t ranslucent part usi ng alcohol (or other solvent not affecting the
package).

2

).

. This amount is reached in 15 to 20 mi nutes

The above recommended dosage is a value which takes the guard band into consideration and is a multiple of
the time in which all bits can be evaluated to have been erased. Observe the recommended dosage for erasure;
the purpo se of the guard band is to ensure erasur e in all temperature and supply voltage ranges. In addition,
check the life span of the lamp and control the illuminance appropriately.

Data in the MB90W214A/W214B are erased by exposure to light with a wavelength of 4000 Å or less.
Data in the device is also erased even by exposure to fluorescent lamp light or sunlight although the exposure

results in a much lower erasure rate than exposure to 2537 Å ultraviolet rays. Note that ex posure to such lights
for an extended period will therefore affect system reliability. If the chip is used where it is exposed to any light
with a wavelength of 4000 Å or less, cover the translucent part, for example, with a protective seal to prevent
the chip from being exposed to the light.

Exposure to light with a wavelength of 4,000 to 5,000 Å or more will not erase data in the device. If the light
applied to the chip has a ver y high illuminance, however, the device may cause malfunction in the circuit for
reasons of general semiconductor characteristics. Although the circuit will recover normal operation when
exposure is stopped, the device require s proper co unter meas ures for use in a place exposed continuously to
such light even though the wavelength is 4,000 Å or more.

20

MB90210 Series

5. Recommended Screening Conditions

High temperature aging is recommended as the pre-assembly screening procedure.

Program, verify

Aging

+150°C, 48 Hrs.

Data verification

Assembly

6. Programming Yeild

MB90P214A/P214B cannot be write-tested for all bits due to their nature. Therefore the write yield cannot always
be guaranteed to be 100%.

7. Pin Assignment in EPROM Mode

(1) Pins compatible with MBM27C1000

MBM27C1000

MB90P214A, MB90P214B,

MB90W214A, MB90W214B

MBM27C1000

Pin no. Pin name Pin no. Pin name Pin no. Pin name Pin no. Pin name

1V

PP 43 MD2 (VPP)32 VCC

2 OE 59 P55 31 PGM 60 P56
3A1519P37 30N.C.
4 A12 16 P34 29 A14 18 P36
5 A07 10 P27 28 A13 17 P35
6 A06 9 P26 27 A08 12 P30
7 A05 8 P25 26 A09 13 P31
8 A04 7 P24 25 A11 15 P33

9 A03 6 P23 24 A16 20 P40
10 A02 5 P22 2 3 A10 14 P32
11 A01 4 P21 2 2 CE 58 P54
12 A00 3 P20 2 1 D07 74 P07
13 D00 67 P00 20 D06 73 P06

MB90P214A, MB90P214B,

MB90W214A, MB90W214B

14 D01 68 P01 19 D05 72 P05
15 D02 69 P02 18 D04 71 P04
16 GND 17 D03 70 P03

21

MB90210 Series

(2) Power supply and ground connection pins

Type Pin no. Pin name

Power supply 41

42
44
66

MD0
MD1
HST
VCC

GND 11

30
31
34
56
57
62
63

(3) Pins other than MBM27C1000-compatible pins

Pin no. Pin name Treatment

64 X0 Pull up to 4.7 kΩ.
65 X1 Open

1
2

21

to
27
28
29
32
33
35

to
40
45

to
50
51
to
53
54
55
61
75

to
80

P16
P17
P41
to
P47
AV

CC

AVRH
P60
P61
P62
to
P67
P70
to
P75
P80
to
P82
P50
P51
P57
P10
to
P15

Connect a pull-up resistor of approximately 1 MΩ to each pin.

V

SS

AVRL

SS

AV
VSS
P52
P53
RST
VSS

22

■ BLOCK DIAGRAM

X1
X0
RST
HST
MD2
MD1
MD0

WI

CTS0
SCK3
SID3
SOD3
SCK2
SID2
SOD2
SCK1
SID1
SOD1
SCK0
SID0
SOD0

TOUT0 to
TOUT3
TIN0 to
TIN3

7

13

8

Clock controller

Write-inhibit

RAM

UART × 3

16-bit
timer 1
× 4

PWC
timer

× 4

Internal data bus

DTP/External
interrupt

× 4

External bus
interface

2

F

MC-16F

CPU

MB90210 Series

4

PWC0 to PWC3
/POUT0 to POUT3

4

4

INT0 to INT3

D00 to D15
A00 to A23
CLK
RDY

47

HAK
HRQ
WRH
WRL
RD

TIN4 to
TIN7

ATG
AN0 to
AN7
AV

CC

AVRH
AVRL
AVSS

P00 to P07
P10 to P17
P20 to P27
P30 to P37
P40 to P47
P50 to P57
P60 to P67
P70 to P75
P80 to P82

PPG

13

4

16-bit
timer 2
× 4

10-bit
A/D converter
8 ch.

65

8-bit

I/O port

PPG timer

8-bit

8-bit
PPG timer

PPG timer

RAM

ROM

23

MB90210 Series

■ PROGRAMMING MODEL

Dedicated Registers

AH

AL

USP
SSP
PS

PC
USPCU
SSPCU
USPCL
SSPCL

DPR

PCB
DTB
USB
SSB
ADB

Accumulator

User stack pointer
System stack pointer
Processor status
Program counter
User stack upper register
System stack upper register
User stack lower register
System stack lower register

Direct page register

Program bank register
Data bank register
User stack bank register
System stack bank register
Additional data bank register

General-purpose Registers

000180

Processor Status (PS)

ILM

Upper

Lower

H + RP × 10H

32 bits

RP

16 bits

R 7
R 5
R 3
R 1

MSB LSB

—

8 bits

Max.32 banks

R 6
R 4
R 2

R 0
RW3
RW 2
RW 1
RW 0

16 bits

ISTNZVC

RW 7
RW 6
RW 5

RW 4

RL 3

RL 2

RL 1

RL 0

24

C C R

■ MEMORY MAP

MB90210 Series

FFFFFF

H

Address #1

010000H

Address #2

Address #3
Address #4

Single chip

ROM area ROM area

ROM area

FF bank

image

Internal ROM
and external bus

ROM area

FF bank

image

External ROM
and external bus

Address #5

Address #6
000380H

000180H
000100H

0000C0H

000000H

Type

Write-inhibit RAM

RAM

Peripherals

Registers

Address #1 Address #2 Address #3 Address #4 Address #5 Address #6

Write-inhibit RAM Write-inhibit RAM

RAM RAM

Registers Registers

Peripherals Peripherals

: Internal

: External

: No access

MB90214 FF0000H 004000H 001300H 001200H 001100H 000D00H
MB90P214A/P214B

MB90W214A/W214B

FF0000

H 004000H 001300H 001200H 001100H 001100H

MB90V210 (FE0000H) 004000H 001300H 001300H 001100H 001100H

25

MB90210 Series

■ I/O MAP

Address Register

3

Port 0 data register PDR0 R/W

000000
000001
000002
000003
000004
000005
000006
000007
000008
000009

H

*

3

Port 1 data register PDR1 R/W

H

*

3

Port 2 data register PDR2 R/W

H

*

3

Port 3 data register PDR3 R/W

H

*

3

Port 4 data register PDR4 R/W

H

*

3

Port 5 data register PDR5 R/W

H

*

H Port 6 data r egister PDR6 R/W Port 6 11111111
H Port 7 data register PDR7 R/W Port 7 ––XXXXXX
H Port 8 data register PDR8 R/W Port 8 –––––XXX

H

to 0FH

3

000010H
000011
000012
000013
000014
000015
000016

Port 0 data direction register DDR0 R/W

*

3

Port1 data direction register DDR1 R/W

H

*

3

Port 2 data direction register DDR2 R/W

H

*

3

Port 3 data direction register DDR3 R/W

H

*

3

Port 4 data direction register DDR4 R/W

H

*

3

Port 5 data direction register DDR5 R/W

H

*

H Analog input enable register ADER R/W Port 6 11111111

Register

name

Access

(Reserved area) *

Resource

name

Initial value

Port 0 XXXXXXXX
Port 1 XXXXXXXX
Port 2 XXXXXXXX
Port 3 XXXXXXXX
Port 4 XXXXXXXX
Port 5 XXXXXXXX

1

Port 0 00000000
Port 1 00000000
Port 2 00000000
Port 3 00000000
Port 4 00000000
Port 5 00000000

000017
000018
000019

H Port 7 data direction register DDR7 R/W Port 7 ––000000
H Port 8 data direction register DDR8 R/W Port 8 – ––––000

to 1FH

H

(Reserved area) *

1

000020H Mode control register 0 UMC0 R/W UART (ch.0) 00000100
000021

000022
000023

000024
000025

000026
000027

H Status register 0 USR0 R/W 00010000

Input data register 0/output data

H

register 0

H Rate and data register 0 URD0 R/W 00000000
H Mode control register 1 UMC1 R/W UART (ch.1) 00000100
H Status register 1 USR1 R/W 00010000

Input data register 1/output data

H

register 1

H Rate and data register 1 URD1 R/W 00000000

UIDR0/

UODR0

UIDR1/

UODR1

R/W

R/W

XXXXXXXX

XXXXXXXX

(Continued)

26

Address Register

Register

name

MB90210 Series

Access

Resource

name

Initial value

000028

000029
00002A
00002B

00002C
00002D

H Mode control register 2 UMC2 R/W UART (ch.2) 00000100
H Status register 2 USR2 R/W 00010000

Input data register 2/output data

H

register 2

H Rate and data register 2 URD2 R/W 00000000
H UART redirect control register URDR R/W UART (ch.0/2) –––0 0000

H

to 2FH

UIDR2/

UODR2

(Reserved area) *

R/W XXXXXXXX

1

000030H Interrupt/DTP enable register ENIR R/W DTP/external

000031

000032

000033

H Interrupt/DTP factor register EIRR R/W ––––0000
H Reque st level setting register ELVR R/W 00000000

H

(Reserved area) *

1

interrupt

000034H AD control status register ADCS R/W 10-bit A/D

000035

000036

to 37H

000038

to 39H

00003A

to 3BH

H 00000000

H

AD data register ADCD R/W

*4

H

Timer control status register 0 TMCSR0 R/W 16-bit reload

H

Timer control status register 1 TMCSR1 R/W 16-bit reload

converter

timer 1 (ch.0)

timer 1 (ch.1)

––––0000

00000000

XXXXXXXX
0–––––XX

00000000
––––0000

00000000
––––0000

00003C

to 3DH

00003E

to 3FH
000040
000041
000042
000043
000044
000045
000046
000047

H

Timer control status register 2 TMCSR2 R/W 16-bit reload

timer 1 (ch.2)

H

Timer control status register 3 TMCSR3 R/W 16-bit reload

timer 1 (ch.3)

H Timer 0 timer register TMR0 R 16-bit reload
H XXXXXXXX
H Timer 0 reload register TMRLR0 W XXXXXXXX
H XXXXXXXX
H Timer 1 timer register TMR1 R 16-bit reload
H XXXXXXXX
H Timer 1 reload register TMRLR1 W XXXXXXXX
H XXXXXXXX

timer 1 (ch.0)

timer 1 (ch.1)

00000000
––––0000

00000000
––––0000

XXXXXXXX

XXXXXXXX

(Continued)

27

MB90210 Series

Address Register

Register

name

Access

Resource

name

Initial value

000048
000049

00004A
00004B
00004C
00004D
00004E

00004F
000050
000051
000052
000053
000054
000055
000056
000057
000058
000059

00005A

H Timer 2 timer register TMR2 R 16-bit reload
H XXXXXXXX
H Timer 2 reload register TMRLR2 W XXXXXXXX
H XXXXXXXX
H Timer 3 timer register TMR3 R 16-bit reload
H XXXXXXXX
H Timer 3 reload register TMRLR3 W XXXXXXXX
H XXXXXXXX
H Timer 4 timer register TMR4 R 16-bit reload
H XXXXXXXX
H Timer 4 reload register TMRLR4 W XXXXXXXX
H XXXXXXXX
H Timer 5 timer register TMR5 R 16-bit reload
H XXXXXXXX
H Timer 5 reload register TMRLR5 W XXXXXXXX
H XXXXXXXX
H Timer 6 timer register TMR6 R 16-bit reload
H XXXXXXXX
H Timer 6 reload register TMRLR6 W XXXXXXXX

timer 1 (ch.2)

timer 1 (ch.3)

timer 2 (ch.4)

timer 2 (ch.5)

timer 2 (ch.6)

XXXXXXXX

XXXXXXXX

XXXXXXXX

XXXXXXXX

XXXXXXXX

00005B
00005C
00005D
00005E

00005F
000060
000061
000062H
000063
000064H
000065

H XXXXXXXX
H Timer 7 timer register TMR7 R 16-bit reload
H XXXXXXXX
H Timer 7 reload register TMRLR7 W XXXXXXXX
H XXXXXXXX

Timer control status register 4 TMCSR4 R/W 16-bit reload

H

H

(Reserved area) *

1

timer 2 (ch.7)

timer 2 (ch.4)

Timer control status register 5 TMCSR5 R/W 16-bit reload

timer 2 (ch.5)

H

(Reserved area) *

1

Timer control status register 6 TMCSR6 R/W 16-bit reload

timer 2 (ch.6)

H

(Reserved area) *

1

XXXXXXXX

00000000

00000000

00000000

(Continued)

28

Address Register

Register

name

MB90210 Series

Access

Resource

name

Initial value

000066
000067
000068H

000069
00006AH
00006B
00006CH
00006D
00006EH

00006F

Timer control status register 7 TMCSR7 R/W 16-bit reload

H

H

(Reserved area) *

1

PWC0 divide ratio register DIVR0 R/W PWC timer

H

(Reserved area) *

1

PWC1 divide ratio register DIVR1 R/W PWC timer

H

(Reserved area) *

1

PWC2 divide ratio register DIVR2 R/W PWC timer

H

(Reserved area) *

1

PWC3 divide ratio register DIVR3 R/W PWC timer

H

(Reserved area) *

1

timer 2 (ch.7)

(ch.0)

(ch.1)

(ch.2)

(ch.3)

000070H PWC0 control status register PWCSR0 R/W PWC timer

000071

000072

000073

H 00000000
H PWC0 data buffer register PWCR0 R/W 00000000
H 00000000

(ch.0)

00000000

––––––00

––––––00

––––––00

––––––00

00000000

000074

000075

000076

000077

000078

000079
00007A
00007B
00007C
00007D
00007E

00007F

000080

H PWC1 control status register PWCSR1 R/W PWC timer
H 00000000
H PWC1 data buffer register PWCR1 R/W 00000000
H 00000000
H PWC2 control status register PWCSR2 R/W PWC timer
H 00000000
H PWC2 data buffer register PWCR2 R/W 00000000
H 00000000
H PWC3 control status register PWCSR3 R/W PWC timer
H 00000000
H PWC3 data buffer register PWCR3 R/W 00000000
H 00000000

to 87H

H

(Reserved area) *

1

(ch.1)

(ch.2)

(ch.3)

00000000

00000000

00000000

000088H PPG operation mode control register PPGC R/W 8-bit PPG timer 00000––1

000089

H

(Reserved area) *

1

(Continued)

29

MB90210 Series

Address Register

Register

name

Access

Resource

name

Initial value

00008A
00008B
00008C

00008EH WI control register WICR R/W

00008F

00009FH

H PPG reload register PRL R/W 8-bit PPG timer XXXXXXXX
H XXXXXXXX

to 8DH

H

(Reserved area) *

1

Write-inhibit RAM

to 9EH

H

Delayed interrupt source generate/
release register

(Reserved area) *

DIRR R/W

1

Delayed interrupt
generation module

–––X––––

–––––––0

Standby control register STBYC R/W Low-power

0000A0

H

consumption

0001∗∗∗∗

mode

to A2H

H

(Reserved area) *

1

0000A1

0000A3H Middle address control register MACR W External pin ########
0000A4
0000A5
0000A6

H Upper address control regist er HACR W ########
H External pin control register EPCR W ##0–0#00

to A7H

H

(Reserved area) *

1

0000A8H Watchdog timer control register WTC R/W Watchdog timer XXXXXXXX
0000A9

0000AA

H Timebase timer control register TBTC R/W Timebase timer 1––00000

to AFH

H

(Reserved area) *

1

0000B0H Interrupt control register 00 ICR00 R/W Interrupt
0000B1
0000B2
0000B3
0000B4
0000B5
0000B6
0000B7
0000B8
0000B9

H Interrupt control register 01 ICR01 R/W 00000111
H Interrupt control register 02 ICR02 R/W 00000111
H Interrupt control register 03 ICR03 R/W 00000111
H Interrupt control register 04 ICR04 R/W 00000111
H Interrupt control register 05 ICR05 R/W 00000111
H Interrupt control register 06 ICR06 R/W 00000111
H Interrupt control register 07 ICR07 R/W 00000111
H Interrupt control register 08 ICR08 R/W 00000111
H Interrupt control register 09 ICR09 R/W 00000111

controller

00000111

(Continued)

30

(Continued)

MB90210 Series

Address Register

0000BA
0000BB
0000BC
0000BD
0000BE
0000BF
0000C0

H Interrupt control register 10 ICR10 R/W Interrupt
H Interrupt control register 11 ICR11 R/W 00000111
H Interrupt control register 12 ICR12 R/W 00000111
H Interrupt control register 13 ICR13 R/W 00000111
H Interrupt control register 14 ICR14 R/W 00000111
H Interrupt control register 15 ICR15 R/W 00000111

H

to FFH

Register

name

(External area) *

Access

2

Resource

name

controller

Initial value

00000111

Initial value
0: The initial value of this bit is 0.

1: The initial value of this bit is 1.
X: The initial value of this bit is undefined.
–: This bit is not used. The initial value is undefined.
∗: The initial value of this bit varies with the reset source.
#: The initial value of this bit varies with the operation mode.

*1: Access inhibited
*2: The only area available for the external access below address 0000FF

H is this area. Ac cesses to these addresses

are handled as accesses to an external I/O area.

*3: When the external bus is enabled, do not access any register not serving as a general-purpose port in the areas

from address 000000

H to 000005H and from 000010H to 000015H.

*4: Writing to bit 15 is possible. Writing to other bits is used as a test function.

31

MB90210 Series

■ INTERRUPT SOURCES AND INTERRUPT VECTORS/INTERRUPT

CONTROL REGISTERS

2

OS

Interrupt source

EI

support

Reset × # 08 08
INT9 instruction × # 09 09
Exceptional × # 10 0A

UART interrupt #0 # 11 0B

Interrupt vector Interrupt control register

No. Address ICR Address

H FFFFDCH ——
H FFFFD8H ——
H FFFFD4H ——

H FFFFD0H

UART interrupt #1 # 12 0CH FFFFCCH
UART interrupt #2 # 13 0DH FFFFC8H
UART interrupt #3 # 14 0EH FFFFC4H
PWC timer # 0 · count completed # 15 0FH FFFFC0H
PWC timer # 0 · overflow # 16 10H FFFFBCH
PWC timer # 1 · count completed # 17 11H FFFFB8H
PWC timer # 1 · overflow # 18 12H FFFFB4H
PWC timer # 2 · count completed # 19 13H FFFFB0H
PWC timer # 2 · overflow # 20 14H FFFFACH
PWC timer # 3 · count completed # 21 15H FFFFA8H
PWC timer # 3 · overflow # 22 16H FFFFA4H

ICR00 000B0H

ICR01 000B1H

ICR02 000B2H

ICR03 000B3H

ICR04 000B4H

ICR05 000B5H

16-bit reload timer 1 # 0 overflow # 23 17H FFFFA0H
16-bit reload timer 1 # 1 overflow # 24 18H FFFF9CH
16-bit reload timer 1 # 2 overflow # 25 19H FFFF98H
16-bit reload timer 1 # 3 overflow # 26 1AH FFFF94H
16-bit reload timer 2 # 4 overflow # 27 1BH FFFF90H
16-bit reload timer 2 # 5 overflow # 28 1CH FFFF8CH
16-bit reload timer 2 # 6 overflow # 29 1DH FFFF88H
16-bit reload timer 2 # 7 overflow # 30 1EH FFFF84H
A/D converter count completed # 31 1FH FFFF80H
Timebase timer interval interrupt # 32 20H FFFF7CH
UART2 · transmission completed # 33 21H FFFF78H
UART2 · reception completed # 34 22H FFFF74H

ICR06 000B6H

ICR07 000B7H

ICR08 000B8H

ICR09 000B9H

ICR10 000BAH

ICR11 000BBH

(Continued)

32

(Continued)

Interrupt source

2

OS

EI

support

MB90210 Series

Interrupt vector Interrupt control register

No. Address ICR Address

UART1 · transmission completed # 35 23

H FFFF70H

ICR12 0000BCH

UART1 · reception completed # 36 24H FFFF6CH
UART0 · transmission completed # 37 25H FFFF68H ICR13 0000BDH
UART0 · reception completed # 39 27H FFFF60H ICR14 0000BEH
Delayed interrupt generation module × # 42 2AH FFFF54H ICR15 0000BFH

Stack fault × # 255 FFH FFFC00H ——

:EI2OS is supported (with stop request).

2

:EI

OS is supported; however, since two interrupt sources are allocated to a single ICR, in case EI2OS is used

for one of the two, EI

2

OS is supported; however, since two interrupt sources are allocated to a single ICR, in case EI2OS is used

:EI

for one of the two, EI

2

×

:EI

OS is not supported.

2

OS and ordinary interrupt are not both available for the other (with stop request).

2

OS and ordinary interrupt are not both available for the other (with no stop request).

33

MB90210 Series

■ PERIPHERAL RESOURCES

1. Parall el Ports

The MB90210 series has 57 I/O pins and 8 open-drain I/O pins.
Ports 0 to 5, 7, and 8 are I/O ports. Each of these ports serves as an input port when the data direction register

value is 0 and as an output port when the value is 1.
Port 6 is an open-drain port, which may be used as a port when the analog input enable register value is 0.

(1) Register Configuration

• Port data registers 0 to 8 (PDR0 to PDR8)

Port data register

000001 H

PDR1

Address:

000003H

PDR3

000005H

PDR5
PDR7

000007H

Read/write
Initial value

Port data register

000000 H

PDR0

Address:

000002H

PDR2

000004H

PDR4
PDR6

000006H

PDR8

000008H

Read/write
Initial value

Note: No register bit is included in bits 7 and 6 of port 7 or bits 7 to 3 of port 8.

Bit

→
→

Bit

→
→

15 14 13 12 11 10 9 8

PDx7

(R/W)

(R/W)

(R/W)

(R/W)

(R/W)

(X)

(X)

(X)

(X)

(X)

76543210

PDx7

(R/W)

(R/W)

(R/W)

(R/W)

(R/W)

(X)

(X)

(X)

(X)

(X)

(1)

(1)

(1)

(1)

(1)

(R/W)

(X)

(R/W)

(R/W)

(X)
(1)

(X)

(R/W)

(X)
(1)

PDx0PDx1PDx2PDx3PDx4PDx5PDx6

(R/W)

(X)

PDx0PDx1PDx2PDx3PDx4PDx5PDx6

(R/W)

(X)
(1)

• Port direction registers 0 to 5, 7, and 8 (DDR0 to DDR5, DDR7, and DDR8)

Port direction register

000011 H

DDR1

Address:

000013H

DDR3
DDR5

000015H

DDR7

000017H

Read/write
Initial value

Port direction register

000010 H

DDR0

Address:

000012H

DDR2
DDR4

000014H

DDR8

000018H

Bit

→
→

Bit

15 14 13 12 11 10 9 8

DDx7

(R/W)

(R/W)

(R/W)

(R/W)

(R/W)

(0)

(0)

(0)

(0)

(0)

76543210

DDx7

(R/W)

(0)

(R/W)

(0)

DDx0DDx1DDx2DDx3DDx4DDx5DDx6

(R/W)

( 0)

DDx0DDx1DDx2DDx3DDx4DDx5DDx6

PDRx

← Only for the PDR6

DDRx

34

Read/write
Initial value

No register bit is included in bits 7 and 6 of port 7 or bits 7 to 3 of port 8.

Note:

Port 6 has no DDR.

→

(R/W)

(R/W)

(R/W)

→

(0)

(0)

(0)

(R/W)

(0)

(R/W)

(0)

(R/W)

(0)

(R/W)

(0)

(R/W)

(0)

• Analog input enable register (ADER)

MB90210 Series

Analog input enable register

Address:

000016 HADER

Read/write
Initial value→→

(2) Block Diagram

• I/O port (Port 0 to 5, 7, and 8)

Port data register read

Port data register write

Internal data busInternal data bus

Port direction register write

76543210

Bit

ADE7

(R/W)

(R/W)

(1)

(1)

Port data register

Port direction register

(R/W)

(1)

(R/W)

(1)

(R/W)

(1)

(R/W)

(1)

(R/W)

(1)

ADE0ADE1ADE2ADE3ADE4ADE5ADE6

(R/W)

(1)

Pin

ADER

Port direction register read

• I/O port with an open-drain output (Port 6)

Port data register read

Port data register

Port data register write

Analog input enable register

Analog input enable register write

Analog input enable register read

RMW
(Read-modify-write instruction)

Pin

35

MB90210 Series

2. 16-bit Reload Timer 1 (with Event Count Function)

The 16-bit reload timer 1 consists of a 16-bit down counter, a 16-bit reload register, an input pin (TIN), an output
pin (TOUT), and a control register. The input clock can be selected from among three in ter na l clocks and one
external clock. At the outpu t pin (TOUT), the pulses in the toggled output waveform are output in the reload
mode; the rectangular pulses indicating that the timer is counting are in the single-shot mode. The input pin
(TIN) can be used for event input in the event count mode, and for trigger input or gate input in the internal clock
mode.

MB90210 series contains four channels for this timer.

(1) Register Configuration

• Timer control status register (TMCSR)

Timer control status register (Upper byte)

000039H

ch.0

Address:

00003BH

ch.1

00003DH

ch.2
ch.3

00003FH

Read/write
Initial value

Timer control status register (Lower byte)

000038 H

ch.0

Address:

00003AH

ch.1
ch.2

00003CH

ch.3

00003EH

Read/write
Initial value

• Timer register (TMR)

Timer register (Upper byte)

000041H

ch.0

Address:

000045H

ch.1

000049H

ch.2
ch.3

00004DH

Read/write
Initial value

Timer register (Lower byte)

000040H

ch.0

Address:

000044H

ch.1
ch.2

000048H

ch.3

00004CH

Read/write
Initial value

Bit

→
→

Bit

→
→

→
→

→
→

15 14 13 12 11 10 9 8

—

(—)

(—)

(—)

(—)

(R/W)

(R/W)

(—)

(—)

(—)

(—)

(0)

(0)

76543210

MDO0

(R/W)

(R/W)

(R/W)

(R/W)

(R/W)

(R/W)

(0)

(0)

(0)

(0)

(0)

(0)

Bit

Bit

15 14 13 12 11 10 9 8

(R)

(R)

(R)

(R)

(R)

(R)

(X)

(X)

(X)

(X)

(X)

(X)

76543210

(

R

)

(R)

(R)

(R)

(R)

(R)

(X)

(X)

(X)

(X)

(X)

(X)

(R/W)

(0)

(R/W)

(R)
(X)

(0)

(R)
(X)

MOD1MOD2CSL0CSL1———

(R/W)

(0)

TRGCNTEUFINTERELDOUTLOUTE

(R/W)

(R)
(X)

TMCSRx

(0)

TMRx

(R)
(X)

36

• Reload register (TMRLR)

MB90210 Series

Reload register (Upper byte)

ch.0

Address:

ch.1
ch.2
ch.3

Reroal register (Lower byte)

ch.0

Address:

ch.1
ch.2
ch.3

(2) Block Diagram

16

8

000043H
000047H
00004BH
00004FH

Read/write
Initial value

000042H
000046H
00004AH
00004EH

Read/write
Initial value

Bit

→
→

Bit

→
→

16-bit reload register

15 14 13 12 11 10 9 8

(W)

(W)

(X)

(X)

76543210

(

W

)

(W)

(X)

(X)

(W)
(X)

(W)
(X)

(W)
(X)

(W)
(X)

(W)
(X)

(W)
(X)

Reload

(W)
(X)

(W)
(X)

(W)
(X)

(W)

(X)

(W)
(X)

TMRLRx

(W)
(X)

16

Internal data bus

2

3

16-bit down counter

2

Clock selector

φφφ

13 5

222

Internal clock

GATE

EXCK

Prescaler clear

CSL 1

CSL 0

IN CTL

UF

Retrigger

3

MOD 2
MOD 1

MOD 0

OUT
CTL.

RELD
OUTE

OUTL
I NTE

2

UF

CNTE

TRG

UART (timer 1 ch.2 output)
A/D (timer 1 ch.3 output)

IRQ

Clear

2

EI OSCLR

Port (TIN)

Port (TOUT)

37

MB90210 Series

3. 16-bit Reload Timer 2 (with Gate Mode)

The 16-bit relo ad tim er 2 co nsi sts of a 16-bit down counte r, a 16-bit reload regi s ter, an input pin (TIN) , and an
8-bit control register. The input clock can be selected from among four internal clocks.

The MB90210 series contains four channels for this timer.

(1) Register Configuration

• Timer control status register (TMCSR)

Timer control status register

000060 H

ch.4

Address:

ch.5

000062H

ch.6

000064H

ch.7

000066H

Read/write
Initial value→→

Bit

CSL1

(R/W)

(0)

• Timer register (TMR)

Timer register (Upper byte)

000051H

ch.4

Address:

ch.5

000055H

ch.6

000059H

ch.7

00005DH

Read/write
Initial value

Timer register (Lower byte)

000050H

ch.4

Address:

000054H

ch.5
ch.6

000058H

ch.7

00005CH

Read/write
Initial value

Bit

→

(R)

→

(X)

Bit

→
→

76543210

STRTUFINTERELDGATLGATECSL0

(R/W)

(R/W)

(R/W)

(R/W)

(0)

(0)

(0)

(0)

15 14 13 12 11 10 9 8

(R)

(R)

(R)

(R)

(X)

(X)

(X)

(X)

76543210

(

R

)

(R)

(R)

(R)

(R)

(X)

(X)

(X)

(X)

(X)

(R/W)

(0)

(R)

(X)

(R)
(X)

(R/W)

(0)

(R)
(X)

(R)
(X)

(R/W)

(0)

(R)
(X)

TMCSRx

TMRx

(R)
(X)

38

• Reload register (TMRLR)

Reload register (Upper byte)

000053H

ch.4

Address:

000057H

ch.5
ch.6

00005BH

ch.7

00005FH

Read/write
Initial value

Reload register (Lower byte)

000052H

ch.4

Address:

ch.5

000056H

ch.6

00005AH

ch.7

00005EH

Read/write
Initial value

Bit

→
→

Bit

→
→

15 14 13 12 11 10 9 8

(W)

(W)

(W)

(W)

(W)

(X)

(X)

(X)

(X)

(X)

76543210

(

W

)

(W)

(W)

(W)

(W)

(X)

(X)

(X)

(X)

(X)

(W)
(X)

(W)
(X)

(W)
(X)

(W)

(X)

(W)
(X)

TMRLRx

(W)
(X)

(2) Block Diagram

16

4

MB90210 Series

16-bit reload register

Reload

16

Internal data bus

2

2

16-bit down counter

2

Clock selector

φφφφ

25628

222

GATE

UF

CSL 1

CSL 0

IN CTL

2

GATE
GATL

RELD
INTE
UF
STRT

Clear (RELD = 0)

Clear
EI OSCLR

Port (TIN)

IRQ

2

39

MB90210 Series

4. UART

The UART is a serial I/O port for synchronous or asynchronous communication with external resources. It has
the following features:

• Full duplex double buffer

• Data transfer synchronous or asynchronous with clock pulses

• Multiprocessor mode support (Mode 2)

• Built-in dedicated baud-rate generator (Nine types)

• Arbitrary baud-rate setting from external clock input or internal timer
(Use the 16-bit reroad timer 1 channel 2 for internal timer.)

• Variable data length (7 to 9 bits (without parity bit); 6 to 8 bits (with parity bit))

• Variable data length (7 to 9 bit no parity, 6 to 8 bit with parity)

• Error detection function (Framing, overrun, parity)

• Interrupt function (Two sources for transmission and reception)

• Transfer in NRZ format
The MB90210 series contains three channels for the UART.

UART channel 0 has the CTS function.
UART channel 2 provides dual I/O pin switching.

(1) Register Configuration

• Serial mode control register (UMC)

Serial mode control register

000020 H

ch.0

Address:

ch.1

000024H

ch.2

000028H

Read/write
Initial value→→

Bit

76543210

PEN

(R/W)

(R/W)

(R/W)

(R/W)

(0)

(0)

(0)

(0)

• Status register (USR)

Status register

ch.0

Address:

ch.1
ch.2

000021 H
000025H
000029H

Read/write
Initial value

Bit

→
→

15 14 13 12 11 10 9 8

RDRF

(R)

(R)

(R)

(R)

(0)

(0)

(0)

(1)

• Input data register (UIDR)/output data register (UODR)

(R/W)

(0)

(R/W)

(0)

(W)

(R/W)

(0)

(1)

(R/W)

(R)
(0)

(0)

TBFRBFTIERIETDREPEORFE

(R)
(0)

SOESCKERFCSMDEMC0MC1SBL

(R/W)

(0)

UMC

USR

40

Input data register/output data register

000022 H

ch.0

Address:

000026H

ch.1
ch.2

00002AH

Read/write
Initial value

Bit

D7

→

(R/W)

→

(X)

76543210

D0D1D2D3D4D5D6

(R/W)

(R/W)

(R/W)

(X)

(X)

(X)

(R/W)

(X)

(R/W)

(X)

(R/W)

(X)

(R/W)

(X)

UIDR (read)/
UODR (write)

• Rate and data register (URD)

MB90210 Series

Rate and data register

000023 H

ch.0

Address:

ch.1

000027H

ch.2

00002BH

Read/write
Initial value

Bit

→
→

15 14 13 12 11 10 9 8

BCH

(R/W)

(R/W)

(0)

(0)

• UART redirect control register (URDR)

UART redirect control register

76543210

Bit

Address:

00002C H

Read/write
Initial value

—

→

(—)
(—)

(—)
(—)

→

(R/W)

(0)

(—)
(—)

(R/W)

(0)

(R/W)

(0)

(R/W)

(0)

(R/W)

(0)

(R/W)

(0)

(R/W)

(0)

(R/W)

(0)

(R/W)

(0)

D8PBCH0RC0RC1RC2RC3

(R/W)

(0)

SEL3UDPECTSECSPCTE——

(R/W)

URDx

URDR

(0)

41

MB90210 Series

(2) Block Diagram

CONTROL BUS

Dedicated baud-rate clock

16-bit reload timer 1 channel 2
(internally connected)

selector circuit

External clock

SID0 to SID3

Clock

Receiving clock pulse

Reception control circuit

Start bit detector

Received bit counter

Recieved parity

bit counter

Transmitting clock pulse

Transmission control circuit

Transmission control

Transmission parity

Reception interrupt
(To CPU)

SCK0 to SCK3

Transmission interrupt
(To CPU)

circuit

Transmission bit

counter

counter

SOD0 to SOD3

Reception status

detection circuit

Reception error
occurence signal for

2

EI

UMC

register

OS (To CPU)

PEN
SBL
MC1
MC0
SMDE
RFC
SCKE
SOE

Reception shifter

End of reception

SIDR

Internal data bus

USR

register

RDRF
ORFE
PE
TDRE
RIE
TIE
RBF
TBF

Transmission shifter

Start of
transmission

UODR

URD

register

BCH
RC3
RC2
RC1
RC0
BCH0
P
D8

CONTROL BUS

42

MB90210 Series

5. 10-bit A/D Converter

The 10-bit A/D converter converts the analog input voltage to a digital value. It has the following features:

• Conversion time: min.6.125 µs per channel (at 16-MHz machine clock)

• RC-type successive approximation with built-in sample-and-hold circuit

• 10-bit or 8-bit resolution

• Eight analog input channels programmable for selection
Single conversion mode: Selects and converts one channel.
Scan conversion mode: Converts multiple consecutive channels (up to eight channels programmable).
Consecutive conversion mode: Converts a specified channel repeatedly.
Stop conversion mode: Converts one channel and suspends its own operation until the next activation (allowing
synchronized conversion start).

• On completion of A/D conversion, the converter can gen erate an inter r u pt re quest to the CPU. This interrupt

2

generation can acti vate the EI
suitable for continuous operation.

• Conversion can be activated by software, external trigger (falling edge), and/or timer (rising edge) as selected.
Use the 16-bit reroad timer 1 channel 3 for the timer.

(1) Register Configuration

OS to transfer the A/D conversion result to memory, making the co nverter

• A/D Control status register (ADCS1 and ADCS0)

A/D Control status register (Upper byte)

Address:

A/D Control status register (Lower byte)

Address:

000035 H

Read/write
Initial value

000034 H

Read/write
Initial value

15 14 13 12 11 10 9 8

Bit

BUSY

→

(R/W)

(R/W)

(R/W)

→

(0)

(0)

76543210

Bit

MD1

→

(R/W)

(0)

(R/W)

(0)

→

(R/W)

(0)

(R/W)

(0)

• A/D Data registers (ADCD1 and ADCD0)

A/D Data register (Upper byte)

Address:

000037 H

Read/write
Initial value

15 14 13 12 11 10 9 8

Bit

S10

→

(W)

(—)

→

(0)

(—)

(—)
(—)

(0)

(R/W)

(—)
(—)

(0)

(R/W)

(0)

(R/W)

(0)

(—)
(—)

(R/W)

(0)

(R/W)

(—)
(—)

(0)

(W)

(0)

(R/W)

(R)
(X)

(0)

—STRTSTS0STS1PAUSINTEINT

(—)

(0)

ANE0ANE1ANE2ANS0ANS1ANS2MD0

(R/W)

D8D9—————

(R)
(X)

ADCS1

ADCS0

(0)

ADCD1

A/D Data register (Lower byte)

Address:

000036 H

Read/write
Initial value

76543210

Bit

D7

→

(R)

(R)

(R)

(R)

(R)

→

(X)

(X)

(X)

(X)

(X)

(R)

(X)

(R)
(X)

D0D1D2D3D4D5D6

(R)
(X)

ADCD0

43

MB90210 Series

(2) Block Diagram

MPX

AN0
AN1
AN2
AN3
AN4
AN5
AN6
AN7

Input circuit

AV CC

AVRH/AVRL

AV SS

D/A converter

Successive

approximation register

Comparator

ATG

16-bit reload timer 1 channel 3
(internally connected)

Machine clock (φ)

Sample-and-hold circuit

Trigger activation

Timer activation

Internal data bus

A/D data register

ADCD0, ADCD1

Decorder

A/D control status register

ADCS0, ADCS1

Operation clock

Prescaler

44

MB90210 Series

6. PWC(Pulse Width Count) Timer

The PWC (pulse width count) timer is a 16-bit multifunction up-count timer with an input-signal pulse-width count
function and a reload timer function. The hardware co nfiguration of this module is a 16-bi t up-count timer, an
input pulse divi der with divide ratio control regist er, four count input pi ns, and a 16-bit contro l register. Using
these components, the PWC timer provides the following features:

• Timer functions: An interrupt request can be generated at set time intervals.

Pulse signals synchronized with the timer cycle can be output.
The reference internal clock can be selected from among three internal clocks.

• Pulse-width count functions: The time between arbitrary pulse input events can be counted.

The reference internal clock can be selected from among three internal clocks.
Various count modes:

“H” pulse width (↑ to ↓) /“L” pulse width (↑ to ↓)
Rising-edge cycl e (↑ to ↑) /Falling-edge cycle (↓ to ↓)

Count between edges (↑ or ↓ to ↓ or ↑)
Cycle count can be performed by 22n division (n = 1, 2, 3, 4) of the input
pulse, with an 8 bit input divider.
An interrupt request can be generated once counting has been performed.
The number of times counting is to be performed (once or subsequently) can
be selected.

The MB90210 series contains four channels for the PWC timer.

(1) Register Configuration

• PWC control status register (PWCSR)

PWC control status register (Upper byte)

000071 H

ch.0

Address:

000075H

ch.1
ch.2

000079H

ch.3

00007DH

Read/write
Initial value

PWC control status register (Lower byte)

000070 H

ch.0

Address:

ch.1

000074H

ch.2

000078H

ch.3

00007CH

Read/write
Initial value

→
→

→
→

Bit

STRT

(R/W)

(0)

Bit

CKS1

(R/W)

(0)

15 14 13 12 11 10 9 8

POUTERROVIEOVIREDIEEDIRSTOP

(R/W)

(R)

(R/W)

(R/W)

(R/W)

(0)

(0)

(0)

(0)

76543210

(R/W)

(R/W)

(R/W)

(R/W)

(0)

(0)

(0)

(0)

(0)

(R/W)

(0)

(R)

(0)

(R/W)

(0)

(R/W)

(0)

MOD0MOD1MOD2S/CPIS0PIS1CKS0

(R/W)

(0)

PWCSRx

45

MB90210 Series

• PWC data buffer register (PWCR)

PWC data buffer register (Upper byte)

000073 H

ch.0

Address:

000077H

ch.1
ch.2

00007BH

ch.3

00007FH

Read/write
Initial value

PWC data buffer register (Lower byte)

000072 H

ch.0

Address:

000076H

ch.1
ch.2

00007AH

ch.3

00007EH

Read/write
Initial value

Bit

→
→

Bit

→
→

15 14 13 12 11 10 9 8

(R/W)

(R/W)

(0)

(0)

76543210

(R/W)

(R/W)

(0)

(0)

• PWC divide ratio control register (DIVR)

Divide ratio control register

000068 H

ch.0

Address:

00006AH

ch.1
ch.2

00006CH

ch.3

00006EH

Read/write
Initial value→→

Bit

76543210

—

(—)

(—)

(—)

(—)

(R/W)

(0)

(R/W)

(—)
(—)

(0)

(R/W)

(0)

(R/W)

(—)
(—)

(0)

(R/W)

(0)

(R/W)

(0)

(—)
(—)

(R/W)

(0)

(R/W)

(—)
(—)

(0)

(R/W)

(0)

(R/W)

(R/W)

(0)

(0)

(R/W)

(0)

(R/W)

DIV0DIV1—————

(R/W)

PWCR

(0)

DIVR

(0)

46

(2) Block Diagram

MB90210 Series

PWCR read

Write enable

Internal data bus

Flag setting, etc.

15

Error detection

16

16

Reload
Data transfer

Overflow

Control circuit

Start edge

select

Count start edge

Count edge end

Control bit output

Count end interrupt edge

Overflow interrupt request

detection

PWCSR

ERR

PWCR

16

16-bit up-count timer

End edge
select

Edge

ERR

PIS 1
PIS 0

Dividing
ON/OFF

CKS 1
CKS 0

16

Timer clear

Divide ratio

select

2

Clock

Count enable

DIVR

8-bit

divider

Overflow

CKS 1
CKS 0

Internal clock
(machine clock/4)

2

2

divider

3

2

Divider clear

PIS 1
PIS 0

F.F.

Clock

PWC0
PWC1
PWC2
PWC3

POUT
*

* : The POUT pins of the MB90210 series are assigned as follows:

Channel POUT pin

PWC
PWC
PWC

PWC

ch.0
ch.1

ch.2
ch.3

P44/A20/PWC0/POUT0
P45/A21/PWC1/POUT1
P46/A22/PWC2/POUT2

P47/A23/PWC3/POUT3

47

MB90210 Series

7. 8-bit PPG Timer

This block is an 8-bit reloa d timer module for PPG outp ut by controlling pulse outp ut according to th e timer
operation.

The hardware config uration of this block is an 8-bit down c ounter, two 8-bit reload registers, an 8- bit control
register, and an external pulse output pin. Using these components, the module provides the following features:

PPG output operation: The module outputs pulse waves of any period and duty factor. It can also be used as

a D/A converter using an external circuit.

(1) Register Configuration

• PPG operation mode control register (PPGC)

76543210

PPG operation mode control register

Bit

Address:

000088 H

Read/write
Initial value→→

PEN

(R/W)

(0)

(R/W)

(0)

• PPG reload registers (PRLL and RRLH)

PPG reload register

Address:

PPG reload register

Address:

00008B H

Read/write
Initial value

00008A H

Read/write
Initial value

15 14 13 12 11 10 9 8

Bit

→

(R/W)

→

Bit

→
→

(R/W)

(X)

(X)

76543210

(R/W)

(R/W)

(X)

(X)

(R/W)

(R/W)

(X)

(R/W)

(0)

(X)

(R/W)

(R/W)

(X)

(R/W)

(0)

(X)

(R/W)

(R/W)

(X)

(R/W)

(0)

(X)

(—)
(—)

(R/W)

(X)

(R/W)

(X)

(—)
(—)

(R/W)

(X)

(R/W)

(X)

Reserved——PUFReservedPOEPCKS

(R/W)

(R/W)

(X)

(R/W)

(X)

PPGC

(1)

PRLH

PRLL

48

(2) Block Diagram

Output A of timebase counter

Output B of timebase counter

MB90210 Series

PPG
output pin

(Port section)

Output enable

PPG

output latch

Count clock
selection

Invert

PCNT (Down counter)

Reload

L/H selector

PRLL

PRLH

Clear

PEN

PRLBH

Low-byte data bus

High-byte data bus

PPGC

Operation

mode control

49

MB90210 Series

8. DTP/External Interrupt

The data transfer peripheral (DTP) is located between external peripherals and the F2MC-16F CPU. It rece iv es
a DMA request or an interrupt reque st generated by the external p eripherals and repor ts it to the F
CPU to activate the extended intelligent I/O service or interrupt handler. The user can select two request levels
of “H” and “L” for extended intelligent I/O ser vice or, and four request levels of “H,” “L,” rising edge and falling
edge for external interrupt requests.

(1) Register Configuration

• Interrupt/DTP enable register (ENIR)

76543210

Interrupt/DTP enable register

Bit

2

MC-16F

Address:

000030H

Read/write
Initial value→→

—

(—)
(—)

• Interrupt/DTP source register (EIRR)

15 14 13 12 11 10 9 8

Interrupt/DTP source register

Address:

000031 H

Read/write
Initial value→→

Bit

—

(—)
(—)

• Request level setting register (ELVR)

76543210

Request level setting register

Address:

000032 H

Bit

LB3

(—)
(—)

(—)
(—)

(—)
(—)

(—)
(—)

(—)

(—)

(—)

(—)

(R/W)

(0)

(R/W)

(0)

(R/W)

(0)

(R/W)

(0)

(R/W)

(0)

(R/W)

(0)

EN0EN1EN2EN3———

(R/W)

(0)

ER0ER1ER2ER3———

(R/W)

(0)

LA0LB0LA1LB1LA2LB2LA3

ENIR

EIRR

ELVR

50

Read/write
Initial value→→

(R/W)

(0)

(R/W)

(0)

(R/W)

(0)

(R/W)

(0)

(R/W)

(0)

(R/W)

(0)

(R/W)

(0)

(R/W)

(0)

(2) Block Diagram

MB90210 Series

4

4

4

Internal data bus

8

Interrupt/DTP enable register

Gate

Interrupt/DTP source register

Request level setting register

Source F/F

Edge detection circuit

4

INT

51

MB90210 Series

9. Watchdog Timer and Timebase Timer

The watchdog timer consi s ts o f a 2 - bit watchdog co unt er us ing car ry signals f ro m an 18-b it ti me bas e ti me r as
the clock source, a control register, and a watchdog reset control section. The timebase timer consists of an 18­bit timer and an interval interrupt control circuit.

(1) Register Configuration

• Watchdog timer control register (WTC)

Watchdog timer control register

Address:

0000A8H

Read/write
Initial value

76543210

Bit

PONR

→

(R)
(X)

(R)
(X)

→

• Timebase timer control register (TBTC)

Timebase timer control register

Address:

0000A9H

Read/write
Initial value

15 14 13 12 11 10 9 8

Bit

Reserved

→

(W)

(1)

(—)
(—)

→

(—)
(—)

(R)
(X)

(R/W)

(0)

(R)

(X)

(R/W)

(0)

(R)
(X)

(R)

(0)

(W)
(X)

(W)

(R/W)

(0)

(X)

WT0WT1WTESRSTERSTWRSTSTBR

(W)

TBC0TBC1TBRTBOFTBIE——

(R/W)

(0)

WTC

(X)

TBTC

52

(2) Block Diagram

MB90210 Series

Oscillation clock

TBTC
TBC1

TBC0
TBR

TBIE
TBOF

Timebase
interrupt

WTC
WT1

Internal data bus

WT0
WTE

PONR
STBR
WRST
ERST

AND

Selector

S

QR

Selector

12

2

14

2

16

2

18

2

TBTRES

2-bit counter

CLR

Clock input

Timebase timer

2142162172

Watchdog

OF

generator

CLR

reset

18

WDGRST
To internal reset generator

From power-on occurence
From hardware standby

control circuit

RST pin

SRST

From RST bit in STBYC
register

53

MB90210 Series

10.Delayed Interrupt Generation Module

The delayed interrupt generation module is used to generate an interrupt for task switching. Using this module
allows an interrupt request to the F

(1) Register Configuration

• Delayed interrupt source generate/release register (DIRR)

2

MC-16F CPU to generate or cancel by software.

Delayed interrupt source generate/release register

Address:

(2) Block Diagram

00009FH

Read/write
Initial value→→

Internal data bus

15 14 13 12 11 10 9 8

Bit

—

(—)

(—)

(—)

(—)

(—)

(—)

(—)

(—)

(—)

(—)

(—)

(—)

Delayed interrupt source
generate/release register

Source latch

(—)
(—)

R0——————

(R/W)

(0)

DIRR

54

MB90210 Series

11.Write-inhibit RAM

The write-inh ibit RAM is write-protecta ble with the WI pin input. Maintaining the “L” level input to the WI pin
prevents a certain area of RAM from being written. The WI

(1) Register Configuration

• WI control register (WICR)

pin has a 4-machine-cycle filter.

WI control register

Address:

00008EH

Read/write
Initial value→→

(2) Write-inhibit RAM Area

Write-inhibit RAM area

001100
001100

H to 0011FFH (MB90214/P214A/P214B/W214A/W214B)
H to 0012FFH (MB90V210)

(3) Block Diagram

W I

76543210

Bit

—

(—)
(—)

4-machine-cycle
skew removal

4-machine-cycle
skew removal

(—)
(—)

L
H

(—)

(R/W)

(—)

(1)

Access to other area

S Q
R

(—)

(—)

(—)

(—)

SQ

Preceded

R

————WI——

(—)

(—)

(—)

(—)

Write-inhibit

circuit

Select

RAM

decoder

WR

WICR

Write­inhibit

RAM

Internal data bus

55

MB90210 Series

12. Low-power Consumption Modes, Oscillation Stabilization Delay Time, and Gear Function

The MB90210 series has three low-power consumption modes: the sleep mode, the stop mode, the hardware
standby mode, and gear function.

Sleep mode is used to suspend only the CPU operation clock; the other components remain in operation. Stop
mode and hardware standby mode stop oscillation, minimizing the power consumption while holding data.

The clock gear function div ides the exter nal clock frequ ency, which is used usual ly as it is, to pr ovide a lower
machine clock frequency. This function can therefore lower the overall operation speed without changing the
oscillation frequency . The function can select the machine clock as a division of the frequency of crystal oscillation
or external clock input by 1, 2, 4, or 16.

The OSC1 and OSC0 bits can be used to set the oscillation stabilization delay time for wake-up from stop mode
or hardware standby mode.

(1) Register Configuration

• Standby control register (STBYC)

Standby control register

Address:

Note: The initial value(*) of bit0 to bit3 is changed by reset source.

0000A0H

Read/write
Initial value→→

76543210

Bit

STP

(W)

(W)

(R/W)

(R/W)

(0)

(0)

(0)

(1)

(R/W)

(*)

(R/W)

(*)

(R/W)

(*)

CLK0CLK1OSC0OSC1RSTSPLSLP

(R/W)

(*)

STBYC

56

(2) Block Diagram

MB90210 Series

Oscillation clock

Gear divider circuit

STBYC

CLK1
CLK0

SLP
STP

Internal data bus

OSC1
OSC0

SPL

1/1 1/2 1/4 1/16

Selector

Standby control circuit

RST Clear HST start

0

2

16

2

Selector

17

2

18

2

Pin high-impedance control circuit

CPU clock

generator

Peripheral clock

generator

Clock input

Timebase timer

14

16

2 2 2 2

CPU clock

Peripheral clock

HST pin

Interrupt request
or RST

17

18

Pin HI–Z

RST

Internal reset generator

RST pin

Internal RST

To watchdog timer
WDGRST

57

MB90210 Series

■ ELECTRICAL CHARACTERISTICS (MB90V210, de vice used for ev aluation, is excluded)

1. Absolute Maximum Ratings

(VSS = AVSS = 0.0 V)

Parameter

Symbol

Pin

name

Value

Unit Remarks

Min. Max.

Power supply voltage V
Program voltage V

CC VCC VSS – 0.3 VSS + 7.0 V
PP VPP VSS – 0.3 13.0 V

CC AVCC VSS – 0.3 VCC + 0.3 V

AV

MB90P214A/W214A
MB90P214B/W214B

Power supply voltage
for A/D converter

Analog power supply voltage

AVRH
AVRL

Input voltage

V
Output voltage V
“L” level output current I
“L” level total output current ΣI
“H” level output current I
“H” level total output current ΣI

*1

I

O *2 VSS – 0.3 VCC + 0.3 V

OL *3 — 20 mA Rush current

OL *3 — 50 mA Total output current

OH *2 — –10 mA Rush current

OH *2 — –48 mA Total output current

AVRH
AVRL

V

SS – 0.3 AVCC V

—VSS – 0.3 VCC + 0.3 V

Refer ence vo ltage for A/D
converter

Power consumption Pd — — 650 mW

–40 +105 °C MB90214/P214B/W214B

Operating temperature T

A —

–40 +85 °C MB90P214A/W214A

Storage temperature Tstg — –55 +150 °C

I and VO must not exceed VCC + 0.3 V.

*1: V
*2: Output pins

P00 to P07, P10 to P17, P20 to P27, P30 to P37, P40 to P47, P50 to P57, P70 to P75, P80 to P82

*3: Output pins

P00 to P07, P10 to P17, P20 to P27, P30 to P37, P40 to P47, P50 to P57, P60 to P67, P70 to P75, P80 to P82

WARNING: Semiconductor devices can be permanently damaged by application of stress (voltage, current,

temperature, etc.) in excess of absolute maximum ratings. Do not exceed these ratings.

58

2. Recommended Operating Conditions

Parameter

Power supply voltage V

Symbol

CC VCC

Pin

name

MB90210 Series

(VSS = AVSS = 0.0 V)

Value

Min. Max.

4.5 5.5 V When operating

3.0 5.5 V

Unit Remarks

Retains the RAM state in stop
mode

Power supply voltage for A/D
converter

Reference voltage for A/D
converter

Single-chip mode
MB90214/P214B/W214B

Single-chip mode
MB90P214A/W214A

Analog power supply
voltage

Clock frequency F

Operating temperature T

AV

CC AVCC 4.5 VCC + 0.3 V

AVRH AVRH AVRL AV
AVRL AVRL AV

C —10 16MHz

SS AVRH V

CC V

–40 +105 °C

A*—

–40 +85 °C
–40 +70 °C External bus mode

* :Excluding the temperature rise due to the heat produced.
WARNING: Recommended operating conditions are normal operating ranges for the semiconductor device. All the

device’s electrical characteristics are warranted when operated within these ranges.
Always use semicondu ctor devi ces within the recomm ended ope ratin g condit ions. Oper ation outside

these ranges may adversely affect reliability and could result in device failure.
No warranty is made with respec t to uses, operat ing condit ions, or comb inations not represent ed on

the data sheet. Users considering application outside the listed conditions are advised to contact their
FUJITSU representative beforehand.

59

MB90210 Series

3. DC Characteristics

Single-chip mode MB90214/P214B/W214B : (VCC = +4.5 V to +5 .5 V, VSS = 0.0 V, T A = –40°C to +105°C)

MB90P214A/W214A : (V

External bus mode : (V

Parameter Symbol Pin name Condition

IH *1 — 0.7 VCC —

V
“H” level input
voltage

“L” level input
voltage

“H” level ou tput
voltage

IHS *2 — 0.8 VCC —

V

V

IHM

IL *1 —

V

ILS *2 —

V

V

ILM

OH *3

V

V

OH1 X1

MD0 to MD2

MD0 to MD2

CC = 4.5 V

V
I

OH = –4.0 mA

CC = 4.5 V

V
I

OH = –2.0 mA

CC = +4.5 V to +5.5 V, VSS = 0.0 V, TA = –40°C to +85°C)
CC = +4.5 V to +5.5 V, VSS = 0.0 V, TA = –40°C to +70°C)

Value

Unit Remarks

Min. Typ. Max.

—

—

VCC – 0.3

VSS– 0.3
VSS – 0.3
VSS – 0.3

VCC – 0.5

VCC – 2.3

VCC + 0.3
VCC + 0.3
VCC + 0.3

—
— 0.3 VCC V CMOS level input
— 0.2 VCC V Hysteresis input

VSS+ 0.3

—
—VCC V

—VCC V

V CMOS level input
V Hysteresis input
V

V

“L” level output
voltage

Input leakage
current

Analog power
supply voltage

Input capacitance C

Pull-up resistor R

Pull-down resistor R

V

V

OL *4

OL1 X1

V

I

I

I

I2 X0

I

A

*1
*2

AVCC

I

AH ———

IN *6 — — 10 — pF

CC = 4.5 V

OL = 4.0 mA

I

CC = 4.5 V

V
I

OL = 2.0 mA

V

CC =5.5 V

0.2 VCC < VI < 0.8

0—0.4V

0—

VCC – 2.3

——±10 µA

VCC

V

CC =5.5 V

0.2 VCC < VIH < 0.8 VCC

——±25 µA

FC = 16 MHz — 3 7 mA

5

5*

RST — 22 50 110 kΩ

puIU

MD1 — 110 300 650 kΩ

Generic pin — 22 50 110 kΩ

MD0, MD2 — 110 300 650 kΩ

puID

Generic pin — 22 50 110 kΩ

V

Except pins with
pull-up/pull-down
resistor and RST
pin

In stop mode,

µA

T

A = +25°C

7

*
MB90214
MB90P214A/
W214A/P214B/
W214B

7

*
MB90214

7

*
MB90214

7

*
MB90214

7

*
MB90214

(Continued)

60

(Continued)

MB90210 Series

Parameter Symbol Pin name Condition

Unit Remarks

Min. Typ. Max.

Value

—

ICC VCC FC = 16 MHz

—

50*

70*

8

80 mA MB90214

8

100 mA

MB90P214A/
W214A
MB90P214B/
W214B

Power supply
voltage*

9

I

CCS VCC FC = 16 MHz — — 40 mA In sleep mode

A = +25°C

T
In stop mode

CCH VCC ——510µA

I

In hardware
standby input
time

*1: CMOS level input (P00 to P07, P10 to P17, X0)
*2: Hystere sis input pi ns (RST

, HST, P20 to P27, P30 to P37, P40 to P47, P50 to P57, P60 to P67 P70 to P75, P80

to P82)
*3: Output pins (P00 to P07, P10 to P17, P20 to P27, P30 to P37, P40 to P47, P50 to P57, P70 to P75, P80 to P82)
*4: Output pins (P00 to P07, P10 to P17 , P20 to P27, P30 to P 37, P40 to P47, P50 to P57, P60 to P67, P 70 to

P75, P80 to P82)
*5: The current value applies to the CPU stop mode with A/D converter inactive (V
*6: Other than V

CC, VSS, AVCC and AVSS

CC = AVCC = AVRH = +5.5 V) .

*7: A list of availabilities of pull-up/pull-down resistors

Pin name MB90214 MB90P214A/W214A MB90P214B/W214B

RST

Availability of pull-up resistors is

optionally defined.

Pull-up resistors

available

Pull-up resistors

available
MD1 Pull-up resistors available Unavailable Unavailable
MD0, MD2 Pull-down resistors available Unavailable Unavailable

Generic pin

CC = +5.0 V, VSS = 0.0 V, TA = +25°C, FC = 16 MHz

*8: V

Availability of pull-up/pull-down

resistors is optionally defined.

Unavailable Unavailable

*9: Measurement condition of power supply current; external clock pin and output pin are open.

Measurement condition of V

CC; see the table above mentioned.

61

MB90210 Series

2. AC Characteristics

(1) Clock Timing Standards

Single-chip mode MB90214/P214B/W214B : (V

MB90P214A/W214A : (V

External bus mode : (V

Parameter

Clock frequency F
Clock cycle time t

Input clock pulse width

Input clock rising/falling time

• Clock Input Timings

X0

CC = +4.5 V to +5.5 V , VSS = 0.0 V, TA = –40°C to +105°C)
CC = +4.5 V to +5.5 V, VSS = 0.0 V, TA = –40°C to +85°C)
CC = +4.5 V to +5.5 V, VSS = 0.0 V, TA = –40°C to +70°C)

Symbol

C X0, X1 — 10 — 16 MHz

C X 0, X1 — 62.5 — 100 ns 1/FC

WH

P
PWL

cr

t
tcf

Pin

name

Condition

Min. Typ. Max.

X0 — 0.4 tC —0.6 tC ns Duty ratio: 60%

X0 — — — 8 ns tcr + tcf

tC

PWH

PWL

tcf

Value

Unit Remarks

0.7 VCC0.7 VCC

0.3 VCC

tcr

• Clock Conditions

When a crystal

ceramic resonator is used

C1

C1 = C2 = 10 pF
Select the optimum capacity value for the resonator.

or

2

C

When an external clock is used

X0 X1X0 X1

Open

62

• Relationship between Clock Frequency and Power Supply Voltage

MB90210 Series

V CC

[V]

5.5

4.5

016

Single-chip mode

(MB90214/P214B/W214B)
(MB90P214A/W214A)

External bus mode

(2) Clock Output Timing Standards

Parameter

Machine cycle time t
CLK ↑ → CLK↓ t

Symbol

CYC

CHCL

CLK

Operation assurance range

10

External mode: (V

Pin

name

Load condition:
80 pF

: (TA = –40°C to +105°C, FC = 10 to 16 MHz)
: (TA = –40°C to +85°C, FC = 10 to 16 MHz)
: (T

A = –40°C to +70°C, FC = 10 to 16 MHz)

[MHz]

CC = +4.5 to +5.5 V, VSS = 0.0 V, TA = –40°C to +70°C)

Value

Condition

Min. Typ. Max.

62.5 — 1600 ns *
tCYC/

2 – 20

F

C

—t

CYC/2 ns

Unit Remarks

* :t

CYC = n/FC, n gear ratio (1, 2, 4, 16)

CLK

tCHCL

tCYC

1/2 V

CC 1/2 VCC

63

MB90210 Series

(3) Recommended Resonator Manufacturers

• Sample Application of Piezoelectric Resonator (FAR Series)

X0 X1

FAR

*1

C1 C2

FAR part number

(built-in capacitor type)

FAR-C4C F-1 6000- 02

Frequency

Initial deviation of

FAR frequency

(T

= +25°C)

A

±0.5% ±0.5%

16.00

FAR-C4C F-1 6000- 12

±0.5% ±0.5%

Inquiry: FUJIT S U LIMITE D

(4) Reset and Hardware Standby Input Standards

Single-chip mode MB90214/P214B/W214B : (V

MB90P214A/W214A : (V

External bus mode : (V

Parameter

Reset input time t
Hardware standby input time t

Symbol

RSTL RST
HSTL HST 5 tCYC ——ns*

Pin

name

*2*2

*1: Fujitsu Acoustic Resonator

Temperature

characteristics of

FAR frequency

(T

= –20°C to +60°C)

A

Load

capacitance*

Built-in

CC = +4.5 V to +5.5 V , VSS = 0.0 V, TA = –40°C to +105°C)
CC = +4.5 V to +5.5 V, VSS = 0.0 V, TA = –40°C to +85°C)

CC = +4.5 V to +5 .5 V, VSS = 0.0 V, T A = –40°C to +70°C)

Value

Condition

Unit Remarks

Min. Typ. Max.

CYC ——ns

5 t

—

2

* :The machine cycle (t

RST
HST

64

CYC) at hardware standby input is set to 1/16 divided oscillation.

tRSTL, tHSTL

0.2 VCC

0.2 VCC

(5) Power on Supply Specifications (Power-on Reset)

MB90210 Series

Single-chip mode MB90214/P214B/W214B : (V

MB90P214A/W214A : (V

External bus mode : (V

Parameter

Power supply rising time t
Power supply cut-off time t

* :Before the power rising, V

CC must be less than +0.2 V.

Symbol

R VCC ———30ms*
OFF VCC —1——ms

Pin

name

CC = +4.5 V to +5.5 V , VSS = 0.0 V, TA = –40°C to +105°C)
CC = +4.5 V to +5.5 V, VSS = 0.0 V, TA = –40°C to +85°C)

CC = +4.5 V to +5.5 V, VSS = 0.0 V, TA = –40°C to +70°C)

Value

Condition

Unit Remarks

Min. Typ. Max.

Notes: • The above specifications are for the power-on reset.

• Always apply power-on reset using these specifications, regardless of whether or not

the power-on reset is needed.

• There are some internal registers (such as STBYC) which are only initialized by the power-on reset.

• Power-on Reset

tR

VCC

4.5 V

0.2 V

0.2 V
tOFF

0.2 V

Note: Caution on switching power supply

Abrupt change of supply voltage may initiate power-on reset, even if the above requirements are not met.
It is, therefore, recommended to power up gradually during the instantaneous c hange of power supply as
shown in the figure be low.

• Changing Power Supply

Main power
supply voltage

Subpower
supply voltage

VSS

The rising edge should be 50 mV/ms or less.

65

MB90210 Series

(6) Bus Read Timing

Parameter

Symbol

Pin

name

(V

CC = +4.5 to +5.5 , VSS = 0.0 V, TA = –40°C to +70°C)

Value

Condition

Unit Remarks

Min. Max.

Valid address → RD
RD

pulse width tRLRH RD tCYC – 25 — ns
↓ → valid data input tRLDV

RD
RD

↑ → data hold time tRHDX 0—ns

Valid address→ valid data
input

RD

↑ → address valid time tRHAX A23 to A00 tCYC/2 – 20 — ns
Valid address → CLK ↑ time t
RD

↓ → CLK ↓ time tRLCL RD, CLK tCYC/2 – 25 — ns

RD

↓ time tAVRL A23 to A00

t

AVDV —3 tCYC/2 – 40 ns

AVCH

CLK

D15 to D00

A23 to A00
CLK

tAVRL

tRLCLtAVCH

0.7 VCC

0.3 VCC

Load
condition:
80 pF

0.3 VCC

tRLRH

tCYC/2 – 20 — ns

—t

t

CYC/2 – 25 — ns

0.7 VCC

CYC – 30 ns

66

A23 to A00

D15 to D00

0.7 VCC

0.3 VCC

tAVDV

tRLDV

0.7 VCC

0.3 VCC

Read data

tRHAX

0.7 VCC

0.3 VCC

tRHDX

0.7 VCC

0.3 VCC

(7) Bus Write Timing

Parameter

(V

CC = +4.5 to +5.5 V, VSS = 0.0 V, TA = –40°C to +70°C)

Symbol Pin name Condition

MB90210 Series

Value

Unit Remarks

Min. Max.

Valid address → WR
WR

↓ pulse width tWLWH WRL, WRH tCYC – 25 — ns

Valid data output → WR
time

↑ → data hold time tWHDX tCYC/2 – 20 — ns

WR

↑ → address valid time tWHAX A23 to A00 tCYC/2 – 20 — ns

WR
WR

↓ → CLK ↓ time tWLCH WRL, WRH, CLK tCYC/2 – 25 — ns

↓ time tAVWL A23 to A00

↑

t

DVWH

CLK

WR
(WRL, WRH)

A23 to A00

D15 to D00

tAVWL

Load
condition:
80 pF

tWLCL

0.3 VCC

tWLWH

0.3 VCC

t

CYC/2 – 20 — ns

CYC – 40 — ns

t

0.7 VCC

tWHAX

0.7 VCC

0.3 VCC

D15 to D00

Un­defined

t

DVWH

Write data

t

WHDX

0.7 VCC

0.3 VCC

67

MB90210 Series

(8) Ready Signal Input Timing

Parameter

Symbol Pin name Condition

(V

CC = +4.5 to +5.5 V, VSS = 0.0 V, TA = –40°C to +70°C)

Value

Unit Remarks

Min. Max.

RDY setup time t
RDY hold time t

RYHS

RDY

RYHH 0—ns

Load condition:
80 pF

Note: Use the auto-ready function if the RDY setup time is insufficient.

CLK

A23 to A00

RD/WR
(WRL, WRH)

RDY
No wait

Wait

tRYHS tRYHH

0.8 VCC 0.8 VCC

0.2 VCC

40 — ns

0.7 VCC

tRYHS tRYHH

0.7 VCC

0.8 VCC0.8 VCC

(9) Hold Timing

Parameter

Pin floating → HAK
HAK

↑ → pin valid time tHAHV tCYC 2tCYC ns

↓ time tXHAL

Symbol

Note: It takes at least one cycle for HAK

HRQ

HAK

Each pin

0.8 VCC

68

CC = +4.5 to +5.5 V, VSS = 0.0 V, TA = –40°C to +70°C)

(V

Pin

name

HAK

Condition

Load condition:
80 pF

to vary after HRQ is fetched.

0.2 VCC

0.3 VCC

tXHAL tHAHV

High impedance

Value

Min. Max.

30 t

0.7 VCC

CYC ns

Unit Remarks

(10) UART Timing

MB90210 Series

Single-chip mode MB90214/P214B/W214B : (V
External bus mode : (V

Parameter

Serial clock cycle time t
SCLK ↓ → SOUT

delay time
Valid SIN → SCLK ↑ t
SCLK ↑ → Valid SIN

hold time
Serial clock “H” puls e

width
Serial clock “L” pulse

width
SCLK ↓ → SOUT

delay time
Valid SIN → SCLK ↑ t
SCLK ↑ → Valid SIN

hold time

CC = +4.5 V to +5.5 V, VSS = 0.0 V, TA = –40°C to +10 5°C)

MB90P214A/W214A : (V

Symbol

SCYC

SLOV –80 80 ns

t

Pin

name

Condition

CC = +4.5 V to +5.5 V, VSS = 0.0 V, TA = –40°C to +85°C)
CC = +4.5 V to +5.5 V, VSS = 0.0 V, TA = –40°C to +70°C)

Value

Unit Remarks

Min. Max.

8 t

CYC —ns

Internal shift
clock mode

IVSH 100 — ns

t

SHIX 60 — ns

t

SHSL 4 tCYC —ns

t

SLSH 4 tCYC —ns

Load condition:

—

80 pF

output pin

External shift

SLOV — 150 ns

t

IVSH 60 — ns

t

SHIX 60 — ns

clock mode
output pin

Notes:

• These AC characteristics assume the CLK synchronous mode.

• tCYC is the machine cycle (unit: ns).

69

MB90210 Series

• Internal Shift Clock Mode

SCK

SOD

0.3 V

tSLOV

tSCYC

0.7 VCC

CC

0.7 VCC

0.3 VCC

0.3 VCC

SID

• External Shift Clock Mode

SCK

SOD

SID

0.2 VCC

tSLOV

0.8 VCC

0.2 VCC

tSLSH

0.2 VCC

0.7 VCC

0.3 VCC

0.8 VCC

0.2 VCC

tIVSH

tIVSH

tSHIX

0.8 VCC

0.2 VCC

tSHSL

0.8 VCC

0.2 VCC

tSHIX

0.8 VCC

0.2 VCC

70

(11) Resource Input Timing

MB90210 Series

Single-chip mode MB90214/P214B/W214B : (V

MB90P214A/W214A : (V

External bus mode : (V

Parameter

Symbol Pin name Condition

TIN0 to TIN3

TIWH

Input pulse width

t
tTIWL

TIN4 to TIN7 2 t

PWC0 to PWC3

INT0 to INT3 3 t
ATG

t

WIWL WI 4 tCYC ——ns

TIN0 to TIN7
PWC0 to PWC3
INT0 to INT3
WI

Load
condition:
80 pF

tTIWH

CC = +4.5 V to +5.5 V , VSS = 0.0 V, TA = –40°C to +105°C)
CC = +4.5 V to +5.5 V, VSS = 0.0 V, TA = –40°C to +85°C)

CC = +4.5 V to +5.5 V, VSS = 0.0 V, TA = – 40°C to +70°C)

Value

Unit Remarks

Min. Typ. Max.

4 t

CYC ——

External event
count input mode

ns

2 t

CYC ——
CYC — — ns Gate input mode

Trigger input/
Gate input mode

2 tCYC ——ns

CYC ——ns

2 tCYC ——ns

0.8 VCC0.8 VCC

0.2 VCC0.2 VCC

tTIWL, tWIWL

(12) Resource Output Timing

Single-chip mode MB90214/P214B/W214B : (V

MB90P214A/W214A : (V

External bus mode : (V

Parameter

CLK ↑ →
T

OUT transition time

Symbol Pin name Condition

TOUT0 to TOUT3
PPG

TO

t

POUT0 to POUT3

CLK

TOUT0 to TOUT3
PPG
POUT0 to POUT3

CC = +4.5 V to +5.5 V, VSS = 0.0 V, TA = –40°C to +10 5°C)
CC = +4.5 V to +5.5 V, VSS = 0.0 V, TA = –40°C to +85°C)
CC = +4.5 V to +5.5 V, VSS = 0.0 V, TA = –40°C to +70°C)

Value

Unit Remarks

Min. Max.

Load condition:
80 pF

0.7 VCC

0.7 VCC

0.3VCC

tTO

—30ns

71

MB90210 Series

≤≤≤

5. A/D Converter Electrical Characteristics

Single-chip mode MB90214/P214B/W214B:

CC = VCC = +5.0±10%, AVSS = VSS = 0.0 V, TA = –40°C to +105°C, +4.5 V AVRH – AVRL)

(AV

Single-chip mode MBP90214A/W214A:

CC = VCC = +5.0±10%, AVSS = VSS = 0.0 V, TA = –40°C to +85°C, +4.5 V AVRH – AVRL)

(AV

External bus mode:

CC = VCC = +5.0±10%, AVSS = VSS = 0.0 V, TA = –40°C to +70°C, +4.5 V AVRH – AVRL)

(AV

Parameter

Symbol Pin name Condition

Min. Typ. Max.

Resolution n — — — — 10 bit
Total error — — — –3.0 — +3.0 LSB
Linearity error — — — –2.0 — +2.0 LSB
Differential

linearity error

—— — ——±1.5 LSB

Value

Unit

Remarks

Zero transition
voltage

V

OT

—

AVRL – 1.5 AVRL + 0.5 AVRL + 2.5

AN0 to AN7

Full-scale
transition voltage

Conversion time

Sampling period

Analog port input
current

V

FST —

T

CONV —

CYC = 62.5 ns

t

SAMP —3.75—µs

T

I

AIN

———±0.1 µA

AVRH – 3.5 AVRH – 1.5 AVRH + 0.5

6.125 — µs

—

—

AN0 to AN7

Analog input
voltage

Analog reference
voltage

Reference voltage
supply current

Interchannel
disparity

* :The current value applies to the CPU stop mode with the A/D converter inactive (V

AIN — AVRL — AVRH V

V

AVRH — AVRL — AV

CC V

—

AVRL — AV

I

R

——200500µA

SS —AVRHV

AVRH

I

RH ———5*µA

— AN0 to AN7 — — — 4 LSB

CC = AVCC = AVRH = +5.5 V).

Notes: (1) The smaller the | AVRH – AVRL |, the greater the error would become relatively.

(2) Use the output impedance of the external circuit for analog input under the following conditions:

External circuit output impedance < approx. 10 kΩ (Sampling period 3.75 µs, t

.

=

.
(3) Precision values are standard values applicable to sleep mode.
(4) If V

CC/A VCC or VSS/AVSS is caused by a noise to drop to below the analog input voltage, the analog input

current is likely to increase. In such cases, a bypass capacitor or the like should be provided in the external
circuit to suppress the noise.

LSB

LSB

98 machine

cycles

60 machine

cycles

CYC = 62.5 ns)

72

• Equivalent Circuit of Analog Input Circuit

MB90210 Series

Analog input

C0

Comparator

External impedance

R ON1

RON1: Approx. 1.5 k
R

ON2: Approx. 1.5 k

0: Approx. 60 pF

C

Ω
Ω

R ON2

1

C

C1: Approx. 4 pF

Note: The values shown here are reference values.

6. A/D Converter Glossary

Resolution: Analog changes that are identifiable with the A/D converter

When the number of bits is 10, analog voltage can be divided into 2

Total error: Difference between actual and logical values. This error is caused by a zero transition error,

full-scale transition error, linearity error, differential linearity error, or by noise.

Linearity error: The deviation of the straight line connecting the zero transition point (“00 0000 0000” ↔ “00

0000 0001”) with the full-scale transition point (“11 1111 1111” ↔
conversion characteristics

Differential linearity error: The deviation of input voltage needed to change the output code by 1 LSB from the

theoretical value.

10

= 1024.

“11 1111 1110”) from actual

Digital output
11 1111 1111
11 1111 1110
11 1111 1101

•

•

•

•

N + 1
N
N – 1

•

•

•

•

00 0000 0010
00 0000 0001
00 0000 0000

•

1LSB

•

Linearity error

•

Differential linearity error

•

Total error

Theoretical value
Actual conversion value

V

V 0T V(N–1)T

1T V 2T V(N+1)T

V

=

FST – V0T

1022

• 1LSB theoretical value

V

NT– (N × 1LSB + V0T)

=

VNT – { ( N + 0.5 ) × 1LSB theoretical value }

=

1LSB

V

NT – V(N – 1) T

=

1LSB

1LSB theoretical value

Theoretical value V NT

Total error

Linerity error

N × 1LSB + V

V NT AVRH (V)AVRL

AVRH – AVRL

=

1022

N = 0 to 1022

NT (N = 0) = V0T

V
VNT (N = 1022) = VFST

N = 1 to 1022

– 1

N = 0 to 1022

0T

V FST

73

MB90210 Series

■ EXAMPLE CHARACTERISTICS

(1) Power Supply Current

I CCH vs. T A example characteristics

CCH (µA)

I

40

CC (mA)

I

100

I CC vs. T A example characteristics

F C = 16 MHz

90

External clock input
V

CC = 5.5 V

30

80

20

70

MB90P214A

10

60

50

MB90214

40

–50 0 50 100 150

T

A (°C)

0

–10

–50 0 50 100 150

Note: These are not assured value of characteristics but example characteristics.

(2) Output Voltage

T

A (°C)

V CC = 5.5 V

OL vs. I OL example characteristics

V OH vs. I OH example characteristics

OH (V)

V

5.5

V

2.0

V

OL (V)

T A = +25°C

5.0

V CC = 5.0 V

4.5

4.0

3.5

3.0
–15 –10 –5 0 5

I

OH (mA)

1.5

1.0

0.5

0.0

–0.5

–5 0 5 10 15

Note: These are not assured value of characteristics but example characteristics.

I

OL (mA)

T A = +25°C
V CC = 5.0 V

20 25

74

(3) Pull-up/Pull-down Resistor

MB90210 Series

Pull-down resistor example characteristics

pul D (kΩ)

R

100

90
80
70

V CC = 4.5 V
V CC = 5.0 V

V CC = 5.5 V

60
50
40
30
20

–50 0 50 100 150

T

A (°C)

Pull-down resistor example characteristics

pul D (kΩ)

R

500

V CC = 5.5 V

400
300
200
100

–50 0 50 100 150

T

A (°C)

Pull-up resistor example characteristics

pul U (kΩ)

R

100

90
80
70
60

V CC = 4.5 V
V CC = 5.0 V

V CC = 5.5 V

50
40
30
20

–50 0 50 100 150

T

A (°C)

Pull-up resistor example characteristics

pul U (kΩ)

R

500
400

V CC = 5.5 V

300
200
100

–50 0 50 100 150

T

A (°C)

Note: These are not assured value of characteristics but example characteristics.

(4) Analog Filter

Analog filter example characteristics

Input pulse width (ns)

80

T A = +25°C

70

60

50

40

30

Filtering enable

20

10

4.0 4.5 5.0 5.5 6.0
V

CC (V)

Note: These are not assured value of characteristics but example characteristics.

75

MB90210 Series

■ INSTRUCTIONS (421 INSTRUCTIONS)

Table 1 Description of Items in Instruction List

Item Description

Mnemonic English upper case and symbol: Described directly in assembler code.

English lower case: Converted in assembler code.

Number of letters after English lower case: Describes bit width in code.
# Describes number of bytes.
~ Describes number of cycles.

For other letters in other items, refer to table 4.
B Describes correction value for calculating number of actual states.

Number of actual states is calculated by adding value in the ~section.

Operation Describes operation of instructions.

LH Describes a special operation to 15 bits to 08 bits of the accumulator.

Z : Transfer 0.

X: Sign-extend and transfer.

– : No transmission

AH Describes a special operation to the upper 16-bit of the accumulator.

* : Transmit from AL to AH.

– : No transfer.

Z : Transfer 00

X: Sign-extend AL and transfer 00

H to AH.

H or FFH to AH.

I Describes status of I (interrupt enable), S (stack), T (sticky bit), N (negative), Z (zero),
S
T

N

Z
V

C

RMW Describes whether or not the instruction is a read-modify-write type (a data is read out from

V (overflow), and C (carry) flags.
* : Changes after execution of instruction.
– : No changes.
S: Set after execution of instruction.
R: Reset after execution of instruction.

memory etc. in single cycle, and the result is written into memory etc.).
* : Read-modify-write instruction
– : Not read-modify-write instruction
Note: Not used to addresses having different functions for reading and writing operations.

76

Table 2 Description of Symbols in Instruction Table

Item Description

A 32-bit accumlator

The bit length is dependent on the instructions to be used.
Byte : Lower 8-bit of AL
Word:16-bit of AL
Long : AL: 32-bit of AH

AH Upper 16-bit of A

AL Lower 16-bit of A
SP Stack pointer (USP or SSP)

PC Program counter
SPCU Stack pointer upper limited register
SPCL Stack pointer lower limited register

PCB Program bank register
DTB Data bank register
ADB Additional data bank register
SSB System stack bank register
USB User stack bank register
SPB Current stack bank register (SSB or USB)
DPR Direct page register
brg1 DTB, ADB, SSB, USB, DPR, PCB
brg2 DTB, ADB, SSB, USB, DPR

Ri R0, R1, R2, R3, R4, R5, R6, R7
RWi RW0, RW1, RW2, RW3, RW4, RW5, RW6, RW7
RWj RW0, RW1, RW2, RW3

RLi RL0, RL1, RL2, RL3

dir

addr16
addr24

ad24 0 to 15

ad24 16 to 23

io I/O area (000000

#imm4

#imm8
#imm16
#imm32

ext (imm8)

disp8

disp16

bp Bit offset value

vct4
vct8

( )b Bit address

rel

ear

eam

rlst Register all ocati on

Specify shortened direct address.
Specify direct address.
Specify physical direct address.
bit0 to bit15 of addr24
bit16 to bit 23 of addr24

H to 0000FFH)

4-bit immediate data
8-bit immediate data
16-bit immediate data
32-bit immediate data
16-bit data calculated by sign-extending an 8-bit immediate data

8-bit displacement
16-bit displacement

Vector number (0 to 15)
Vector number (0 to 255)

Specify PC relative branch.
Specify effective address (code 00 to 07).
Specify effective address (code 08 to 1F).

MB90210 Series

77

MB90210 Series

Table 3 Effective Address Field

Code Symbol Address type

00
01
02
03
04
05
06
07

08
09
0A
0B

0C
0D

0E
0F

10
11
12
13
14
15
16
17

R0
R1
R2
R3
R4
R5
R6
R7

RW0
RW1
RW2
RW3
RW4
RW5
RW6
RW7

@RW0
@RW1
@RW2
@RW3

@RW0 +
@RW1 +
@RW2 +
@RW3 +

@RW0 + disp8
@RW1 + disp8
@RW2 + disp8
@RW3 + disp8
@RW4 + disp8
@RW5 + disp8
@RW6 + disp8
@RW7 + disp8

RL0

(RL0)

RL1

(RL1)

RL2

(RL2)

RL3

(RL3)

Register direct
"ea" corresponds to byte, word, and
long word from left respectively.

Register indirect

Register indirect with post increment

Register indirect with 8-bit
displacement

Number of bytes in address

extension block*

—

0

0

1

18
19
1A
1B

1C
1D

1E
1F

Note: Number of bytes for address extension corresponds to “+” in the # (number of bytes) part in the instruction

table.

@RW0 + disp16
@RW1 + disp16
@RW2 + disp16
@RW3 + disp16

@RW0 + RW7
@RW1 + RW7

@PC + disp16

addr16

Register indirect with 16-bit
displacement

Register indirect with index
Register indirect with index
PC indirect with 16-bit displacement
Direct address

2

0
0
2
2

78

MB90210 Series

Table 4 Number of Execution Cycles in Addressing Modes

Code Operand

Ri

00 to 07

08 to 0B @RWj 1

0C to 0F @RWj + 4

10 to 17 @RWi + disp8 1

18 to 1B @RWj + disp16 1

1C
1D
1E
1F

Note: (a) is used for ~ (number of cycles) and B (correction value) in instruction table.

Table 5 Correction Value for Number of Cycles for Calculating Actual Number of Cycles

Operand

Internal regis ter +0 +0 +0

RWi

RLi

@RW0 + RW7
@RW1 + RW7

@PC + disp16

addr16

Number of execution cycles for addressing modes

Listed in instruction table

(b)* (c)* (d)*

byte word long

(a)*

2
2
2
1

Internal RAM even address
Internal RAM odd address

Other than internal RAM even address
Other than internal RAM odd address

External data bus 8-bit +1 +3 +6

Notes: (b), (c), (d) is used for ~ (number of cycles) and B (correction value) in instruction table.

+0
+0

+1
+1

+0
+1

+1
+3

+0
+2

+2
+6

79

MB90210 Series

Table 6 Transmission Instruction (Byte) [50 Instructions]

Mnemonic # ~ B Operation

MOV A, dir
MOV A, addr16
MOV A, Ri
MOV A, ear
MOV A, eam
MOV A, io
MOV A, #imm8
MOV A, @A
MOV A, @RLi + disp8
MOV A, @SP + disp8
MOVP A, addr24
MOVP A, @A
MOVN A, #imm4

MOVX A, dir
MOVX A, addr16
MOVX A, Ri
MOVX A, ear
MOVX A, eam
MOVX A, io
MOVX A, #imm8
MOVX A, @A
MOVX A, @ RWi + disp 8
MOVX A, @RLi + disp8
MOVX A, @SP + disp8

MOVPX A, addr24
MOVPX A, @A

2
3
1
2

2 +

2
2
2
3
3
5
2
1

2
3
2
2

2 +

2
2
2
2
3
3
5
2

2 + (a)

2 + (a)

LH AH

byte (A) ← (dir)

(b)

2
2
1
1

2
2
2
6
3
3
2
1

2
2
1
1

2
2
2
3
6
3
3
2

byte (A) ← (addr16)

(b)

byte (A) ← (Ri)

0

byte (A) ← (ear)

0

byte (A) ← (eam)

(b)

byte (A) ← (io)

(b)

byte (A) ← imm8

0

byte (A) ← ((A))

(b)

byte (A) ← ((RLi) + disp8)

(b)

byte (A) ← ((SP) + disp8)

(b)
(b)

byte (A) ← (addr24)

(b)

byte (A) ← ((A))

0

byte (A) ← imm4

(b)

byte (A) ← (dir)

(b)

byte (A) ← (addr16)

0

byte (A) ← (Ri)

0

byte (A) ← (ear)

(b)

byte (A) ← (eam)

(b)

byte (A) ← (io)

0

byte (A) ← imm8

(b)

byte (A) ← ((A))

byte (A) ← ((RWi) + disp8)

(b)
(b)

byte (A) ← ((RLi) + disp8)

byte (A) ← ((SP) + disp8)

(b)
(b)

byte (A) ← (addr24)

(b)

byte (A) ← ((A))

Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z

X
X
X
X
X
X
X
X
X
X
X
X
X

ISTNZVCRMW

–

–

*

*

–

–

–

*

–

*

–

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*

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*

*

*

*

*

*

*

*

*

*

*

*

*

*

*

*

*

*

*

*

*

*

*

R

*

*

*

*

*

*

*

*

*

*

*

*

*

*

*

*

*

*

*

*

*

*

*

*

*

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–
–
–
–
–
–

–
–
–
–
–
–
–
–
–
–
–
–
–

(b)

2

MOV dir, A
MOV addr16, A
MOV Ri, A
MOV ear, A
MOV eam, A
MOV io, A
MOV @RLi + disp8, A
MOV @SP + disp8, A
MOVP addr24, A

MOV Ri, ear
MOV Ri, eam
MOVP @A, Ri
MOV ear, Ri
MOV eam, Ri
MOV Ri, #imm8
MOV io, #imm8
MOV dir, #imm8
MOV ear, #imm8
MOV eam, #imm8

MOV @AL, AH
XCH A, ear

XCH A, eam
XCH Ri, ear
XCH Ri, eam

Note: For (a) and (b), refer to “Table 4 Number of Execution Cycles in Addressing Modes” and “Table 5 Correction

Values for Number of Cycles for Calculating Actual Number of Cycles.”

2
3
1
2

2 +

2
3
3
5

2

2 +

2
2

2 +

2
3
3
3

3 +

2
2

2 +

2

2 +

2
1
2

2 + (a)

2
6
3
3

2

3 + (a)

3
3

3 + (a)

2
3
3
2

2 + (a)

2
3

3 + (a)

4

5 + (a)

(b)

0

0
(b)
(b)
(b)
(b)
(b)

0
(b)
(b)

0
(b)

0
(b)
(b)

0
(b)

(b)

0

2 × (b)

0

2 × (b)

byte (dir) ← (A)
byte (addr16) ← (A)
byte (Ri) ← (A)
byte (ear) ← (A)
byte (eam) ← (A)
byte (io) ← (A)

byte ((RLi) + disp8) ← (A)
byte ((SP) + disp8) ← (A)

byte (addr24) ← (A)
byte (Ri) ← (ear)

byte (Ri) ← (eam)
byte ((A)) ← (Ri)
byte (ear) ← (Ri)
byte (eam) ← (Ri)
byte (Ri) ← imm8
byte (io) ← imm8
byte (dir) ← imm8
byte (ear) ← imm8
byte (eam) ← imm8

byte ((A)) ← (AH)
byte (A) ↔ (ear)

byte (A) ↔ (eam)
byte (Ri) ↔ (ear)
byte (Ri) ↔ (eam)

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

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–

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–

Z

–

Z

–

–

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*

–

*

–

*

–

*

–

*

–

*

–

*

–

*

–

*

–

*

–

*

–

*

–

*

–

*

–

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–

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*

–

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*

–

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*

–

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*

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*

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*

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*

–

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*

–

*

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*

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–

–

–

–

–

*

*

–

80

MB90210 Series

Table 7 Transmission Instruction (Word) [40 Instructions]

Mnemonic # ~ B Operation

MOVW A, dir
MOVW A, addr16
MOVW A, SP
MOVW A, RWi
MOVW A, ear
MOVW A, eam
MOVW A, io
MOVW A, @A
MOVW A, #imm16
MOVW A, @RWi + disp8
MOVW A, @RLi + disp8
MOVW A, @SP + disp8

MOVPW A, addr24
MOVPW A, @A

MOVW dir, A
MOVW addr16, A
MOVW SP, #imm16
MOVW SP, A
MOVW RWi, A
MOVW ear, A
MOVW eam, A
MOVW io, A
MOVW @RWi + disp8, A
MOVW @RLi + disp8, A
MOVW @SP + disp8, A

MOVPW addr24, A
MOVPW @A, RWi

MOVW RWi, ear
MOVW RWi, eam
MOVW ear, RWi
MOVW eam, RWi
MOVW RWi, #imm16
MOVW io, #imm16
MOVW ear, #imm16
MOVW eam, #imm16

2
3
1
1
2

2 +

2
2
3
2
3
3
5
2

2
3
4
1
1
2

2 +

2
2
3
3
5
2
2

2 +

2

2 +

3
4
4

4 +

2
2
2
1
1

2 + (a)

2
2
2
3
6
3
3
2

2
2
2
2
1
2

2 + (a)

2
3
6
3
3
3
2

3 + (a)

3

3 + (a)

2
3
2

2 + (a)

word (A) ← (dir)

(c)

word (A) ← (addr16)

(c)

word (A) ← (SP)

0

word (A) ← (RWi)

0

word (A) ← (ear)

0

word (A) ← (eam)

(c)

word (A) ← (io)

(c)

word (A) ← ((A))

(c)

word (A) ← imm16

0

word (A) ← ((RWi) +disp8)

(c)

word (A) ← ((RLi) +disp8)

(c)

word (A) ← ((SP) + disp8)

(c)
(c)

word (A) ← (addr24)

(c)

word (A) ← ((A))

(c)

word (dir) ← (A)

(c)

word (addr16) ← (A)

0

word (SP) ← imm16

0

word (SP) ← (A)

0

word (RWi) ← (A)

0

word (ear) ← (A)

(c)

word (eam) ← (A)

(c)

word (io) ← (A)

word ((RWi) +disp8) ← (A)

(c)

word ((RLi) +disp8) ← (A)

(c)

word ((SP) + disp8) ← (A)

(c)
(c)

word (addr24) ← (A)

(c)

word ((A)) ← (RWi)

0

word (RWi) ← (ear)

(c)

word (RWi) ← (eam)

0

word (ear) ← (RWi)

(c)

word (eam) ← (RWi)

0

word (RWi) ← imm16

(c)

word (io) ← imm16

0

word (ear) ← imm16

(c)

word (eam) ← imm16

LH AH

*

–

*

–

*

–

*

–

*

–

*

–

*

–

–

–

*

–

*

–

*

–

*

–

*

–

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–

–

–

–

ISTNZVCRMW

–

–

–

*

*

–

–

–

–

–

–

*

*

–

–

–

–

–

–

*

*

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*

*

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*

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*

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*

*

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*

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*

*

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*

*

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*

*

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*

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*

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*

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*

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*

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*

*

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*

*

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*

*

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*

*

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*

*

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*

*

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*

*

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*

*

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*

*

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*

*

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*

*

–

–

–

–

–

–

–

–

–

–

–
MOVW @AL, AH
XCHW A, ear

XCHW A, eam
XCHW RWi, ear
XCHW RWi, eam

2
2

2 +

2

2 +

2
3

3 + (a)

4

5 + (a)

(c)

word ((A)) ← (AH)

0

word (A) ↔ (ear)

2 × (c)

word (A) ↔ (eam)

0

word (RWi) ↔ (ear)

2 × (c)

word (RWi) ↔ (eam)

–
–

–
–
–

–

–

–

–

–

–

–

–

–

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–

–

–

–

–

–

–

–

*

*

–

–

Note: For (a) and (c), refer to “Table 4 Number of Execution Cycles in Addressing Modes” and “Table 5 Correction

Values for Number of Cycles for Calculating Actual Number of Cycles.”

81

MB90210 Series

Table 8 Transmission Instruction (Long) [11 Instructions]

Mnemonic # ~ B Operation

MOVL A, ear 2 2 0 long (A) ← (ear) –––––* *–– –
MOVL A, eam 2 +
MOVL A, #imm32 5 3 0 long (A) ← imm32 –––––**–– –
MOVL A, @SP + disp8 3 4 (d)
MOVPL A, addr24 5 4 (d) long (A) ← (addr24) –––––**–– –
MOVPL A, @A 2 3 (d) long (A) ← ((A)) –––––* *–– –

MOVPL @A, RLi 2 5 (d) long ((A)) ← (RLi) –––––* *–– –

MOVL @SP + disp8, A 3 4 (d)
MOVPL addr24, A 5 4 (d) long (addr24) ← (A) –––––**–– –
MOVL ear, A 2 2 0 long (ear) ← (A) –––––**–– –
MOVL eam, A 2 +

Note: For (a) and (c), refer to “Table 4 Number of Execution Cycles in Addressing Modes” and “Table 5 Correction

Values for Number of Cycles for Calculating Actual Number of Cycles.”

3 + (a)

3 + (a)

(d) long (A) ← (eam) –––––**–– –

long (A) ← ((SP) + disp8)

long ((SP) + disp8) ← (A)

(d) long (eam) ← (A) –––––**–– –

LH AH

–––––* *–– –

–––––* *–– –

ISTNZVCRMW

82

MB90210 Series

Table 9 Add/Subtract (Byte, Word, Long) [42 Instructions]

Mnemonic # ~ B Operation

byte (A) ← (A) +imm8

ADD A,#imm8
ADD A, dir
ADD A, ear
ADD A, eam
ADD ear, A
ADD eam, A
ADDC A
ADDC A, ear
ADDC A, eam
ADDDC A
SUB A, #imm8
SUB A, dir
SUB A, ear
SUB A, eam
SUB ear, A
SUB eam, A
SUBC A
SUBC A, ear
SUBC A, eam
SUBDC A

ADDW A
ADDW A, ear
ADDW A, eam
ADDW

ADDW ear, A
ADDW eam, A
ADDCW A, ear
ADDCW A, eam
SUBW A
SUBW A, ear
SUBW A, eam
SUBW
SUBW ear, A
SUBW eam, A
SUBCW A, ear
SUBCW A, eam

ADDL A, ear
ADDL A, eam
ADDL

SUBL A, ear
SUBL A, eam
SUBL

A, #imm16

A, #imm16

A, #imm32

A, #imm32

2
2
2

2 +

2

2 +

1
2

2 +

1
2
2
2

2 +

2

2 +

1
2

2 +

1
1

2

2 +

3
2

2 +

2

2 +

1
2

2 +

3
2

2 +

2

2 +

2

2 +

5
2

2 +

5

2
3
2

3 + (a)

2

3 + (a)

2
2

3 + (a)

3
2
3
2

3 + (a)

2

3 + (a)

2
2

3 + (a)

3
2

2

3 + (a)

2
2

3 + (a)

2

3 + (a)

2
2

3 + (a)

2
2

3 + (a)

2

3 + (a)

5

6 + (a)

4
5

6 + (a)

4

0

(b)

0

(b)

0

2 × (b)

0
0

(b)

0
0

(b)

0

(b)

0

2 × (b)

0
0

(b)

0
0

0

(c)

0
0

2 × (c)

0

(c)

0
0

(c)

0
0

2 × (c)

0

(c)

0

(d)

0
0

(d)

0

byte (A) ← (A) +(dir)
byte (A) ← (A) +(ear)
byte (A) ← (A) +(eam)
byte (ear) ← (ear) + (A)
byte (eam) ← (eam) + (A)
byte (A) ← (AH) + (AL) + (C)
byte (A) ← (A) + (ear) + (C)
byte (A) ← (A) + (eam) + (C)

byte (A) ← (AH) + (AL) + (C) (decimal)

byte (A) ← (A) – imm8
byte (A) ← (A) – (dir)
byte (A) ← (A) – (ear)
byte (A) ← (A) – (eam)
byte (ear) ← (ear) – (A)
byte (eam) ← (eam) – (A)
byte (A) ← (AH) – (AL) – (C)
byte (A) ← (A) – (ear) – (C)
byte (A) ← (A) – (eam) – (C)

byte (A) ← (AH) – (AL) – (C) (decimal)

word (A) ← (AH) + (AL)
word (A) ← (A) + (ear)
word (A) ← (A) + (eam)
word (A) ← (A) + imm16
word (ear) – (ear) + (A)
word (eam) – (eam) + (A)
word (A) ← (A) + (ear) + (C)
word (A) ← (A) + (eam) + (C)
word (A) ← (AH) – (AL)
word (A) ← (A) – (ear)
word (A) ← (A) – (eam)
word (A) ← (A) – imm16
word (ear) ← (ear) – (A)
word (eam) ← (eam) – (A)
word (A) ← (A) – (ear) – (C)
word (A) ← (A) – (eam) – (C)

long (A) ← (A) + (ear)
long (A) ← (A) + (eam)
long (A) ← (A) + imm32
long (A) ← (A) – (ear)
long (A) ← (A) – (eam)
long (A) ← (A) – imm32

LH AH

–

Z

–

Z

–

Z

–

Z

–

–

–

Z

–

Z

–

Z

–

Z

–

Z

–

Z

–

Z

–

Z

–

Z

–

–

–

–

–

Z

–

Z

–

Z

–

Z

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

ISTNZVCRMW

–

*

*

*

*

–

–

–

–

*

*

*

*

–

–

–

–

*

*

*

*

–

–

–

–

*

*

*

*

–

–

–

*

*

*

*

*

–

–

–

*

*

*

*

*

–

–

–

–

*

*

*

*

–

–

–

–

*

*

*

*

–

–

–

–

*

*

*

*

–

–

–

–

*

*

*

*

–

–

–

–

*

*

*

*

–

–

–

–

*

*

*

*

–

–

–

–

*

*

*

*

–

–

–

–

*

*

*

*

–

–

–

*

*

*

*

*

–

–

–

*

*

*

*

*

–

–

–

–

*

*

*

*

–

–

–

–

*

*

*

*

–

–

–

–

*

*

*

*

–

–

–

–

*

*

*

*

–

–

–

–

*

*

*

*

–

–

–

–

*

*

*

*

–

–

–

–

*

*

*

*

–

–

–

–

*

*

*

*

–

–

–

*

*

*

*

*

–

–

–

*

*

*

*

*

–

–

–

–

*

*

*

*

–

–

–

–

*

*

*

*

–

–

–

–

*

*

*

*

–

–

–

–

*

*

*

*

–

–

–

–

*

*

*

*

–

–

–

–

*

*

*

*

–

–

–

*

*

*

*

*

–

–

–

*

*

*

*

*

–

–

–

–

*

*

*

*

–

–

–

–

*

*

*

*

–

–

–

–

*

*

*

*

–

–

–

–

*

*

*

*

–

–

–

–

*

*

*

*

–

–

–

–

*

*

*

*

–

–

–

–

*

*

*

*

–

–

–

–

*

*

*

*

–

–

–

Note: For (a) to (d), refer to “Table 4 Number of Execution Cycles in Addressing Modes” and “Table 5 Correction

Values for Number of Cycles for Calculating Actual Number of Cycles.”

83

MB90210 Series

Table 10 Increment/Decrement (Byte, Word, Long) [12 Instructions]

Mnemonic # ~ B Operation

INC ear
INC eam

DEC ear
DEC eam

INCW ear
INCW eam

DECW ear
DECW eam

INCL ear
INCL eam

DECL ear
DECL eam

Note: For (a) to (d), refer to “Table 4 Number of Execution Cycles in Addressing Modes” and “Table 5 Correction

Values for Number of Cycles for Calculating Actual Number of Cycles.”

Mnemonic # ~ B Operation

CMP A
CMP A, ear
CMP A, eam
CMP A, #imm8

2

2

2 +

3 + (a)

2

2

2 +

3 + (a)

2

2

3 + (a)

2 +

2

2

3 + (a)

2 +

4

2

5 + (a)

2 +

4

2

5 + (a)

2 +

Table 11 Compare (Byte, Word, Long) [11 Instructions]

1

1

2

2

3 + (a)

2 +

2

2

0

byte (ear) ← (ear) +1

2 × (b)

2 × (b)

2 × (c)

2 × (c)

2 × (d)

2 × (d)

byte (eam) ← (eam) +1

0

byte (ear) ← (ear) –1
byte (eam) ← (eam) –1

word (ear) ← (ear) +1

0

word (eam) ← (eam) +1
word (ear) ← (ear) –1

0

word (eam) ← (eam) –1
long (ear) ← (ear) +1

0

long (eam) ← (eam) +1
long (ear) ← (ear) –1

0

long (eam) ← (eam) –1

byte (AH) – (AL)

0

byte (A) – (ear)

0

byte (A) – (eam)

(b)

byte (A) – imm8

0

LH AH

–
–

–
–

–
–

–
–

–
–

–
–

LH AH

–
–
–
–

ISTNZVCRMW

–

–

–

–

*

*

*

–

–

–

–

–

*

*

*

–

–

–

–

–

*

*

*

–

–

–

–

–

*

*

*

–

*

*

–

–

–

–

*

*

–

–

–

–

*

–

–

–

–

*

*

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

ISTNZVCRMW

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

*
*

*

*

*

*

*

*

*

*

*

*

*

*

*

*

*

–

*

–

*

–

*

–

*

–

*

–

*

–

*

–

*

*

*

*

*

*

*

*

*

*
*

*
*

*
*

*
*

–
*

*
*

–
–
–
–

word (AH) – (AL)

1

CMPW A
CMPW A, ear
CMPW A, eam
CMPW A, #imm16

CMPL A, ear
CMPL A, eam
CMPL A, #imm32

Note: For (a) to (d), refer to “Table 4 Number of Execution Cycles in Addressing Modes” and “Table 5 Correction

Values for Number of Cycles for Calculating Actual Number of Cycles.”

84

1
2

2 +

3
2

2 +

5

2

3 + (a)

2
6

7 + (a)

3

0

word (A) – (ear)

0

word (A) – (eam)

(c)

word (A) – imm16

0
0

word (A) – (ear)

(d)

word (A) – (eam)

0

word (A) – imm32

–

*

*

*

*

–

–

–

–

–

*

*

*

*

–

–

–

–

–

*

*

*

*

–

–

–

–

–
–

–

–

–

–

*

*

*

*

–

–

–

–

–

*

*

*

*

–

–

–

–

–

*

*

*

*

*

*

*

*

–

–

–

–

–
–
–
–

–
–
–

MB90210 Series

Table 12 Unsigned Multiply/Division (Word, Long) [11 Instructions]

Mnemonic # ~ B Operation

DIVU A

DIVU A, ear

DIVU A, eam

DIVUW A, ear

DIVUW A, eam

MULU A
MULU A, ear
MULU A, eam
MULUW A
MULUW A, ear
MULUW A, eam

Note: For (b) and (c), refer to “Table 5 Correction Values for Number of Cycles for Calculating Actual Number of

Cycles.”

1

2

2 +

2

2+

1
2

2 +

1
2

2 +

*1

*2

*3

*4

*5

*8

*9
*10
*11
*12
*13

0

word (AH) /byte (AL)

Quotient → byte (AL)
Remainder → byte (AH)

0

word (A)/byte (ear)

Quotient → byte (A)
Remainder → byte (ear)

word (A)/byte (eam)

*6

Quotient → byte (A)
Remainder → byte (eam)

long (A)/word (ear)

0

Quotient → word (A)
Remainder → word (ear)

long (A)/word (eam)

*7

Quotient → word (A)
Remainder → word (eam)

byte (AH) byte (AL) → wo rd (A)

0

byte (A) byte (ear) → word (A)

0

byte (A) byte (eam) → word (A)

(b)

word (AH) word (AL) → long (A)

0

word (A) word (ear) → long (A)

0

word (A) word (eam) → long (A)

(c)

LH AH

–

–

–

–

–

–
–
–
–
–
–

ISTNZVCRMW

–

–

–

–

–

–

*

*

–

–

–

–

–

–

*

*

–

–

–

–

–

–

*

*

–

–

–

–

–

–

*

*

–

–

–

–

–

–

*

*

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–
–
–
–
–
–

*1: Set to 3 when the division-by-0, 6 for an overflow, and 14 for normal operation.
*2: Set to 3 when the division-by-0, 6 for an overflow, and 13 for normal operation.
*3: Set to 5 + (a) when the division-by-0, 7 + (a) for an overflow, and 17 + (a) for normal operation.
*4: Set to 3 when the division-by-0, 5 for an overflow, and 21 for normal operation.
*5: Set to 4 + (a) when the division-by-0, 7 + (a) for an overflow, and 25 + (a) for normal operation.
*6: When the division-by-0, (b) for an overflow, and 2 × (b) for normal operation.
*7: When the division-by-0, (c) for an overflow, and 2 × (c) for normal operation.
*8: Set to 3 when byte (AH) is zero, 7 when byte (AH) is not zero.
*9: Set to 3 when byte (ear) is zero, 7 when byte (ear) is not zero.
*10:Set to 4 + (a) when byte (eam) is zero, 8 + (a) when byte (eam) is not zero.
*11:Set to 3 when word (AH) is zero, 11 when word (AH) is not zero.
*12:Set to 4 when word (ear) is zero, 11 when word (ear) is not zero.
*13:Set to 4 + (a) when word (eam) is zero, 12 + (a) when word (eam) is not zero.

85

MB90210 Series

Table 13 Signed multiplication/division (Word, Long) [11 Instructions]

Mnemonic # ~ B Operation

DIV A 2 *10word (AH)/byte (AL) Z––––––** –

Quotient → byte (AL)
Remainder → byte (AH)

DIV A, ear 2 *20word (A)/byte (ear) Z––––––* * –

Quotient → byte (A)
Remainder → byte (ear)

DIV A, eam 2 +*3*6word (A)/byte (eam) Z––––––** –

Quotient → byte (A)
Remainder → byte (eam)

DIVW A, ear 2 *4 0 long (A)/word (ear) – – – ––––* * –

Quotient → word (A)
Remainder → word (ear)

DIVW A, eam 2 + *5 *7 long (A)/word (eam) – – – ––––* * –

Quotient → word (A)

Remainder → word (eam)
MUL A 2 *8 0 byte (AH) × byte (AL) → word (A)––––––––– –
MUL A, ear 2 *9 0 byte (A) × byte (ear) → word (A) ––––––––– –
MUL A, eam 2 + *10 (b)
MULW A 2 *11 0
MULW A, ear 2 *12 0
MULW A, eam 2 + *13 (b) word

For (b) and (c), refer to “Table 5 Correction Values f or Number of Cycles for Calculating Actual Number of Cycles.”

byte (A) × byte (eam) → word (A)
word (AH) × word (AL) → long (A)
word (A) × word (ear) → long (A)

(A) × word (eam)

→

long (A) ––––––––– –

LH AH

––––––––– –
––––––––– –
––––––––– –

ISTNZVCRMW

*1: Set to 3 for divide-by-0, 8 or 18 for an overflow, and 18 for normal operation.
*2: Set to 3 for divide-by-0, 10 or 21 for an overflow, and 22 for normal operation.
*3: Set to 4 + (a) for divide-by-0, 11 + (a) or 22 + (a) for an overflow, and 23 + (a) for normal operation.
*4: Positive divided: Set to 4 for divide-by-0, 10 or 29 for an overflow, and 30 for normal operation.

Negative divided: Set to 4 for divide-by-0, 11 or 30 for an overflow, and 31 for normal operation.

*5: Positive divided: Set to 4 + (a) for divide-by-0, 11 + (a) or 30 + (a) for an overflow , and 31 + (a) for normal operation.

Negative divided: Set to 4 + (a) for divide-by-0, 12 + (a) or 31 + (a) for an overflow, and 32 + (a) for normal

operation.
*6: Set to (b) when the division-by-0 or an overflow, and 2
*7: Set to (c) when the division-by-0 or an overflow, and 2
*8: Set to 3 when byte (AH) is zero, 12 when the result is positive, and 13 when the result is negative.
*9: Set to 3 when byte (ear) is zero, 12 when the result is positive, and 13 when the result is negative.
*10:Set to 4 + (a) when byte (eam) is zero, 13 + (a) when the result is positive, and 14 + (a) when the result is negative.
*11:Set to 3 when word (AH) is zero, 12 when the result is positive, and 13 when the result is negative.
*12:Set to 3 when word (ear) is zero, 16 when the result is positive, and 19 when the result is negative.
*13:Set to 4 + (a) when word (eam) is zero, 17 + (a) when the result is positive, and 20 + (a) when the result is negative.

Note: When overflow occurs during DIV or DIVW instruction execution, the number of execution cycles takes two

values because of detection before and after an operation.
When overflow occurs during DIV or DIVW instruction execution, the contents of AL are destroyed.

× (b) for normal operation.
× (c) for normal operation.

86

MB90210 Series

Table 14 Logic 1 (Byte, Word) [39 Instruc tions]

Mnemonic # ~ B Operation

byte (A) ← (A) and imm8

AND A, #imm8
AND A, ear
AND A, eam
AND ear, A
AND eam, A

OR A, #imm8
OR A, ear
OR A, eam
OR ear, A
OR eam, A

XOR A, #imm8
XOR A, ear
XOR A, eam
XOR ear, A
XOR eam, A
NOT A
NOT ear
NOT eam

ANDW A
ANDW A, #imm16
ANDW A, ear
ANDW A, eam
ANDW ear, A
ANDW eam, A

2
2

2 +

2

2 +

2
2

2 +

2

2 +

2
2

2 +

2

2 +

1
2

2 +

1
3
2

2 +

2

2 +

2
2

3 + (a)

3

3 + (a)

2
2

3 + (a)

3

3 + (a)

2
2

3 + (a)

3

3 + (a)

2
2

3 + (a)

2
2
2

3 + (a)

3

3 + (a)

0
0

(b)

0

2 × (b)

0
0

(b)

0

2 × (b)

0
0

(b)

0

2 × (b)

0
0

2 × (b)

0
0
0

(c)

0

2 × (c)

byte (A) ← (A) and (ear)
byte (A) ← (A) and (eam)
byte (ear) ← (ear) and (A)
byte (eam) ← (eam) and (A)

byte (A) ← (A) or imm8
byte (A) ← (A) or (ear)
byte (A) ← (A) or (eam)
byte (ear) ← (ear) or (A)
byte (eam) ← (eam) or (A)

byte (A) ← (A) xor imm8
byte (A) ← (A) xor (ear)
byte (A) ← (A) xor (eam)
byte (ear) ← (ear) xor (A)
byte (eam) ← (eam) xor (A)
byte (A) ← not (A)
byte (ear) ← not (ear)
byte (eam) ← not (eam)

word (A) ← (AH) and (A)
word (A) ← (A) and imm16
word (A) ← (A) and (ear)
word (A) ← (A) and (eam)
word (ear) ← (ear) and (A)
word (eam) ← (eam) and (A)

LH AH

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

ISTNZVCRMW

–

–

R

*

*

–

–

–

–

–

R

*

*

–

–

–

–

–

R

*

*

–

–

–

*

–

R

*

*

–

–

–

*

–

R

*

*

–

–

–

–

–

R

*

*

–

–

–

–

–

R

*

*

–

–

–

–

–

R

*

*

–

–

–

*

–

R

*

*

–

–

–

*

–

R

*

*

–

–

–

–

–

R

*

*

–

–

–

–

–

R

*

*

–

–

–

–

–

R

*

*

–

–

–

*

–

R

*

*

–

–

–

*

–

R

*

*

–

–

–

–

–

R

*

*

–

–

–

*

–

R

*

*

–

–

–

*

–

R

*

*

–

–

–

–

–

R

*

*

–

–

–

–

–

R

*

*

–

–

–

–

–

R

*

*

–

–

–

–

–

R

*

*

–

–

–

*

–

R

*

*

–

–

–

*

–

R

*

*

–

–

–

word (A) ← (AH) or (A)

2

ORW A
ORW A, #imm16
ORW A, ear
ORW A, eam
ORW ear, A
ORW eam, A

XORW A
XORW A, #imm16
XORW A, ear
XORW A, eam
XORW ear, A
XORW eam, A
NOTW A
NOTW ear
NOTW eam

Note: For (a) to (c), refer to “Table 4 Number of Execution Cycles in Addressing Modes” and “Table 5 Correction

Values for Number of Cycles for Calculating Actual Number of Cycles.”

1
3
2

2 +

2

2 +

1
3
2

2 +

2

2 +

1
2

2 +

2
2

3 + (a)

3

3 + (a)

2
2
2

3 + (a)

3

3 + (a)

2
3

3 + (a)

0
0
0

(c)

0

2 × (c)

0
0
0

(c)

0

2 × (c)

0
0

2 × (c)

word (A) ← (A) or imm16
word (A) ← (A) or (ear)
word (A) ← (A) or (eam)
word (ear) ← (ear) or (A)
word (eam) ← (eam) or (A)

word (A) ← (AH) xor (A)
word (A) ← (A) xor imm16
word (A) ← (A) xor (ear)
word (A) ← (A) xor (eam)
word (ear) ← (ear) xor (A)
word (eam) ← (eam) xor (A)
word (A) ← not (A)
word (ear) ← not (ear)
word (eam) ← not (eam)

–

–

–

R

*

*

–

–

–

–

–

–

–

R

*

*

–

–

–

–

–

–

–

R

*

*

–

–

–

–

–

*

–

R

*

*

–

–

–

–

–

*

–

R

*

*

–

–

–

–

–

–

–

R

*

*

–

–

–

–

–

–

–

R

*

*

–

–

–

–

–

–

–

R

*

*

–

–

–

–

–

–

–

R

*

*

–

–

–

–

–

*

–

R

*

*

–

–

–

–

–

*

–

R

*

*

–

–

–

–

–

–

–

R

*

*

–

–

–

–

–

*

–

R

*

*

–

–

–

–

–

*

–

R

*

*

–

–

–

–

–

–

–

R

*

*

–

–

–

–

87

MB90210 Series

Table 15 Logic 2 (Long) [6 Instructions]

Mnemonic # ~ B Operation

ANDL A, ear
ANDL A, eam

ORL A, ear
ORL A, eam

XORL A, ear
XORL A, eam

2

2 +

2

2 +

2

2 +

5

6 + (a)

5

6 + (a)

5

6 + (a)

0

long (A) ← (A) and (ear)

(d)

long (A) ← (A) and (eam)

0

long (A) ← (A) or (ear)

(d)

long (A) ← (A) or (eam)

0

long (A) ← (A) xor (ear)

(d)

long (A) ← (A) xor (eam)

LH AH

–

–

–

–

–

–

–

–

–

–

–

–

ISTNZVCRMW

–

–

–

*

*

R

–

–

–

–

–

*

*

R

–

–

–

–

–

*

*

R

–

–

–

–

–

*

*

R

–

–

–

–

–

*

*

R

–

–

–

–

–

*

*

R

–

–

Note: For (a) and (d), refer to “Table 4 Number of Execution Cycles in Addressing Modes” and “Table 5 Correction

Values for Number of Cycles for Calculating Actual Number of Cycles.”

Table 16 Sign Reverse (Byte, Word) [6 Instructions]

Mnemonic # ~

NEG A
NEG ear

NEG eam
NEGW A

NEGW ear
NEGW eam

1
2

2 +

1
2

2 +

2
3

5 + (a)

2
3

5 + (a)

RG

B Operation

byte (A) ← 0 – (A)

0

0

byte (ear) ← 0 – (ear)

0

2
0

0
2

0

2 × (b)

2 × (c)

byte (e am) ← 0 – (eam)
word (A) ← 0 – (A)

0

word (ear ) ← 0 – (ear)

0

word (eam) ← 0 – (eam)

LH AH

–

X

–

–

–

–

–

–

–

–

–

–

ISTNZVC

*

*

*

*

–

–

–

*

*

*

*

–

–

–

*

*

*

*

–

–

–

*

*

*

*

–

–

–

*

*

*

*

–

–

–

*

*

*

*

–

–

–

RMW

–
–

*

–
–

*

Note: For (a) and (d), refer to “Table 4 Number of Execution Cycles in Addressing Modes” and “Table 5 Correction

Values for Number of Cycles for Calculating Actual Number of Cycles.”

Table 17 Absolute Values (Byte, Word, Long) [3 Instructions]

Mnemonic # ~ B Operation

byte (A) ← Absolute value (A)

ABS A
ABSW A
ABSL A

2
2
2

2
2
4

0

word (A) ← Absolute value (A)

0

long (A) ← Absolute value (A)

0

LH AH

–

Z

–

–

–

–

ISTNZVCRMW

–

–

*

*

*

–

–

–

–

–

*

*

*

–

–

–

–

–

*

*

*

–

–

–

Table 18 Normalize Instruction (Long) [1 Instruction]

Mnemonic # ~ RG B Operation

NRML A, R0 2 *1 1 0 long (A) ← Shift to where “1”

LH AH

ISTNZVC

––––––*–– –

RMW

is originally located
byte (R0) ← Number of shifts
in the operation

* :Set to 5 when the accumulator is all “0”, otherwise set to 5 + (R0).

88

MB90210 Series

Table 19 Shift Type Instruction (Byte, Word, Long) [27 Instructions]

Mnemonic # ~ B Operation

RORC A
ROLC A

RORC ear
RORC eam
ROLC ear
ROLC eam

ASR A, R0
LSR A, R0
LSL A, R0

ASR

A, #imm8

LSR A, #imm8
LSL A, #imm8

ASRW A
LSRW

A/SHRW A

LSL W A/SHLW A
ASRW A, R0

LSRW A, R0
LSLW A, R0

ASRW

A, #imm8

LSRW A, #imm8
LSLW A, #imm8

ASRL A, R0
LSRL A, R0
LSLL A, R0

2
2

2

2 +

2

2 +

2
2
2

3
3
3

1
1
1

2
2
2

3
3
3

2
2
2

2
2

2

3 + (a)

2

3 + (a)

*1
*1
*1

*3
*3
*3

2
2
2

*1
*1
*1

*3
*3
*3

*2
*2
*2

0

byte (A) ← With right-rotate carry

0

byte (A) ← With left-rotate carry

0

byte (ear) ← With right-rotate carry

2 × (b)

byte (e am) ← With right-rotate carry

0

byte (ear) ← With left-ro tate ca rry

2 × (b)

byte (e am) ← With left-rotate carry

byte (A) ← Arithmetic right barrel shift (A, R0)

0

byte (A) ← Logical right barrel shift (A, R0)

0

byte (A) ← Logical left barrel shift (A, R0)

0

byte (A) ← Arithmetic right barrel shift (A, imm8)

0

byte (A) ← Logical right barrel shift (A, imm8)

0

byte (A) ← Logical left barrel shift (A, imm8)

0

word (A) ← Arithmetic right shift (A, 1 bit)

0

word (A) ← Logical right shift (A, 1 bit)

0

word (A) ← Logical left shift (A, 1 bit)

0

word (A) ← Arithmetic right barrel shift (A, R0)

0

word (A) ← Logical right barrel shift (A, R0)

0

word (A) ← Logical left barrel shift (A, R0)

0

word (A) ← Arithmetic right barrel shift (A, imm8)

0

word (A) ← Logical right barrel shift (A, imm8)

0

word (A) ← Logical left barrel shift (A, imm8)

0

long (A) ← Arithmetic right barrel shift (A, R0)

0

long (A) ← Logical right barrel shift (A, R0)

0

long (A) ← Logical left barrel shift (A, R0)

0

LH AH

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–
–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

ISTNZVC

–

–

–

*

*

–

*

–

–

–

*

*

–

*

–

–

–

*

*

–

*

–

–

–

*

*

–

*

–

–

–

*

*

–

*

–

–

–

*

*

–

*

–

–

*

*

*

–

*

–

–

*

*

*

–

*

–

–

–

*

*

–

*

–

–

*

*

*

–

*

–

–

*

*

*

–

*

–

–

–

*

*

–

*
*

–

*

*

*

–

–

*

–

*

R

*

–

–

*

–

*

*

–

–

–

*

–

*

*

*

–

–

*

–

*

*

*

–

–

*

–

*

*

–

–

–

*

–

*

*

*

–

–

*

–

*

*

*

–

–

*

–

*

*

–

–

–

*

–

*

*

*

–

–

*

–

*

*

*

–

–

*

–

*

*

–

–

–

RMW

–
–

*
*
*
*

–
–
–

–
–
–

–
–
–

–
–
–

–
–
–

–
–
–

ASRL

A, #imm8

LSRL A, #imm8
LSLL A, #imm8

*4

3

*4

3

*4

3

long (A) ← Arithmetic right barrel shift (A, imm8)

0

long (A) ← Logical right barrel shift (A, imm8)

0

long (A) ← Logical left barrel shift (A, imm8)

0

–

*

–

*

*

*

–

–

–

–

–

*

–

*

*

*

–

–

–

–

–

*

–

*

*

–

–

–

–

–

Note: For (a) and (b), refer to “Table 4 Number of Execution Cycles in Addressing Modes” and “Table 5 Correction

Values for Number of Cycles for Calculating Actual Number of Cycles.”

*1: Set to 3 when R0 is 0, otherwise 3 + (R0).
*2: Set to 3 when R0 is 0, otherwise 4 + (R0).
*3: Set to 3 when imm8 is 0, otherwise 3 + imm8.
*4: Set to 3 when imm8 is 0, otherwise 4 + imm8.

89

MB90210 Series

Table 20 Branch 1 [31 Instructions]

Mnemonic # ~ B Operation

Branch if (Z) = 1

BZ/BEQ rel
BNZ/BNE rel
BC/BLO rel
BNC/BHS rel
BN rel
BP rel
BV rel
BNV rel
BT rel
BNT rel
BLT rel
BGE rel
BLE rel
BGT rel
BLS rel
BHI rel
BRA rel

JMP

@A

JMP addr16
JMP @ear
JMP @eam
JMPP @ear *
JMPP @eam *
JMPP addr24

CALL @ear *
CALL @eam *
CALL addr 16 *
CALLV #vct4 *
CALLP @ear *

*1

2

*1

2

*1

2

*1

2

*1

2

*1

2

*1

2

*1

2

*1

2

*1

2

*1

2

*1

2

*1

2

*1

2

*1

2

*1

2

*1

2

2

1

2

3

3

2

4 + (a)

2 +

3

3

2 +

4

4

2 +

5

5

6

2
4
2
3

1
2

3

4 + (a)

3
4

5 + (a)

5
5
7

0

Branch if (Z) = 0

0

Branch if (C) = 1

0

Branch if (C) = 0

0

Branch if (N) = 1

0

Branch if (N) = 0

0

Branch if (V) = 1

0

Branch if (V) = 0

0

Branch if (T) = 1

0

Branch if (T) = 0

0

Branch if (V) xor (N) = 1

0

Branch if (V) xor (N) = 0

0

Branch if ((V) xor (N)) or (Z) = 1

0

Branch if ((V) xor (N)) or (Z) = 0

0
0

Branch if (C) or (Z) = 1

0

Branch if (C) or (Z) = 0

0

Branch unconditionally

0

word (PC) ← (A)

0

word (PC) ← addr16

0

word (PC) ← (ear)

(c)

word (PC) ← (eam)

word (PC) ← (ear), (PCB) ← (ear + 2)

0

word (PC) ← (eam), (PCB) ← (eam + 2)

(d)

0

word (PC) ← ad24 0 – 15,
(PCB) ← ad24 16 – 23

(c)

word (PC) ← (ear)

2 × (c)

word (PC) ← (eam)

(c)

word (PC) ← addr16

2 × (c)

Vector call instruction

2 × (c)

word (PC) ← (ear) 0 – 15
(PCB) ← (ear) 16 – 23

CALLP @eam *

6

2 +

8 + (a)

*2

word (PC) ← (eam) 0 – 15
(PCB) ← (eam) 16 – 23

CALLP addr 24 *

7

4

2 × (c)

7

word (PC) ← addr0 – 15,
(PCB) ← addr16 – 23

LH AH

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

ISTNZVCRMW

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

Note: For (a), (c) and (d), refer to “T ab le 4 Number of Execution Cycles in Addressing Modes” and “T able 5 Correction

Values for Number of Cycles for Calculating Actual Number of Cycles.”

*1: Set to 3 when branch is executed, and 2 when branch is not executed.
*2: 3 × (c) + (b)
*3: Reads (word) of the branch destination address.
*4: W pushes to stack (word), and R reads (word) of the branch destination address.
*5: Pushes to stack (word).
*6: W pushes to stack (long), and R reads (long) of the branch destination address.
*7: Pushes to stack (long).

90

MB90210 Series

Table 21 Branch 2 [20 Instructions]

Mnemonic # ~ B Operation

CBNE A, #imm8, rel
CWBNE A, #imm16, rel

CBNE ear, #imm8, rel
CBNE eam, #imm8, rel
CWBNE ear, #imm16, rel
CWBNE eam, #imm16, rel

DBNZ ear, rel
DBNZ eam, rel

DWBNZ ear, rel
DWBNZ eam, rel

INT #vct8
INT addr16
INTP addr24
INT9
RETI
RETIQ *

6

3
4

4

4 +

5

5 +

3

3 +

3

3 +

2
3
4
1
1
2

*1
*1

*1
*3
*1
*3

*2
*4

*2
*4

14
12
13
14

9

11

0
0

0

(b)

0

(c)

0

2 × (b)

0

2 × (c)

8 × (c)
6 × (c)
6 × (c)
8 × (c)
6 × (c)

*5

Branch if byte (A) ≠ imm8

Branch if word (A) ≠ imm16
Branch if byte (ear) ≠ imm8

Branch if byte (eam) ≠ imm8
Branch if word (ear) ≠ im m1 6
Branch if word (eam) ≠ im m16

byte (ear) = (ear) – 1,
Branch if (ear) ≠ 0
byte (eam) = (eam) – 1,
Branch if (eam) ≠ 0

word (ear) = (ear) – 1,
Branch if (ear) ≠ 0
word (eam) = (eam) – 1,
Branch if (eam) ≠ 0

Software interrupt
Software interrupt
Software interrupt
Software interrupt
Return from interrupt
Return from interrupt

LH AH

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

ISTNZVCRMW

–

–

–

*

*

*

*

–

–

–

–

*

*

*

*

–

–

–

–

*

*

*

*

–

–

–

–

*

*

*

*

–

–

–

–

*

*

*

*

–

–

–

–

*

*

*

*

–

–

–

–

*

*

*

–

–

–

–

–

*

*

*

–

*

–

–

–

*

*

*

–

–

–

–

–

*

*

*

–

*

R

S

–

–

–

–

–

–

R

S

–

–

–

–

–

–

R

S

–

–

–

–

–

–

R

S

–

–

–

–

–

–

*

*

*

*

*

*

*

–

*

*

*

*

*

*

*

–

LINK #imm8

2

6

Stores old frame pointer in

(c)

–

–

–

–

–

–

–

–

–

–
the beginning of the
function, set new frame
pointer, and reserves local
pointer area

UNLINK

1

5

Restore old frame pointer

(c)

–

–

–

–

–

–

–

–

–

–
from stack in the end of
the function

RET *
RETP *

7

8

1

4

1

5

Return from subroutine

(c)

Return from subroutine

(d)

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

Note: For (a) to (d), refer to “Table 4 Number of Execution Cycles in Addressing Modes” and “Table 5 Correction

Values for Number of Cycles for Calculating Actual Number of Cycles.”

*1: Set to 4 when branch is executed, and 3 when branch is not executed.
*2: Set to 5 when branch is executed, and 4 when branch is not executed.
*3: Set to 5 + (a) when branch is executed, and 4 + (a) when branch is not executed.
*4: Set to 6 + (a) when branch is executed, and 5 + (a) when branch is not executed.
*5: Set to 3 × (b) + 2 × (c) when an interrupt request is issued, and 6 × (c) for return.
*6: This is a high-speed interrupt return instruction. In the instruction, an interrupt request is detected. When an

interrupt occurs, stack operation is not performed, with this instruction branching to the interrupt vector.
*7: Return from stack (word).
*8: Return from stack (long).

91

MB90210 Series

Table 22 Miscellaneous Control Types (Byte, Word, Long) [36 Instructions]

Mnemonic # ~ B Operation

word (SP) ← (SP) – 2, ((SP)) ← (A)

(c)

PUSHW A
PUSHW AH
PUSHW PS
PUSHW rlst

POPW A
POPW AH
POPW PS
POPW rlst

JCTX @A
AND

CCR, #imm8

OR CCR, #imm8

MOV RP, #imm8
MOV ILM, #imm8

MOVEA RWi, ear
MOVEA RWi, eam
MOVEA A, ear
MOVEA A, eam

ADDSP #imm8
ADDSP #imm16

MOV A, brgl
MOV brg2, A
MOV brg2, #imm8

1
1
1
2

1
1
1
2

1
2

2
2

2
2

2 +

2

2 +

2
3

2
2
3

3
3
3

*3

3
3
3

*2

9
3

3
2

2
3

2 + (a)

2

1 + (a)

3
3

*1

1
2

word (SP) ← (SP) – 2, ((SP)) ← (AH)

(c)

word (SP) ← (SP) – 2, ((SP)) ← (PS)

(c)

(PS) ← (PS) – 2n, ((SP)) ← (rlst)

*4

word (A) ← ((SP)), (SP) ← (SP) + 2

(c)

word (AH) ← ((SP)), (SP) ← (SP) + 2

(c)

word (PS) ← ((SP)), (SP) ← (SP) + 2

(c)

(rlst) ← ((SP)), (SP) ← (SP) + 2n

*4

6 × (c)

Context switch instruction

0

byte (CCR) ← (CCR) and imm8

0

byte (CCR) ← (CCR) or imm8

0

byte (RP) ← imm8

0

byte (ILM ) ← imm8

0

word (RWi) ← ear

0

word (RWi) ← eam

0

word(A) ← ear

0

word (A) ← eam

0

word (SP) ← (SP) + ext (imm8)

0

word (SP) ← (SP) + imm16

0

byte (A) ← (brgl)

0

byte (brg2) ← (A)

0

byte (brg2) ← imm8

LH AH

–

–

–

–

–

–

–

–
–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–
–
–

–

–

–

–
Z

–

–

–

–

ISTNZVCRMW

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

*

–

–

–

*

–

*
*

*

–
–

–
–
–

*

–

*

–
–

–

*

–
–

*

*

–

–

*

*

*

*

*

*

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

*

*

–

–

*

*

*

*

*

*

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

*

*

*

*

*

*

–

–

–

–

–

–

–

–

–

–

*

*

–

–

*

*

*

*

*

*

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–
–
–
–

–
–
–
–

–
–

–
–

–
–

–
–
–

–
–

–
–
–

NOP
ADB
DTB
PCB
SPB
NCC
CMR

MOVW SPCU, #imm16
MOVW SPCL, #imm16

SETSPC
CLRSPC

BTSCN A

BTSCNS A
BTSCND A

1

1

1

1

1

1

1

1

1

1

1

1

1

1

2

4

2

4

2

2

2

2

*5

2

*6

2

*7

2

0

No operation

Prefix code for accessing AD space

0

Prefix code for accessing DT space

0

Prefix code for accessing PC space

0

Prefix code for accessing SP space

0

Prefix code for no change in flag

0

Prefix for common register bank

0
0

word (SPCU) ← (imm16)

0

word (SPCL) ← (imm16)

0

Enables stack check operation.

0

Disables stack check operation.

Bit position of 1 in byte (A) from word (A)

0

Bit posi ti on ( × 2) of 1 in byte (A) from word (A)

0

Bit posi ti on ( × 4) of 1 in byte (A) from word (A)

0

–
–
–
–
–
–
–

–
–
–
–

Z
Z
Z

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–
–

–
–
–
–

–
–
–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

*

–

*

–

*

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

Note: For (a) and (c), refer to “Table 4 Number of Execution Cycles in Addressing Modes” and “Table 5 Correction

Values for Number of Cycles for Calculating Actual Number of Cycles.”

*1: PCB, ADB, SSB, USB, and SPB : 1 state

DTB : 2 states

DPR : 3 states
*2: 3 + 4 × (number of POPs)
*3: 3 + 4 × (number of PUSHes)
*4: (Number of POPs) × (c), or (number of PUSHes) × (c )
*5: Set to 3 when AL is 0, 5 when AL is not 0.
*6: Set to 4 when AL is 0, 6 when AL is not 0.
*7: Set to 5 when AL is 0, 7 when AL is not 0.

92

MB90210 Series

Table 23 Bit Manipulation Instruction [21 Instructions]

Mnemonic # ~ B Operation

byte (A) ← (dir:bp) b

(b)

3

MOVB A, dir:bp
MOVB A, addr16:bp
MOVB A, io:bp

MOVB dir:bp, A
MOVB addr16:bp, A
MOVB io:bp, A

SETB dir:bp
SETB addr16:bp
SETB io:bp

CLRB dir:bp
CLRB addr16:bp
CLRB io:bp

BBC dir:bp, rel
BBC addr16:bp, rel
BBC io:bp, rel

BBS dir:bp, rel
BBS addr16:bp, rel
BBS io:bp, rel

SBBS addr16:bp, rel

3

byte (A) ← (addr16:bp) b

(b)

3

4

byte (A) ← (io:bp) b

(b)

3

3

2 × (b)

4

3

2 × (b)

4

4

2 × (b)

4

3

2 × (b)

4

3

2 × (b)

4

4

2 × (b)

4

3

2 × (b)

4

3

2 × (b)

4

4

2 × (b)

4

3

*1

4

*1

5

*1

4

*1

4

*1

5

*1

4

2 × (b)

*2

5

bit (dir:bp) b ← (A)
bit (addr16:bp) b ← (A)
bit (io:bp) b ← (A)

bit (dir:bp) b ← 1
bit (addr16:bp) b ← 1
bit (io:bp) b ← 1

bit (dir:bp) b ← 0
bit (addr16:bp) b ← 0
bit (io:bp) b ← 0

Branch if (dir:bp) b = 0

(b)

Branch if (addr16:bp) b = 0

(b)

Branch if (io:bp) b = 0

(b)

Branch if (dir:bp) b = 1

(b)

Branch if (addr16:bp) b = 1

(b)

Branch if (io:bp) b = 1

(b)

Branch if (addr16:bp) b = 1, bit = 1

LH AH

Z
Z
Z

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

ISTNZVCRMW

–

–

*

*

–

–

–

*

–

–

*

*

–

–

–

*

–

–

*

*

–

–

–

*

–

–

*

*

–

–

–

–

–

*

*

–

–

–

–

–

*

*

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

*

–

–

–

–

–

–

*

–

–

–

–

–

–

*

–

–

–

–

–

–

*

–

–

–

–

–

–

*

–

–

–

–

–

–

*

–

–

–

–

–

–

*

–

–

–

–

–
–
–

*
*
*

*
*
*

*
*
*

–
–
–

–
–
–

*

*3

WBTS io:bp
WBTC io:bp

Note: For (b), refer to “Table 5 Correction Values for Number of Cycles for Calculating Actual Number of Cycles.”
*1: Set to 5 when branch is executed, and 4 when branch is not executed.

*2: 7 if conditions are met, 6 when conditions are not met.
*3: Indeterminate times
*4: Until conditions are met

3

*3

3

*4

Wait until (io:bp) b = 1

*4

Wait until (io:bp) b = 0

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

93

MB90210 Series

Table 24 Accumulator Manipulation Instruction (Byte, Word) [6 Instructions]

Mnemonic # ~ B Operation

byte (A) 0 – 7 ↔ (A) 8 – 15

0

3

2
2

2
2

2

1

word (AH) ↔ (AL)

0

2

1

byte sign-extension

0

1

1

word sign-extension

0

2

1

byte zero-extension

0

1

1

word zero-extension

0

1

1

Table 25 String Instruction [10 Instructions]

*2

*3

byte transfer @AH + ← @AL +,
Counter = RW0

*2

*3

byte transfer @AH – ← @AL –,
Counter = RW0

*1

*4

byte search (@AH +) – AL,
Counter = RW0

*1

5m + 6

byte search (@AH –) – AL,

*4

Counter = RW0
byte fill @AH + ← AL,

*5

Counter = RW0

SWAP
SW APW/XCH W AL, AH
EXT
EXTW
ZEXT
ZEXTW

Mnemonic # ~ B Operation

MOVS/MOVSI
MOVSD

SCEQ/SCEQI
SCEQD

FISL/FILSI

LH AH

–

–
–

–

X

X

–

–

Z

Z

–

LH AH

–
–

–
–

–

ISTNZVCRMW

–

–

–

–

–

–

–

–

–

–

–

–

–

–

*

–

–

*

*

–

–

–

–

–

*

*

–

–

–

–

–

*

R

–

–

–

–

–

*

R

–

–

–

ISTNZVCRMW

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

*

*

*

*

–

–

–

–

*

*

*

*

–

–

–

–

*

*

–

–

–
–
–
–
–
–

–
–

–
–

–

MOVSW/MO VSWI
MOVSWD

SCWEQ/SCWEQI
SCWEQD

FILSW/FILSWI

m: RW0 value (counter value)
*1: 3 when RW0 is 0, 2 + 6 × (RW0) when count out, and 6n + 4 when matched

*2: 4 when RW0 is 0, otherwise 2 + 6 × (RW0)
*3: (b) × (RW0)
*4: (b) × n
*5: (b) × (RW0)
*6: (c) × (RW0)
*7: (c) × n
*8: (c) × (RW0)

2
2

2
2

2

*2
*2

*1
*1

5m + 6

*6

word transfer @AH + ← @AL +,
Counter = RW0

*6

word transfer @AH – ← @AL –,
Counter = RW0

*7

word search (@AH +) – AL,
Counter = RW0
word search (@AH –) – AL,

*7

Counter = RW0
word fill @AH + ← AL,

*8

Counter = RW0

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

*

*

*

*

–

–

–

–

*

*

*

*

–

–

–

–

*

*

–

–

–

94

MB90210 Series

Table 26 Multiple Data Transfer Instructions [18 Instruction]

Mnemonic # ~ B Operation

MOVM @A, @RLi, #imm8 3 *1 *3 Multiple data transfer

byte ((A)) ← ((RLi))

MOVM @A, eam, #imm8 3 + *2 *3 Multiple data transfer

byte ((A)) ← (eam)

MOVM

addr16, @RLi, #imm8 5 *1 *3 Multiple data transfer

byte (addr16) ← ((RLi))

MOVM

addr16, @eam, #imm8 5 + *2 *3 Multiple data transfer

byte (addr16) ← (eam)

MOVMW@A, @RLi, #imm8 3 *1 *4 Multiple data transfer

word ((A)) ← ((RLi))

MOVMW@A, eam, #imm8 3 + *2 *4 Multiple data transfer

word ((A)) ← (eam)

MOVMWaddr16, @RLi, #imm8 5 *1 *4 Multiple data transfer

word (addr16) ← ((RLi))

MOVMWaddr16, @eam, #imm8 5 + *2 *4 Multiple data transfer

word (addr16) ← (eam)

MOVM @RLi, @A, #imm8 3 *1 *3 Multiple data transfer

byte ((RLi)) ← ((A))

MOVM @eam, A, #imm8 3 + *2 *3 Multiple data transfer

byte (eam) ← ((A))

MOVM

@RLi, addr16, #imm8 5 *1 *3 Multiple data transfer

byte ((RLi)) ← (addr16)

MOVM

@eam, addr16, #imm8 5 + *2 *3 Multiple data transfer

byte (eam) ← (addr16)

MOVMW@RLi, @A, #imm8 3 *1 *4 Multiple data transfer

word ((RLi)) ← ((A))

MOVMW@eam, A, #imm8 3 + *2 *4 Multiple data transfer

word (eam) ← ((A))

MOVMW@RLi, addr16, #imm8 5 *1 *4 Multiple data transfer

word ((RLi)) ← (addr16)

MOVMW@eam, addr16, #imm8 5 + *2 *4 Multiple data transfer

word (eam) ← (addr16)

MOVM bnk: addr16,

bnk: addr16, #imm8*

7 *1 *3 Multiple data transfer

5

byte (bnk: addr16) ←
(bnk: addr16)

MOVMWbnk: addr16,

bnk: addr16, #imm8*

7 *1 *4 Multiple data transfer

5

word (bnk: addr16) ←
(bnk: addr16)

LH AH

ISTNZVCRMW

––––––––– –
––––––––– –
––––––––– –
––––––––– –
––––––––– –
––––––––– –
––––––––– –
––––––––– –
––––––––– –
––––––––– –
––––––––– –
––––––––– –
––––––––– –
––––––––– –
––––––––– –
––––––––– –
––––––––– –

––––––––– –

*1: 256 when 5 + imm8 × 5, imm8 is 0.
*2: 256 when 5 + imm8 × 5 + (a), imm8 is 0.
*3: (Number of transfer cycles) × (b) × 2
*4: (Number of transfer cycles) × (c) × 2
*5: The bank register specified by bnk is the same as that for the MOVS instruction.

95

MB90210 Series

■ ORDERING INFORMATION

Part number Type Package Remarks

MB90214
MB90P214A
MB90P214B

MB90W214A
MB90W214B

MB90214PF
MB90P214PF
MB90P214BPF

MB90W214ZF
MB90W214BZF

80-pin Plastic QFP

(FPT-80P-M06)

80-pin Ceramic QFP

(FPT-80C-C02)

Only ES level

MB90V210 MB90V210CR 256-pin Ceramic PGA

(PGA-256C-A02)

For evaluation

96

■ PACKAGE DIMENSIONS

80-pin Plastic QFP

(FPT-80P-M06)

23.90±0.40(.941±.016)

64 41

65

20.00±0.20(.787±.008)

MB90210 Series

3.35(.132)MAX

0.05(.002)MIN
(STAND OFF)

40

(Mounting height)

80

LEAD No.

C

1994 FUJITSU LIMITED F80010S-3C-2

80-pin Ceramic QFP

(FPT-80C -C02)

INDEX

0.80(.0315)TYP

18.40(.724)REF

22.30±0.40(.878±.016)

Ø8.89(.350)TYP

0.10(.004)

"A"

0.35±0.10

(.014±.004)

0.16(.006)

14.00±0.20

25

241

M

"B"

12.00(.472)
REF

17.90±0.40
(.705±.016)(.551±.008)

Details of "A" part

0.18(.007)MAX

0.58(.023)MAX

17.90±0.30
(.705±.012)

+0.45
–0.15

14.00

+.018
–.006

.551

0.25(.010)

0.30(.012)

12.00(.472)

0.15±0.05(.006±.002)

Details of "B" part

REF

16.30±0.40

(.642±.016)

0 10°

0.80±0.20

(.031±.008)

Dimension s in mm (inches)

0.05(.002)MIN
(STAND OFF)

16.30±0.25

(.642±.010)

INDEX AREA

0.80(.0315)TYP

18.40(.724) REF

20.00

23.90±0.30

(.941±.012)

C

1994 FUJITSU LIMITED F80018SC-1-2

.787

+0.50
–0.20

+.020
–.008

0.35±0.10

(.014±.004)

0.15±0.05

(.006±.002)

1.45±0.20

3.30(.130)MAX

(.057±.008)

(Mounting height)

0.80±0.2022.30±0.25

(.0315±.008)(.878±.010)

Dimension s in mm (inches)

97

MB90210 Series

MEMO

98

MEMO

MB90210 Series

99

MB90210 Series

FUJITSU LIMITED

For further information please contact:

Japan

FUJITSU LIMITED
Corporate Global Business Support Division
Electronic Devices
KAWASAKI PLANT, 4-1-1, Kamikodanaka
Nakahara-ku, Kawa saki-shi
Kanagawa 211-88, Japan
Tel: [phone]
Fax: [phone]

All Rights Reserved.

The contents of this document are subject to change without
notice. Customers are advised to consult with FUJITSU sales
representatives before ordering.

http://www.fujitsu.co.jp/

North and South America

FUJITSU MICROELECTRONICS, INC.
Semiconductor Division
3545 North First Street
San Jose, CA 95134-1804, U.S.A.
Tel: [phone]
Fax: [phone]

Customer Response Center

Mon. - Fri.: 7 am - 5 pm (PST)

Tel: [phone]
Fax: [phone]

http://www.fujitsumicro.com/

Europe

FUJITSU MIKROELEKTRONIK GmbH
Am Siebenstein 6-10
D-63303 Dreieich-Buchschl ag
Germany
Tel: [phone]
Fax: [phone]

http://www.fujitsu-ede.com/

Asia Pacific

FUJITSU MICROELECTRONICS ASIA P TE LTD
#05-08, 151 Lorong Chuan
New Tech Park
Singapore 556741
Tel: [phone]
Fax: [phone]

http://www.fmap.com.sg/

The information and circ uit diagrams in this document presented
as examples of semicondu ctor device applications, and are not
intended to be incorporated in devices for actual use. Also,
FUJITSU is unable to assume responsibility for infringem ent of
any patent rights or other rights of third parties arising from the
use of this information or circuit diagrams.

FUJITSU semiconductor devices are inten ded for use in
standard applications (computers, office automation and other
office equipment, industrial, communications, and measurement
equipment, personal or household devices, etc.).
CAUTION:
Customers considering the use of ou r pr oducts in special
applications where failure or abno rmal operation may directly
affect human lives or cause physical injury or property damage,
or where extremely high levels of reliability are dema nded (such
as aerospace systems, atomic energy controls, sea floor
repeaters, vehicle operating controls, medical devices for li f e
support, etc.) are requested to consult with FUJITSU sales
representatives before such use. The company will not be
responsible for damages arising from such use without prior
approval.

Any semiconductor devices hav e inhe rently a certain rat e of
failure. You must prot ect against injur y, damage or loss from
such failures by incorporating safety design measures into your
facility and equipment such as redundancy, fire protection, and
prevention of over-current levels and other abnormal operating
conditions.

If any products described in this docume nt represent goods or
technologies subject to certain restrictions on export under the
Foreign Exchange and Foreign Trade Control Law of Japan, the
prior authorization by Japanese government should be required
for export of those products from Japan.

F9710
 FUJITSU LIMITED Printed in Japan

10