Datasheets MB1512 Datasheet

Sept. 1995
Edition 1.0a

DA TA SHEET

MB1512

SERIAL INPUT PLL FREQUENCY SYNTHESIZER

LOW POWER SERIAL INPUT PLL SYNTHESIZER

WITH 1.1GH

The Fujitsu MB1512, utilizing BI-CMOS technology , is a single chip serial input PLL
synthesizer with pulse-swallow function.
The MB1512 contains a 1.1 GH
64/65 or 128/129 divide ratio, control signal generator, 16-bit shift register, 15-bit
latch, programmable reference divider (binary 14-bit programmable reference
counter), 1-bit switch counter, phase comparator with phase conversion function,
charge pump, crystal oscillator, 19-bit shift register, 18-bit latch, programmable
divider (binary 7-bit swallow counter and binary 1 1-bit programmable counter) and
analog switch to speed up lock up time.
It operates with a supply voltage of 5V typ. and achieves very low supply current of
8mA typ. realized through the use of Fujitsu Advanced Process Technology.

Z

PRESCALER

Z

two modulus prescaler that can select of either

• High operating frequency: f

IN MAX

=1.1GHZ (P

IN MIN

=–10dBm)

• Pulse swallow function: 64/65 or 128/129

• Power supply voltage: V

• Low supply current: I

CC

=8mA typ.

CC

=4.5 to 5.5V

• Serial input 18-bit programmable divider consisting of:

Binary 7-bit swallow counter: 0 to 127
Binary 11-bit programmable counter: 16 to 2047

• Serial input 15-bit programmable reference divider consisting of:

Binary 14-bit programmable reference counter: 8 to 16383
1-bit switch counter (SW) sets divide ratio of prescaler

• On-chip analog switch achieves fast lock up time

• 2types of phase detector output

On-chip charge pump (Bipolar type)
Output for external charge pump

• Wide operating temperature: –40°C to +85°C

• 20-pin Plastic Shrink Small Outline Package

ABSOLUTE MAXIMUM RATINGS (See NOTE)

Rating Symbol Value Unit

Power Supply Voltage

Output Voltage
Open-drain Voltage

V
V

V
V

CC
P

OUT

OOP

–0.5 to +7.0

VCC to 10.0

–0.5 to V

–0.5 to 0.8

CC

+0.5

PLASTIC PACKAGE

FPT-20P-M03

PIN ASSIGNMENT

OSC

OSC-

OUT

V

GND

V
V

V

NC

V

CC

D

LD

NC

f

1

IN

2
3
4
5

P

Top View

6
7

O

8
9

10

in

V

20
19
18
17
16
15
14
13
12
11

ØR
NC
ØP
f

OUT

BISW
FC
LE
Data
NC
Clock

Output Current
Storage Temperature

I

OUT

T

STG

±10

–55 to +125

mA

°C

NOTE: Permanent device damage may occur if the above Absolute Maximum

Ratings are exceeded. Functional operation should be restricted to the

conditions as detailed in the operational sections of this data sheet.
Exposure to absolute maximum rating conditions for extended periods
may affect device reliability.

 1994 by FUJITSU LIMITED and FUJITSU MICROELECTRONICS, INC.

Copyright

This device contains circuitry to protect the inputs against
damage due to high static voltages or electric fields. How­ever, it is advised that normal precautions be taken to avoid
application of any voltage higher than maximum rated
voltages to this high impedance circuit.

1

MB1512

MB1512 BLOCK DIAGRAM

OSC

OSC

OUT

V

V

CC

D

GND

LD

1

IN

CRYSTAL
OSCILLATOR

16-BIT SHIFT REGISTER

16-BIT SHIFT REGISTER

PHASE
COMPARATOR

3

15-BIT LATCH

4

P

PROGRAMMABLE REFERENCE

5

6

O

DIVIDER

15-BIT LATCH

BINARY 14-BIT
REFERENCE COUNTER

f

r

S

W

MONITOR
FREQUENCY
CHANGING
CIRCUIT

CHARGE
PUMP

ANALOG
SWITCH

D

LE

O

7

8

19-BIT SHIFT REGISTER

19-BIT SHIFT REGISTER

CONTROL
1-BIT
LATCH

20

17

16

15

14

13

18

∅R

∅P

f

OUT

BISW

FC

LE

Data

11

Clock

18-BIT LATCH

7-BIT LATCH 11-BIT LATCH

f

10

IN

PRESCALER

PROGRAMMABLE DIVIDER

BINARY 7–BIT
SWALLOW
COUNTER

BINARY 11-BIT
PROGRAMMABLE
COUNTER

f

p

CONTROL CIRCUIT

2

PIN DESCRIPTION

MB1512

Pin No. Pin Name Description

1
3

4
5V

6

OSC
OSC

V

D

IN
OUT

P
CC

O

7 GND

I/O

Oscillator input.

I

Oscillator output.

O

A crystal is placed between OSC

and OSC

IN

OUT

– Power supply input for charge pump and analog switch.
– Power supply voltage input.

Charge pump output.

O

The characteristics of charge pump is reversed depending upon FC input.

–

Ground.
Phase comparator output.

8

Normally this pin outputs high level. While the phase difference of fr and fp exists, this

OLD

pin outputs low level.

10

12

9

NC –

f

IN

Clock11

NC

No connection.
Prescaler input.

I

The connection with an external VCO should be AC connection.
Clock input for 19-bit shift register and 16-bit shift register.

I

On rising edge of the clock shifts one bit of data into the shift registers.

– No connection.

Binary serial data input.
The last bit of the data is a control bit which specified destination of shift registers.

13 Data I

When this bit is high level and LE is high level, the data stored in shift register is trans­ferred to 15-bit latch. When this bit is low level and LE is high level, the data is trans­ferred to 18-bit latch.

.

15

17

18
20

19

Load enable input (with internal pull up resistor).
When LE is high or open, the data stored in shift register is transferred into latch de-

I14 LE

pending upon the control bit. At the time, internal charge pump output to be connected
to BISW pin because internal analog switch becomes ON state.

Phse select input of phase comparator (with internal pull up resistor).
When FC is low level, the characteristics of charge pump, phase comparator is re-

IFC

versed.
FC input signal is also used to control f

pin (test pin) output level, fr or fp.

out

Analog switch output.
Usually BISW pin is set high-impedance state. When internal analog switch is ON (LE

BISW

O16

pin is high level), this pin outputs internal charge pump state.
Minitor pin of phase comparator input.

f

pin outputs either programmable reference divider output (fr) or programmable

f

OUT

ØP
ØR

out

O

divider output (f
FC=H: It is the same as f
FC=L: It is the same as fp output level.

Outputs for external charge pump.

O

The characteristics are reversed according to FC input.

O

) depending upon FC pin input level.

p

output level.

r

∅P pin is N-channel open drain output.

2

NC

– No connection.

3

MB1512

FUNCTIONAL DESCRIPTIONS

SERIAL DATA INPUT

Serial data input is achieved by three inputs, such as Data pin, Clock pin and LE pin. Serial data input controls 15-bit programmable
reference divider and 18-bit programmable divider, respectively.
Binary serial data is input to Data pin.
On rising edge of clock shifts one bit of serial data into the internal shift registers and when load enable pin is high level or open, stored
data is transferred into latch depending upon the control bit.
Control data ”H” data is transferred into 15-bit latch.
Control data ”L” data is transferred into 18-bit latch.

PROGRAMMABLE REFERENCE DIVIDER

Programmable reference divider consists of 16-bit shift register, 15-bit latch and 14-bit reference counter . Serial 16-bit data format is
shown below.

Control bit
LSB

CS SS

S

1234

Divide ratio of programmable reference counter setting bit

S
5

Divide ratio of prescaler setting bit

S

S

S

S

S10S

6

7

8

9

11 12

MSB

SS13S14S

14-BIT PROGRAMMABLE REFERENCE COUNTER DIVIDE RA TIO

Divide

Ratio

R
8

9

S

SSS

14 13 12 11S10S9S8S7S6S5S43

00000000001000

SS

• ••••••••••••••

16383

NOTES: Divide ratio less than 8 is prohibited.

11111111111111

Divide ratio: 8 to 16383
SW:This bit selects divide ratio of prescaler.

SW=H :64/65

SW=L :128/129
S1 to S14: These bits select divide ratio of programmable reference divider.
C: Control bit (sets as high level).
Data is input from MSB side.

2

W

S
1

10010000000000

PROGRAMMABLE DIVIDER

Programmable divider consists of 19-bit shift register, 18-bit latch, 7-bit swallow counter and 11-bit programmable counter.
Serial 19-bit data format is shown following page.

4

Control bit
LSB MSB

S

S

S

S

S

S

1234

5

6

7

8

S10S

9

SS13S14SCS SS

11 12

MB1512

15S16S17S18

Divide ratio of swallow

counter

setting bit

7-BIT SWALLOW COUNTER DIVIDE RATIO

Divide

Ratio

A
0

1

S7S6S5S

0000000

SS

43

2

S
1

1000000

• •••••••

127

NOTE: Divide ratio: 0 to 127

1111111

11-BIT PROGRAMMABLE COUNTER DIVIDE RATIO

Divide

Ratio

N

S

SSS

18 17 16 15S14S13S12S11S10S9S8

Divide ratio of programmable

counter

setting bit

16
17

0000001000Ø

10001000000

• •••••••••••

2047

NOTES: Divide ratio less than 16 is prohibited.

11111111111

Divide ratio: 16 to 2047
S1 to S7: Swallow counter divide ratio setting bit. (0 to 127)
S8 to S18: Programmable counter divide ratio setting bit. (16 to 2047)
C: Control bit (sets as low level).
Data is input from MSB side.

PULSE SW ALLOW FUNCTION

f

= [(PxN)+A] xf

VCO

:Output frequency of external voltage controlled oscillator (VCO)

f

VCO

N: Preset divide ratio of binary 11-bit programmable counter (16 to 2047)
A: Preset divide ratio of binary 7-bit swallow counter (0

:Output frequency of the external reference frequency oscillator

f

OSC

R: Preset divide ratio of binary 14-bit programmable reference counter (8 to16383)
P: Preset modulus of external dual modulus prescaler (64 or 128)

OSC

÷R

≤A≤127, A<N)

5

MB1512

Data

Clock

LE

– t

≥1µs

t

1

5

S18=MSB

*(SW) (S14)

S17

SERIAL DATA INPUT TIMING

S10

S9

(S8) (S7)

S1=LSB

(S1)

C: CONTROL BIT

(C: CONTROL BIT)

t

1

t

2

t

3

NOTES: Parenthesis data is used for setting divide ratio of programmable reference divider.

On rising edge of clock shifts one bit of data in the shift register.

PHASE CHARACTERISTICS

VCO CHARACTERISTICS

FC pin is provided to change phase characteristics of phase comparator. Char­acteristics of internal charge pump output level (D

ØR, ØP) are reversed depending upon FC pin input level. Also, monitor

level (
pin (f

) output level of phase comparator is controlled by FC pin input level.

out

The relation between outputs (D
low.

fr>f

p

fr<f

p

fr=f

p

, ØR, ØP) and FC input level are shown be-

O

FC=H or open FC=L

ØR

D

O

H

L

Z

ØP

L

L

H

Z

L

Z

), phase comparator output

O

ØR

f

(f

(fr)

(f

out

D

O

L

)

r

H

Z

)

r

ØP

H

L

L

f

out

Z

)

(f

p

L

(fp)

Z

(f

)

p

VCO OUTPUT FREQUENCY

VCO INPUT VOLTAGE

t

4

t

5

1

2

Note: Z=(High impedance)

Depending upon VCO characteristics, FC pin should be set accordingly:
When VCO characteristics are like , FC should be set high or open circuit;
When VCO characteristics are like , FC should be set Low.

1
2

6

f

r

f

P

LD

MB1512

H

D

O

f

r>fp

fr=f

Z

L

p

fr<f

p

fr<f

p

fr<f

p

NOTES: Phase difference detection range: –2π to +2π

Spike appearance depends on charge pump characteristics. Also, the spike is output in order to diminish dead band.
When f

or fr<fp, spike might not appear depending upon charge pump characteristics.

r>fp

ANALOG SWITCH

ON/OFF of analog switch is controlled by LE input signal. When the analog switch is ON, internal charge pump output (DO) to be
connected to BISW pin. When the analog switch is OFF, BISW pin is set to high-impedance state.

LE=H (Changing the divide ratio of internal prescaler) : Analog switch=ON
LE=L (Normal operating mode) : Analog switch=OFF

LPF time constant is decreased in order to insert a analog switch between

Thus, lock up time is decreased, that is, fast lock up time is achieved.

D

O

CHARGE PUMP LPF-1 LPF-2 V

ANALOG SW

BISW

LPF1 and LPF2 when channel of PLL is changing.

CO

(CONTROL SIGNAL LE)

RECOMMENDED OPERATING CONDITIONS

Value

Parameter Symbol

Min Typ Max

Power Supply Voltage

Input Voltage
Operating Temperature

V

CC

V

P

V

I

T

A

4.5

CC –

GND

–40

5.0 5.5

–

–

8.0

V

CC

85

Unit

V
VV
V

°C

7

MB1512

ELECTRICAL CHARACTERISTICS

Parameter Symbol

Condition

Value

Min Typ Max

Unit

Power Supply Current

Operating Frequency

Input Sensitivity

High-level Input Voltage
Low-level Input Voltage
High-level Input Current
Low-level Input Current

Input Current

High-level Output Current
Low-level Output Current

N-channel Open Drain
Cutoff Current

f

in

OSC

IN

f

in

OSC

IN

Except fi
and OSC

Data
Clock

OSC

IN

LE, FC

Except D
and OSC-

OUT

, ØP

D

O

I

CC

f

in

f

OSC

Pf
V
V

n

IN

V
I

IH

I

IL

I

OSC

I

LE

V

O

V

I

OFF

in

OSC

IH

IL

OH

OL

Note 1
Note 2

VCC=5V

V

CC≤VP

≤8V

–

10

–

–10 6

0.5
x0.7

V

CC

–
–

–
–

–

4.4

–

–

8.0

–

12

–

–
–

–

1.0

–1.0

±50

–60

–
–

–

V

12.0

1100

20

–
–

x0.3

CC

–
–

–
–

–

0.4

1.1

mA

MHz
MHz

dBm
V

PP

V
V

µA

µA

µA
µA

V
V

µA

I

Output Current

Except D
and OSC-

OUT

Analog Switch On Resistor

NOTE 1: f
NOTE 2: AC coupling. Minimum operating frequency is measured when a capacitor 1000pF is connected.

=1.1GHz, OSCIN=12MHz, VCC=5V. Inputs are grounded and outputs are open.

in

OH

O

I

OL

R

ON

–1.0

1.0

–

–
–

25

–
–
–

mA
mA

Ω

8

TEST CIRCUIT

MB1512

VCC=5V Vp=6V

0.1µF

1000pF

P

•G

Ω

50

108765431

92

11 13 14 15 16 17 18 20

12

X’tal

19

Oscilloscope

9

MB1512

TYPICAL APPLICATION EXAMPLE

V

(6V)

PX

10kΩ

Charge Pump

12kΩ

12kΩ

10kΩ

Selection
(Internal or
external)

OUTPUT

LPF VCO

FROM
CONTROLLER

ØR ØP

20 18 17 16 15 14 13 11

19 12

f

OUT

BISW FC LE Data Clock

47kΩ 47kΩ

MB1512

134567810

29

OSC

X’tal

C

OSC

IN

OUTVp

V

CC

D

O

GND LD

6V 5V

C

1

2

f

in

1000p

V

100kΩ

CC

(5V)

33kΩ

0.1µF

0.01

µF

10kΩ

LOCK DET

10

, VPX:

V

p

8V max.
C

, C2: Depends on crystal oscillator

1

LE,FC : With internal pull up resistor
ØP : Open drain output

PACKAGE DIMENSIONS

20-LEAD PLASTIC FLAT PACKAGE

(Case No. : FPT-20P-M03)

∗.256±.004

(6.50±0.10)

INDEX

∗.173±.004

(4.40

(6.40

±0.10)

.252

±.008
±0.20)

”A”

+.008

.049

–.004

+0.20

(1.25 )

–0.10

.004(0.10)

.213(5.40) NOM

MB1512

(MOUNTING HEIGHT)

+.004

REF

.009

–.002
+0.10

(0.22 )

–0.05

.0256±.0047

(0.65

±0.12)

.230(5.85)

∗:This dimension does not include resin protruction.

1991 FUJITSU LIMITED F20012S-2C

All Rights Reserved. Circuit diagrams utilizing Fujitsu products are included as a means of
illustrating typical semiconductor applications. Complete Information sufficient for construc­tion purposes is not necessarily given. The information contained in this document has been
carefully checked and is believed to be reliable. However, Fujitsu assumes no responsibility
for inaccuracies.

+.002

.006

–.001

Details of ”A” part
.004

±.004

(0.10±0.10)

.020±.008

0°to10°

The Information contained in this document does not convey any license under the
copyrights, patent rights or trademarks claimed and owned by Fujitsu. Fujitsu reserves the
right to change products or specifications without notice. No part of this publication may be
copied or reproduced in any form or by any means, or transferred to any third party without
prior written consent of Fujitsu.

(0.50

(STAND OFF

±0.20)

+0.05

(0.15 )

–0.02

HEIGHT)

Dimensions in
inches (millimeters)

11

MB1512

For further information please contact:

Japan

FUJITSU LIMITED
Electronic Devices
International Operations Department
KAWASAKI PLANT, 1015 Kamikodanaka,
Nakahara–ku, Kawasaki–shi,
Kanagawa 211, Japan
Tel: [phone]
FAX: [phone]

North and South America

FUJITSU MICROELECTRONICS, INC.
Semiconductor Division
3545 North First Street
San Jose, CA 95134-1804, USA
Tel: [phone]
FAX: [phone]

Europe

FUJITSU MIKROELEKTRONIK GmbH
Am Siebenstein 6-10,
63303 Dreieich-Buchschlag,
Germany
Tel: [phone]
FAX: [phone]

Asia Pacific

FUJITSU MICROELECTRONICS ASIA PTE LIMITED
No.51 Bras Basah Road,
Plaza By The Park,
#06-04 to #06-07
Singapore 0718
Tel: [phone]
FAX: [phone]

9501
 FUJITSU LIMITED Printed in Japan

12