Datasheets MB1503 Datasheet

Sept. 1995
Edition 1.0a

DA TA SHEET

MB1503

LOW-POWER PLL FREQUENCY SYNTHESIZER WITH
POWER SAVE FUNCTION (1.1GHz)

The Fujitsu MB1503 is a serial input phase-locked loop (PLL) frequency synthesizer with a
pulse-swallow function. A stand-by mode is provided to limit power consumption during
intermittent operation.
The MB1503 is configured of a 1.1GHz dual-modulus prescaler with 128/129 divide ratio,
control signal generator, 16-bit shift register , 15-bit latch, programmable reference divider
(binary 14-bit programmable reference counter), 1-bit switch counter, phase comparator
with phase conversion function, charge pump, crystal oscillator, 19-bit shift register , 18-bit
latch, programmable divider (binary 7-bit swallow counter and binary 1 1-bit programmable
counter), analog switches, and an intermittent operation control circuit that selects the
operating or stand-by mode depending on the power-save control input state (PS).
The MB1503 operates from a single +5 V supply . Fujitsu’s advanced technology achieves
an Icc of 8mA, typical. The stand-by mode current consumption is just 100µA.

Features

• High operating frequency : fIN = 1.1GHz (PIN = –10dBm)

• Pulse-swallow function : High-speed dual-modulus prescaler with 128/129

divide ratio

• Low supply current : I

• Power-saving stand-by mode : 100µA

• Serial input, 18-bit programmable divider consisting of:

– Binary 7-bit swallow counter : 0 to 127
– Binary 11-bit programmable counter: 16 to 2,047

• Serial input 15-bit programmable reference divider consisting of:
– Binary 15-bit programmable reference counter: 8 to 16,383
– 1-bit switch counter sets prescaler divide ratio

• On-chip analog switch for fast lock-up

• On-chip charge pump

• Wide operating temperature range: –40 to +85°C

• Plastic 16–pin dual inline package (Suffix : –P)

Plastic 16–pin small outline package (Suffix : –PF)

= 8mA typ. at 5V

CC

PLASTIC PACKAGE

(FPT-16P-M06)

ABSOLUTE MAXIMUM RATINGS (See NOTE)

Ratings Symbol Value Unit

V

Supply Voltage

Output Voltage V
Output Current I
Storage Temperature Tstg –55 to +125 °C

NOTE: Permanent device damage may occur if the above Absolute Maximum

Ratings are exceeded. Functional operation should be restricted to the

conditions as detailed in the operational sections of this data sheet. Exposure
to absolute maximum rating conditions for extended periods may affect device
reliability .

Copyright1994 by FUJITSULIMITED

V

OUT

CC

P
OUT

–0.5 to +7.0 V

VCC ≤ VP ≤ 10.0 V

–0.5 to VCC +0.5 V

±10 mA

PLASTIC PACKAGE

(DIP-16P-M04)

This device contains circuitry to protect the inputs
against damage due to high static voltages or electric
fields. However, it is advised that normal precautions be
taken to avoid application of any voltage higher than
maximum rated voltages to this high impedance circuit.

1

MB1503

PIN ASSIGNMENT

(TOP VIEW)

OSC

IN

OSC

OUT

V

P

V

CC

D

O

116PS
215f
314f
4 13 BiSW
512FC

GND 6 11 LE

LD 7 10 Data

f

IN

8 9 Clock

R

P

2

BLOCK DIAGRAM

1

OSC

IN

PS1

OSC

V

OUT

V

CC

Oscillator

2

3

P

4

16-bit Shift Register
16-bit Shift Register

15-bit Latch
15-bit Latch

Programmable

Reference Divider

Binary 14-bit

Reference

Counter

S

W

To Lock Detector

PS1

Phase

Characteristics

Changing

Circuit

PS1

Charge

Pump

Phase

Comparator

From
Phase
Comparator

MB1503

16

PS

15

f

R

14

f

P

13

BiSW

D

GND

LD

f

IN

5

O

6

7

8

From Charge
Pump

From
Phase
Comparator

Lock

Detection

Circuit

Prescaler
Output

SW
Prescaler

MC

PS1

PS1

Intermittent

Operation

Control Circuit

19-bit Shift Register
19-bit Shift Register

18-bit Latch

7-bit Latch

Programmable Divider

Binary 7-bit

Swallow

Programmable

Counter

PS1

11-bit Latch

Binary 11-bit

Counter

1-bit

Control

Latch

Schmitt

Trigger

Schmitt

Trigger

Schmitt

Trigger

12

FC

11

LE

10

Data

9

Clock

Control Circuit

3

MB1503

PIN DESCRIPTION

Pin No. Pin Name I/O Description

1 OSC

IN

I Programmable reference divider input

Oscillator input
An external crystal is connected to this pin.

2 OSC

3V
4V

5D

OUT

P
CC

O

O Oscillator output

An external crystal is connected to this pin.

– Power supply input for charge pump and analog switch
– Power supply

O Charge pump output

The phase of the charge pump is reversed depending on the FC input.
6 GND – Ground
7 LD O Phase comparator output

The output level is high when LD is locked. The output level is low when LD is unlocked.
8f

IN

I Prescaler input

Connection with an external VCO should be done by AC coupling.
9 Clock I Clock input for 19-bit and 16-bit shift registers

Data is shifted into the shift register on the rising edge of the clock.The Schmitt trigger is

contained.

10 Data I Serial data input using binary code

The last bit of the data is a control bit.

When the control bit is high, data is transmitted to the 15-bit latch.

When it is low, data is transmitted to the 18-bit latch.The Schmitt trigger input is involved.

1 1 LE I Load enable signal input

When LE is high, the data of the shift register are transferred to a latch, depending on the

control bit in the serial data. At the same time, an internal analog switch turns on and the output

of the internal charge pump is connected to the BiSW pin.The Schmitt trigger input is involved.

12 FC I Phase select input of phase comparator (with internal pull-up resistor)

When FC is low, the characteristics of the charge pump and phase comparator are reversed.

The FC input signal is also used to control the f

pin (test pin) of fR or f

OUT

13 BiSW O Analog switch output

BiSW is usually in the high-impedance state. When the switch is turned on (LE is high), the

state of the internal charge pump is output.

14 f
15 f

P
R

O Monitor pin of programmable counter output
O Monitor pin of reference counter output

16 PS I Power save signal input

Set PS low while the system is powered (never use pin 16 as it is opened)

PS = High : Operation mode
PS = Low : Stand-by mode

4

P.

MB1503

FUNCTIONAL DESCRIPTIONS

Pulse swallow function

The divide ratio can be calculated using the following equation:
f

= [(M x N) + A] x f

VCO

: Output frequency of external voltage controlled oscillator (VCO)

f

VCO

N : Preset divide ratio of binary 11-bit programmable counter (16 to 2,047)
A : Preset divide ratio of binary 7-bit swallow counter (0 ≤ A ≤ 127)

: Output frequency of the reference frequency oscillator

f

OSC

R : Preset divide ratio of binary 14-bit programmable reference counter (8 to 16,383)
M : Preset divide ratio of modules prescaler (128)

Serial data input

Serial data is input using the Data, Clock, and LE pins. Serial data controls the 15-bit programmable reference divider and 18-bit
programmable divider separately .
Binary serial data is input to the Data pin.
One bit of data is shifted into the internal shift registers on the rising edge of the clock. When the load enable pin is high or open, stored
data is latched depending on the control data as follows:

÷ R (A < N)

OSC

Control data Destination of serial data

H 15-bit latch

L 18-bit latch

(a) Programmable reference divider ratio

The programmable reference divider consists of a 15-bit latch and a 14-bit reference counter. The serial 16-bit data format is
shown below:

Direction of data shift

Control bit
LSB

SSSSSSSSSSSSSS

C1234567891011121314SW

Divide ratio setting bit for programmable reference counter

Divide ratio setting bit for prescaler

MSB

5

MB1503

• 14-bit programmable reference counter divide ratio

Divide ratio S S S S S S SSSSSSSS

R 1413121110987654321

8 00000000001000
9 00000000001001

• ••••••••••••••

16383 1 1 1 1 1 1 1 1 1 11111

(Divide ratio = 8 to 16,383)

Notes: 1. Divide ratios less than 8 are prohibited

2. SW: This bit selects the divide ratio of the prescaler
SW Low: 128 or 129 (SW must be always be low)

3. S1 to S14: These bits select the divide ratio of the programmable reference counter (8 to 16,383)

4. C: Control bit: Set high

5. Input MSB data first

(b) Programmable divider divide ratio

The programmable divider consists of a 19-bit shift register, 18-bit latch, 7-bit swallow counter, and 11-bit programmable
counter. The serial 19-bit data format is shown below:

Direction of data shift

Control bit
LSB

SSSSSSSSSSSSSSSSSS

C123456789101112131415161718

Divide ratio setting bit for

swallow counter

Divide ratio setting bit for programmable counter

MSB

6

• 7-bit swallow counter divide ratio • 1 1-bit programmable counter divide ratio

MB1503

Divide

ratio

A

SSSSSSS

7654321

0 0000000
1 0000001

• •••••••

127 1111111

Divide

ratio

N

SSSSSSSSSSS

18 17 16 15 14 13 12 11 10 9 8

16 00000010000
17 00000010001

• •••••••••••

2047 1 1 1 11111111

(Divide ratio = 0 to 127) (Divide ratio = 16 to 2,047)

Notes: 1. Divide ratios less than 16 are prohibited for the 11–bit programmable counter

2. S1 to S7: These bits select the divide ratio of the swallow counter (0 to 127)

3. S8 to S18: These bits select the divide ratio of the programmable counter (16 to 2,047)

4. C: Control bit: (Set low)

5. Input MSB data first

Serial data input timing

• t1 (≥ 1µs) : Data setup time t2 (≥ 1µs) : Data hold time t3 (≥ 1µs) : Clock pulse width
(≥ 1µs) : LE setup time to the rising edge of last clock t5 (≥ 1µs) : LE pulse width

t

4

Data

S18 =

MSB

S17 S10 S9

S1 =

LSB

C: Control bit

(S14) (S8) (S7) (S1) (C: Control bit)(SW) (∗1)

Clock

LE

t

1

t

2

t

3

t

5

t

4

∗1 : Bits enclosed in parentheses are used when the divide ratio of the programmable reference divider is selected.
Note: One bit of data is shifted into the shift register on the rising edge of the clock.

7

MB1503

Intermittent operation

Intermittent operation limits power consumption by shutting down or starting the internal circuits according to their necessity . If device
operation resumes uncontrolled, the error signal output from the phase comparator may exceed the limit due to an undefined phase
relationship between the reference frequency (fR) and the comparison frequency (fP) and frequency lock is lost.
To prevent this, an intermittent operation control circuit is provided to decrease the variation in the locking frequency by forcibly
correcting the phase of both frequencies to limit the error signal output. This is done by the PS control circuit. If PS is set high, the
circuit enters the operating mode. If PS is set low, operation stops and the device enters the stand-by mode. Each mode is explained
below:

• Operating mode (PS =High Level)

All circuits are operating, and PLL operation is normal.

• Stand-by mode (PS = Low level)

Circuits that do not affect operation are powered down to limit current consumption.
The current in the power save state is typically 100µA.
At this time, the levels of D
Since D

is placed in the high-impedance state and the input voltage of the voltage controlled oscillator (VCO) is set to the voltage

O

in the operating mode (when locked) by the time constant of the low-pass filter, the frequency output from the VCO (f
the locking frequency.

The operating and stand-by modes alternate repeatedly . This intermittent operation limits the error signal by forcibly correcting the
phase of the reference and comparison frequencies to limit power consumption.
The device must be set in the stand-by mode (PS = low) when it is powered up.

and LD are the same as when the PLL is locked.

O

VCO

) is kept at

Relationship between the FC input and phase characteristics

The FC pin changes the phase characteristics of the phase comparator. The internal charge pump output level (DO) is reversed,
depending on the FC pin input level. The relationship between the FC input level and D

FC = High or open FC = Low

> f

f

R

P

f

< f

R

P

= f

f

R

P

HL

LH

Z (∗1) Z (∗1)

∗1: High impedance

When designing a synthesizer, the FC pin setting depends on the VCO characteristics.

∗: When the VCO characteristics are similar to

 , set FC high or open.

1

∗: When the VCO characteristics are similar to

 , set FC low.

2

VCO

output

frequency

is shown below:

O

1

2

VCO input voltage

8

Phase comparator output waveform (FC = High)

f

R

f

P

LD

H

D

O

f

> f

R

P

fR = f

Notes: 1. Phase difference detection range: –2π to +2π

2. Spike appearance depends on the charge pump characteristics. Also, the spike is output to diminish
dead band.

3. When f

> fP or fR < fP, a spike might not appear depending on the charge pump characteristics.

R

4. LD is low when the phase difference is tw or more. LD is high when the phase difference is tw or less for
three or more cycles (when f

Z

P

OSCIN

L

fR < f

P

fR < f

P

= 12.8MHz, tw = 625 to 1,250ns).

fR < f

MB1503

P

Analog switch

The LE signal turns the analog switch on or off. When the analog switch is turned on, the charge pump output (DO) is output through
the BiSW pin. When it is turned off, the BiSW pin is in the high-impedance state.

When LE = high (when the divide ratio of the internal divider is changed): Analog switch = on
When LE = low (normal operating mode): Analog switch = off

The LPF time constant can be decreased by inserting an analog switch between LPF1 and LPF2. This decreases the lock-up time
when the PLL channel is changed.

D

O

CHP LPF–1 LPF–2 VCO

Analog

switch

(Control signal LE)

BiSW

9

MB1503

RECOMMENDED OPERATING CONDITIONS

Parameter Symbol Unit

Supply Voltage

Input Voltage V
Operating Temperature T

Min T yp Max

V

CC

V

P

I

A

4.5 5.0 5.5 V

GND – V

–40 – +85 °C

Value

VCC ≤ VP ≤ 8.0 V

CC

V

HANDLING PRECAUTIONS

• This device should be transported and stored in anti-static containers.

• This is a static-sensitive device; take proper anti-ESD precautions. Ensure that personnel and equipment are properly grounded. Cover work-

benches with grounded conductive mats.

• Always turn the power supply off before inserting or removing the device from its socket.

• Protect leads with a conductive sheet when handling or transporting PC boards with devices.

10

ELECTRICAL CHARACTERISTICS

MB1503

Parameter Symbol Unit Condition

Supply Current I

CC

Min Typ Max

– 8.0 12.0 mA

Value

Stand-by Current IPS – 100 – µA

f

IN

f

IN

10 – 1 100 MHz

Operating Frequency

OSC
f

IN

IN

f

OSC

P

f IN

– 12 20 MHz

–10 – 6 dBm

Input Sensitivity

OSC

IN

High-level Input Voltage V
Low-level Input Voltage V

Except fIN and
OSC

IN

V

OSC

IH

IL

0.5 – – Vp–p

VCC x 0.7 – – V

––V

x 0.3 V

CC

With f

= 1.1GHz, OSCIN =

IN

12MHz, V
are V
open.

= 5.0V . Inputs

CC

and outputs are

CC

With fIN = 1.1GHz, OSCIN =
12MHz, V

= 5.0V. The

CC

PS pin is grounded, remain­ing inputs are at V
outputs are open.

CC

, and

AC coupling. The minimum
operating frequency is
measured with a 100pF ca­pacitor connected.

—
—
—
—
—

High-level Input Current I

Data, Clock,
LE

IH

I

IL

– 1.0 – µA
– –1.0 – µA

Low-level Input Current

FC I

Input Current OSC

IN

High-level Output V
Voltage

Low-level Output Voltage V

Except DO and
OSC

OUT

FC

I

OSC

OH

OL

– –60 – µA
– ±50 – µA

4.4 – – V VCC = 5V

– – 0.4 V

High-impedance V
Cut off Current V

Output Current

D

O

Except DO and
OSC

OUT

Analog Switch ON Resistance R

I

OFF

I

OH

I

OL

ON

– – 1.1 µA

–1.0 – – mA

1.0 – – mA
–25–Ω

—

—
—
—

—

= GND to 8V

DO

≤ VP ≤ 8V

CC

—
—
—

11

MB1503

TEST CIRCUIT
(FOR MEASURING PRESCALER INPUT SENSITIVITY)

P · G

50Ω

1000p

= 5V

V

CC

0.1µ

87654321

9 10111213141516

Oscilloscope

X’ tal

VP = 6V

= 5V

V

CC

12

APPLICATION EXAMPLE

MB1503

OSC

PS f

f

R

BiSW FC LE Data Clock

P

16 15 14 13 12 11 10 9

MB1513

12345678

OSC

V

P

6V

V

CCDO

5V

IN

OUT

X’ tal

C

C

1

2

GND LD f

0.1µ

LPF VCO

Output

From
controller

47K 47K

IN

1000p

VP, VPX: Maximum 8V
C

, C2: Depends on the crystal parameters

1

13

MB1503

PACKAGE DIMENSIONS

16-LEAD PLASTIC FLAT PACKAGE

(CASE No.: FPT-16P-M06)

.050(1.27)

TYP

.400

INDEX

+.010
–.008

+0.25

(10.15 )

–0.20

.018

±.004

(0.45

±0.10)

“B”

Ø.005(0.13)

.209

(5.30

(7.80

±.012
±0.30)

M

.307

±.016
±0.40)

.089(2.25)MAX

(MOUNTING HEIGHT)

.002(0.05)MIN

(STAND OFF HEIGHT)

.268

+.016
–.008

.006

+0.40

(6.80 )

–0.20

.020

±.008

(0.50

±0.20)

+.002

(0.15 )

–.001

+0.05
–0.02

.004(0.10)

.350(8.89) REF



1991 FUJITSU LIMITED F16015S-2C

“A”

Details of “A” part

.016(0.40)

.008(0.20)

.007(0.18)

MAX

.027(0.68)

MAX

Details of “B” part

.006(0.15)

.008(0.20)

.007(0.18)

MAX

.027(0.68)

MAX

Dimensions in
inches (millimeters)

14

16-LEAD PLASTIC DUAL IN-LINE PACKAGE

(CASE No.: DIP-16P-M04)

MB1503

INDEX-1

INDEX-2

+.012

.039

–0
+0.30

(0.99 )

–0

.050(1.27)

MAX

.770

+.008

(19.55 )

–.012

.100(2.54)

TYP

+0.20
–0.30

.060

(1.52 )

+.012
–0

+0.30
–0

.018

(0.46

±.003

±0.08)

.244

±.010

(6.20

±0.25)

.172(4.36)MAX

.118(3.00)MIN

.020(0.51)MIN

.300(7.62)

TYP

.010

(0.25

±.002

±0.05)

15

°MAX

1991 FUJITSU LIMITED D16033S-2C



Dimensions in
inches (millimeters)

15