Datasheet MAX7030 Datasheet (MAXIM)

Page 1

General Description

The MAX7030 crystal-based, fractional-N transceiver is designed to transmit and receive ASK/OOK data at factory-preset carrier frequencies of 315MHz, 345MHz†, or

433.92MHz with data rates up to 33kbps (Manchester encoded) or 66kbps (NRZ encoded). This device generates a typical output power of +10dBm into a 50Ω load and exhibits typical sensitivity of -114dBm. The MAX7030 features separate transmit and receive pins (PAOUT and LNAIN) and provides an internal RF switch that can be used to connect the transmit and receive pins to a common antenna.

The MAX7030 transmit frequency is generated by a 16bit, fractional-N, phase-locked loop (PLL), while the receiver’s local oscillator (LO) is generated by an integer-N PLL. This hybrid architecture eliminates the need for separate transmit and receive crystal reference oscillators because the fractional-N PLL is preset to be

10.7MHz above the receive LO. Retaining the fixed-N PLL for the receiver avoids the higher current-drain requirements of a fractional-N PLL and keeps the receiver current drain as low as possible. All frequencygeneration components are integrated on-chip, and only a crystal, a 10.7MHz IF filter, and a few discrete components are required to implement a complete antenna/digital data solution.

The MAX7030 is available in a small, 5mm x 5mm, 32pin thin QFN package, and is specified to operate over the automotive -40°C to +125°C temperature range.

Applications

2-Way Remote Keyless Entry

Security Systems

Home Automation

Remote Controls

Remote Sensing

Smoke Alarms

Garage Door Openers

Local Telemetry Systems

Features

o +2.1V to +3.6V or +4.5V to +5.5V Single-Supply

Operation

o Single-Crystal Transceiver

o Factory-Preset Frequency (No Serial Interface

Required)

o ASK/OOK Modulation

o +10dBm Output Power into 50Ω Load

o Integrated TX/RX Switch

o Integrated Transmit and Receive PLL, VCO, and

Loop Filter

o > 45dB Image Rejection

o Typical RF Sensitivity*: -114dBm

o Selectable IF Bandwidth with External Filter

o < 12.5mA Transmit-Mode Current

o < 6.7mA Receive-Mode Current

o < 800nA Shutdown Current

o Fast-On Startup Feature, < 250µs

o Small, 32-Pin, Thin QFN Package

MAX7030

Low-Cost, 315MHz, 345MHz, and 433.92MHz

ASK Transceiver with Fractional-N PLL

________________________________________________________________

Maxim Integrated Products

Ordering Information

19-3706; Rev 3; 11/10

For pricing, delivery, and ordering information, please contact Maxim Direct at 1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com.

Product Selector Guide

0.2% BER, 4kbps Manchester-encoded data, 280kHz IF BW

Denotes a lead(Pb)-free/RoHS-compliant package.

EP = Exposed pad. Note: The MAX7030 is available with factory-preset operating frequencies. See the

Product Selector Guide

for complete part

numbers.

Pin Configuration, Typical Application Circuit, and Functional Diagram appear at end of data sheet.

†

Contact factory for availability.

†

345

PART TEMP RANGE PIN-PACKAGE

MAX7030_ATJ+ -40°C to +125°C 32 Thin QFN-EP**

PART CARRIER FREQUENCY (MHz)

MAX7030LATJ+ 315

MAX7030MATJ+

MAX7030HATJ+ 433.92

Page 2

MAX7030

Low-Cost, 315MHz, 345MHz, and 433.92MHz ASK Transceiver with Fractional-N PLL

2 _______________________________________________________________________________________

ABSOLUTE MAXIMUM RATINGS

Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.

HVIN to GND .........................................................-0.3V to +6.0V

PAVDD, AVDD, DVDD to GND..............................-0.3V to +4.0V

ENABLE, T/R, DATA, AGC0, AGC1,

AGC2 to GND .......................................-0.3V to (V

HVIN

+ 0.3V)

All Other Pins to GND .............................-0.3V to (V

_VDD

+ 0.3V)

Continuous Power Dissipation (T

= +70°C) 32-Pin Thin QFN (derate 21.3mW/°C

above +70°C).............................................................1702mW

Operating Temperature Range .........................-40°C to +125°C

Storage Temperature Range .............................-65°C to +150°C

Lead Temperature (soldering, 10s) .................................+300°C

Soldering Temperature (reflow) .......................................+260°C

DC ELECTRICAL CHARACTERISTICS

(

Typical Application Circuit

, 50Ω system impedance, V

AVDD

= V

DVDD

= V

HVIN

= V

PAVDD

= +2.1V to +3.6V, fRF= 315MHz, 345MHz, or

433.92MHz, T

= -40°C to +125°C, unless otherwise noted. Typical values are at V

AVDD

= V

DVDD

= V

HVIN

= V

PAVDD

= +2.7V,

= +25°C, unless otherwise noted.) (Note 1)

Supply Voltage (3V Mode) V

Supply Voltage (5V Mode) HVIN

Supply Current I

Voltage Regulator V

DIGITAL I/O

Input-High Threshold V

Input-Low Threshold V

PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS

REG

HVIN, PAVDD, AVDD, and DVDD connected to power supply

PAVDD, AVDD, and DVDD unconnected from HVIN, but connected together

Transmit mode, PA off, V

DATA

cycle (Note 2)

Transmit mode, V at 50% duty cycle (Notes 3, 4)

Transmit mode, V at 100% duty cycle (Note 2)

TA < +85°C, typ at +25°C (Note 4)

TA < +125°C, typ at +125°C (Note 2)

HVIN

(Note 2)

at 0% duty

= 5V, I

DATA

= 15mA 3.0 V

LOAD

fRF = 315MHz 3.5 5.4

= 434MHz 4.3 6.7

fRF = 315MHz 7.6 12.3

= 434MHz 8.4 13.6

fRF = 315MHz 11.6 19.1

= 434MHz 12.4 20.4

Receiver 315MHz 6.1 7.9

Receiver 434MHz 6.4 8.3

Deep-sleep (3V mode)

Deep-sleep (5V mode)

Receiver 315MHz 6.4 8.2

Receiver 434MHz 6.7 8.4

Deep-sleep (3V mode)

Deep-sleep (5V mode)

2.1 2.7 3.6 V

4.5 5.0 5.5 V

0.9 x

HVIN

0.8 8.8

2.4 10.9

8.0 34.2

14.9 39.3

0.1 x

HVIN

µA

Page 3

MAX7030

Low-Cost, 315MHz, 345MHz, and 433.92MHz

ASK Transceiver with Fractional-N PLL

_______________________________________________________________________________________ 3

AC ELECTRICAL CHARACTERISTICS

(

Typical Application Circuit

, 50Ω system impedance, V

PAVDD

= V

AVDD

= V

DVDD

= V

HVIN

= +2.1V to +3.6V, fRF= 315MHz, 345MHz, or

433.92MHz, T

= -40°C to +125°C, unless otherwise noted. Typical values are at V

PAVDD

= V

AVDD

= V

DVDD

= V

HVIN

= +2.7V,

= +25°C, unless otherwise noted.) (Note 1)

DC ELECTRICAL CHARACTERISTICS (continued)

(

Typical Application Circuit

, 50Ω system impedance, V

AVDD

= V

DVDD

= V

HVIN

= V

PAVDD

= +2.1V to +3.6V, fRF= 315MHz, 345MHz, or

433.92MHz, T

= -40°C to +125°C, unless otherwise noted. Typical values are at V

AVDD

= V

DVDD

= V

HVIN

= V

PAVDD

= +2.7V,

= +25°C, unless otherwise noted.) (Note 1)

PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS

Pulldown Sink Current AGC 0- 2, E N ABLE , T/R, D ATA ( V

Output-Low Voltage V

Output-High Voltage V

= 500µA 0.15 V

SINK

SOURCE

= 500µA V

PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS

GENERAL CHARACTERISTICS

Frequency Range

Maximum Input Level P

Transmit Efficiency 100% Duty Cycle

Transmit Efficiency 50% Duty Cycle

RFIN

fRF = 315MHz (Note 6) 32

fRF = 315MHz (Note 6) 24

ENABLE or T/R transition low to high, transmitter frequency settled to within 50kHz of the desired carrier

= 434MHz (Note 6) 30

= 434MHz (Note 6) 22

= 5.5V ) 20 µA

H V I N

- 0.26 V

H V IN

315/345/

433.92

0 dBm

200

MHz

ENABLE or T/R transition low to high,

Power-On Time t

transmitter frequency settled to within 5kHz

350

µs

of the desired carrier

ENABLE transition low to high, or T/R transition high to low, receiver startup time

250

(Note 5)

RECEIVER

Sensitivity

0.2% BER, 4kbps Manchester data rate, 280kHz IF BW, average RF power

315MHz -114

dBm

434MHz -113

Image Rejection 46 dB

POWER AMPLIFIER

TA = +25°C (Note 4) 4.6 10.0 15.5

Output Power P

OUT

TA = +125°C, V

= +2.1V (Note 2)

HVIN

TA = -40°C, V V

= +3.6V (Note 4)

HVIN

PAVDD

= V

AVDD

= V

DVDD

3.9 6.7

13.1 15.8

dBm

Modulation Depth 82 dB

Maximum Carrier Harmonics With output-matching network -40 dBc

Reference Spur -50 dBc

Page 4

MAX7030

Low-Cost, 315MHz, 345MHz, and 433.92MHz ASK Transceiver with Fractional-N PLL

4 _______________________________________________________________________________________

AC ELECTRICAL CHARACTERISTICS (continued)

(

Typical Application Circuit

, 50Ω system impedance, V

PAVDD

= V

AVDD

= V

DVDD

= V

HVIN

= +2.1V to +3.6V, fRF= 315MHz, 345MHz, or

433.92MHz, T

= -40°C to +125°C, unless otherwise noted. Typical values are at V

PAVDD

= V

AVDD

= V

DVDD

= V

HVIN

= +2.7V,

= +25°C, unless otherwise noted.) (Note 1)

PHASE-LOCKED LOOP

Transmit VCO Gain K

Transmit PLL Phase Noise

Receive VCO Gain 340 MHz/V

Receive PLL Phase Noise

Loop Bandwidth

Reference Frequency Input Level 0.5 V

LOW-NOISE AMPLIFIER/MIXER (Note 8)

LNA Input Impedance Z

Voltage-Conversion Gain

Input-Referred, 3rd-Order Intercept Point

Mixer-Output Impedance 330 Ω

LO Signal Feedthrough to Antenna

RSSI

Input Impedance 330 Ω

Operating Frequency f

3dB Bandwidth 10 MHz

Gain 15 mV/dB

ANALOG BASEBAND

Maximum Data-Filter Bandwidth 50 kHz

Maximum Data-Slicer Bandwidth 100 kHz

Maximum Peak-Detector Bandwidth

Maximum Data Rate

PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS

VCO

10kHz offset, 200kHz loop BW -68

1MHz offset, 200kHz loop BW -98

10kHz offset, 500kHz loop BW -80

1MHz offset, 500kHz loop BW -90

Transmit PLL 200

Receive PLL 500

INLNA

IIP3

Normalized to 50Ω

High-gain state

Low-gain state

High-gain state -42

Low-gain state -6

Manchester coded 33

Nonreturn to zero (NRZ) 66

fRF = 315MHz 1 - j4.7

fRF = 315MHz 50

fRF = 315MHz 13

= 434MHz 1- j3.3

= 434MHz 45

= 434MHz 9

340 MHz/V

-100 dBm

10.7 MHz

50 kHz

dBc/Hz

kHz

P-P

dBm

kbps

Page 5

MAX7030

Low-Cost, 315MHz, 345MHz, and 433.92MHz

ASK Transceiver with Fractional-N PLL

_______________________________________________________________________________________ 5

AC ELECTRICAL CHARACTERISTICS (continued)

(

Typical Application Circuit

, 50Ω system impedance, V

PAVDD

= V

AVDD

= V

DVDD

= V

HVIN

= +2.1V to +3.6V, fRF= 315MHz, 345MHz, or

433.92MHz, T

= -40°C to +125°C, unless otherwise noted. Typical values are at V

PAVDD

= V

AVDD

= V

DVDD

= V

HVIN

= +2.7V,

= +25°C, unless otherwise noted.) (Note 1)

Note 1: Supply current, output power, and efficiency are greatly dependent on board layout and PAOUT match. Note 2: 100% tested at T

= +125°C. Guaranteed by design and characterization overtemperature.

Note 3: 50% duty cycle at 10kHz ASK data (Manchester coded). Note 4: Guaranteed by design and characterization. Not production tested. Note 5: Time for final signal detection; does not include baseband filter settling. Note 6: Efficiency = P

OUT

/(VDDx IDD).

Note 7: Dependent on PCB trace capacitance. Note 8: Input impedance is measured at the LNAIN pin. Note that the impedance at 315MHz includes the 12nH inductive degenera-

tion from the LNA source to ground. The impedance at 434MHz includes a 10nH inductive degeneration connected from the LNA source to ground. The equivalent input circuit is 50Ω in series with ~2.2pF. The voltage conversion is measured with the LNA input-matching inductor, the degeneration inductor, and the LNA/mixer tank in place, and does not include the IF filter insertion loss.

Typical Operating Characteristics

(

Typical Application Circuit

, V

PAVDD

= V

AVDD

= V

DVDD

= V

HVIN

= +3.0V, fRF= 433.92MHz, IF BW = 280kHz, 4kbps Manchester encod-

ed, 0.2% BER, T

= +25°C, unless otherwise noted.)

SUPPLY CURRENT vs. SUPPLY VOLTAGE

MAX7030 toc01

SUPPLY VOLTAGE (V)

SUPPLY CURRENT (mA)

3.33.02.72.4

5.8

6.0

6.2

6.4

6.6

6.8

7.0

5.6

2.1 3.6

+85°C

+125°C

+25°C

-40°C

SUPPLY CURRENT vs. RF FREQUENCY

MAX7030 toc02

RF FREQUENCY (MHz)

SUPPLY CURRENT (mA)

425400325 350 375

6.1

6.2

6.3

6.4

6.5

6.6

6.7

6.8

6.0 300 450

+85°C

+125°C

+25°C

-40°C

DEEP-SLEEP CURRENT vs. TEMPERATURE

MAX7030 toc03

TEMPERATURE (°C)

DEEP-SLEEP CURRENT (µA)

1108535 60-10-15

-40

VCC = +3.6V

VCC = +3.0V

VCC = +2.1V

RECEIVER

PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS

CRYSTAL OSCILLATOR

Crystal Frequency f

Frequency Pulling by V

Crystal Load Capacitance (Note 7) 4.5 pF

XTAL

-10.7)

/24

MHz

2 ppm/V

Page 6

MAX7030

Low-Cost, 315MHz, 345MHz, and 433.92MHz ASK Transceiver with Fractional-N PLL

6 _______________________________________________________________________________________

Typical Operating Characteristics (continued)

(

Typical Application Circuit

, V

PAVDD

= V

AVDD

= V

DVDD

= V

HVIN

= +3.0V, fRF= 433.92MHz, IF BW = 280kHz, 4kbps Manchester encod-

ed, 0.2% BER, T

= +25°C, unless otherwise noted.)

RECEIVER

BIT-ERROR RATE

vs. AVERAGE INPUT POWER

100

BIT-ERROR RATE (%)

0.2% BER

0.1

fRF = 315MHz

0.01

-121 -111 AVERAGE INPUT POWER (dBm)

fRF = 434MHz

-113-115-117-119

MAX7030 toc04

-102

-105

-108

-111

SENSITIVITY (dBm)

-114

-117

-120

SENSITIVITY vs. TEMPERATURE

fRF = 434MHz

fRF = 315MHz

-40 TEMPERATURE (°C)

1.8

RSSI vs. RF INPUT POWER

1.6

MAX7030 toc05

1.4

HIGH-GAIN MODE

1.2

1.0

RSSI (V)

0.8

0.6

0.4

0.2 AGC HYSTERESIS: 3dB

11085603510-15

-130 10

LOW-GAIN MODE

RF INPUT POWER (dBm)

AGC SWITCH POINT

-10-30-70 -50-90-110

MAX7030 toc06

RSSI AND DELTA vs. IF INPUT POWER

2.1

1.8

1.5

1.2

RSSI (V)

0.9

0.6

0.3

-90 10

RSSI

IF INPUT POWER (dBm)

NORMALIZED IF GAIN vs. IF FREQUENCY

-4

-8

-12

NORMALIZED IF GAIN (dB)

-16

MAX7030 toc07

DELTA

-10-30-50-70

3.5

2.5

1.5

0.5

-0.5

-1.5

-2.5

-3.5

MAX7030 toc10

DELTA (%)

SYSTEM GAIN (dBm)

-10

-20 030

-6

-12

S11 (dB)

-18

SYSTEM GAIN vs. IF FREQUENCY

UPPER SIDEBAND

48dB IMAGE

REJECTION

IF FREQUENCY (MHz)

FROM RFIN

TO MIXOUT

= 434MHz

LOWER SIDEBAND

252015105

S11 vs. RF FREQUENCY

433.92MHz

MAX7030 toc08

IMAGE REJECTION (dB)

-40

MAX7030 toc11

IMAGE REJECTION vs. TEMPERATURE

fRF = 433MHz

fRF = 315MHz

11085603510-15

TEMPERATURE (°C)

S11 SMITH PLOT OF R

433MHz

400MHz

FIN

500MHz

MAX7030 toc09

MAX7030 toc12

-20 1100

IF FREQUENCY (MHz)

-24 200 500

RF FREQUENCY (MHz)

450400350300250

Page 7

MAX7030

Low-Cost, 315MHz, 345MHz, and 433.92MHz

ASK Transceiver with Fractional-N PLL

_______________________________________________________________________________________

Typical Operating Characteristics (continued)

(

Typical Application Circuit

, V

PAVDD

= V

AVDD

= V

DVDD

= V

HVIN

= +3.0V, fRF= 433.92MHz, IF BW = 280kHz, 4kbps Manchester encod-

ed, 0.2% BER, T

= +25°C, unless otherwise noted.)

RECEIVER

INPUT IMPEDANCE

vs. INDUCTIVE DEGENERATION

MAX7030 toc13

INDUCTIVE DEGENERATION (nH)

REAL IMPEDANCE (Ω)

IMAGINARY IMPEDANCE (Ω)

-280

-270

-260

-250

-240

-230

-220

-290

1100

fRF = 315MHz

IMAGINARY

IMPEDANCE

REAL IMPEDANCE

PHASE NOISE vs. OFFSET FREQUENCY

-50

-60

-70

fRF = 315MHz

MAX7030 toc15

INPUT IMPEDANCE

vs. INDUCTIVE DEGENERATION

REAL IMPEDANCE (Ω)

1100

fRF = 434MHz

IMAGINARY

IMPEDANCE

REAL IMPEDANCE

INDUCTIVE DEGENERATION (nH)

MAX7030 toc14

-150

-160

-170

-180

-190

-200

-210

-220

IMAGINARY IMPEDANCE (Ω)

PHASE NOISE vs. OFFSET FREQUENCY

-50

-60

-70

fRF = 433MHz

MAX7030 toc16

-80

-90

PHASE NOISE (dBc/Hz)

-100

-110

-120 100 10M

OFFSET FREQUENCY (Hz)

1M100k10k1k

-80

-90

PHASE NOISE (dBc/Hz)

-100

-110

-120 1M100k10k1k100 10M

OFFSET FREQUENCY (Hz)

Page 8

MAX7030

Low-Cost, 315MHz, 345MHz, and 433.92MHz ASK Transceiver with Fractional-N PLL

8 _______________________________________________________________________________________

Typical Operating Characteristics (continued)

(

Typical Application Circuit

, V

PAVDD

= V

AVDD

= V

DVDD

= V

HVIN

= +3.0V, fRF= 433.92MHz, IF BW = 280kHz, 4kbps Manchester encod-

ed, 0.2% BER, TA= +25°C, unless otherwise noted.)

SUPPLY CURRENT vs. SUPPLY VOLTAGE

MAX7030 toc17

SUPPLY VOLTAGE (V)

SUPPLY CURRENT (mA)

3.33.02.72.4

2.1 3.6

fRF = 315MHz PA ON WITHOUT ENVELOPE SHAPING

TA = +85°C

TA = +125°C

TA = -40°C

TA = +25°C

SUPPLY CURRENT (mA)

2.5

3.0

3.5

4.0

5.0

4.5

5.5

6.0

2.0

SUPPLY CURRENT

vs. SUPPLY VOLTAGE

MAX7030 toc18

SUPPLY VOLTAGE (V)

3.33.02.72.42.1 3.6

fRF = 315MHz PA OFF

TA = +85°C

TA = +125°C

TA = -40°C

TA = +25°C

SUPPLY CURRENT vs. SUPPLY VOLTAGE

MAX7030 toc19

SUPPLY VOLTAGE (V)

SUPPLY CURRENT (mA)

3.33.02.72.4

2.1 3.6

fRF = 434MHz PA ON WITHOUT ENVELOPE SHAPING

TA = +85°C

TA = +125°C

TA = -40°C

TA = +25°C

SUPPLY CURRENT (mA)

3.0

3.5

4.0

5.0

4.5

5.5

6.0

SUPPLY CURRENT

vs. SUPPLY VOLTAGE

MAX7030 toc20

SUPPLY VOLTAGE (V)

3.33.02.72.42.1 3.6

fRF = 434MHz PA OFF

TA = +85°C

TA = +125°C

TA = -40°C

TA = +25°C

SUPPLY CURRENT vs. OUTPUT POWER

AVERAGE OUTPUT POWER (dBm)

62-10 -6 -2

-14 10

MAX7030 toc21

SUPPLY CURRENT (mA)

fRF = 315MHz PA ON ENVELOPE SHAPING ENABLED

PA ON

50% DUTY CYCLE

SUPPLY CURRENT vs. OUTPUT POWER

AVERAGE OUTPUT POWER (dBm)

62-10 -6 -2

-14 10

MAX7030 toc22

SUPPLY CURRENT (mA)

fRF = 434MHz PA ON ENVELOPE SHAPING ENABLED

PA ON

50% DUTY CYCLE

SUPPLY CURRENT AND OUTPUT POWER

vs. EXTERNAL RESISTOR

MAX7030 toc23-1

EXTERNAL RESISTOR (Ω)

SUPPLY CURRENT (mA)

1k1001 10

0.1 10k

-12

-8

-4

-16

OUTPUT POWER (dBm)

fRF = 315MHz PA ON

POWER

CURRENT

SUPPLY CURRENT AND OUTPUT POWER

vs. EXTERNAL RESISTOR

MAX7030 toc23-2

EXTERNAL RESISTOR (Ω)

SUPPLY CURRENT (mA)

1k1001 10

0.1 10k

-12

-8

-4

-16

OUTPUT POWER (dBm)

fRF = 433MHz PA ON

POWER

CURRENT

TRANSMITTER

Page 9

MAX7030

Low-Cost, 315MHz, 345MHz, and 433.92MHz

ASK Transceiver with Fractional-N PLL

_______________________________________________________________________________________

Typical Operating Characteristics (continued)

(

Typical Application Circuit

, V

PAVDD

= V

AVDD

= V

DVDD

= V

HVIN

= +3.0V, fRF= 433.92MHz, IF BW = 280kHz, 4kbps Manchester

encoded, 0.2% BER, TA= +25°C, unless otherwise noted.)

TRANSMITTER

OUTPUT POWER vs. SUPPLY VOLTAGE

fRF = 315MHz PA ON ENVELOPE SHAPING DISABLED

TA = -40°C

TA = +25°C

OUTPUT POWER (dBm)

TA = +85°C

2.1 3.6 SUPPLY VOLTAGE (V)

OUTPUT POWER vs. SUPPLY VOLTAGE

fRF = 434MHz PA ON ENVELOPE SHAPING ENABLED

OUTPUT POWER (dBm)

2.1 3.6

TA = -40°C

TA = +25°C

TA = +85°C

SUPPLY VOLTAGE (V)

TA = +125°C

3.33.02.72.4

MAX7030 24-1

MAX7030 25-2

OUTPUT POWER vs. SUPPLY VOLTAGE

fRF = 315MHz PA ON ENVELOPE SHAPING ENABLED

TA = +25°C

OUTPUT POWER (dBm)

2.1 3.6

EFFICIENCY vs. SUPPLY VOLTAGE

fRF = 315MHz PA ON

EFFICIENCY (%)

2.1 3.6

OUTPUT POWER vs. SUPPLY VOLTAGE

fRF = 434MHz PA ON

TA = -40°C

MAX7030 24-2

TA = +125°C

TA = +85°C

3.33.02.72.4

SUPPLY VOLTAGE (V)

TA = -40°C

MAX7030 toc26

TA = +25°C

TA = +85°C

TA = +125°C

3.33.02.72.4

SUPPLY VOLTAGE (V)

ENVELOPE SHAPING DISABLED

OUTPUT POWER (dBm)

TA = -40°C

TA = +25°C

TA = +85°C

2.1 3.6 SUPPLY VOLTAGE (V)

EFFICIENCY vs. SUPPLY VOLTAGE

fRF = 434MHz PA ON

EFFICIENCY (%)

2.1 3.6 SUPPLY VOLTAGE (V)

TA = +125°C

3.33.02.72.4

TA = -40°C

TA = +25°C

TA = +85°C

TA = +125°C

3.33.02.72.4

MAX7030 25-1

MAX7030 toc27

EFFICIENCY vs. SUPPLY VOLTAGE

fRF = 315MHz 50% DUTY CYCLE

EFFICIENCY (%)

2.1 3.6 SUPPLY VOLTAGE (V)

TA = -40°C

TA = +25°C

TA = +85°C

TA = +125°C

3.33.02.72.4

MAX7030 toc28

EFFICIENCY vs. SUPPLY VOLTAGE

fRF = 434MHz 50% DUTY CYCLE

EFFICIENCY (%)

2.1 3.6 SUPPLY VOLTAGE (V)

TA = -40°C

TA = +25°C

TA = +125°C

TA = +85°C

3.33.02.72.4

-40

-50

MAX7030 toc29

-60

-70

-80

-90

-100

PHASE NOISE (dBc/Hz)

-110

-120

-130

-140

PHASE NOISE vs. OFFSET FREQUENCY

fRF = 315MHz

100 10M

OFFSET FREQUENCY (Hz)

1M100k10k1k

MAX7030 toc30

Page 10

MAX7030

Low-Cost, 315MHz, 345MHz, and 433.92MHz ASK Transceiver with Fractional-N PLL

10 ______________________________________________________________________________________

Typical Operating Characteristics (continued)

(

Typical Application Circuit

, V

PAVDD

= V

AVDD

= V

DVDD

= V

HVIN

= +3.0V, fRF= 433.92MHz, IF BW = 280kHz, 4kbps Manchester encod-

ed, 0.2% BER, TA= +25°C, unless otherwise noted.)

TRANSMITTER

PHASE NOISE vs. OFFSET FREQUENCY

-40

-50

-60

-70

-80

-90

-100

PHASE NOISE (dBc/Hz)

-110

-120

-130

-140

fRF = 434MHz

OFFSET FREQUENCY (Hz)

1M100k10k1k100 10M

MAX7030 toc31

REFERENCE SPUR MAGNITUDE

vs. SUPPLY VOLTAGE

-40

-45

-50

-55

-60

-65

REFERENCE SPUR MAGNITUDE (dBc)

-70

2.1 3.6

434MHz

315MHz

SUPPLY VOLTAGE (V)

MAX7030 toc32

3.33.02.72.4

FREQUENCY STABILITY

vs. SUPPLY VOLTAGE

-2

-4

FREQUENCY STABILITY (ppm)

-6

-8

-10

SUPPLY VOLTAGE (V)

MAX7030 toc33

fRF = 434MHz

fRF = 315MHz

3.33.02.72.42.1 3.6

Page 11

MAX7030

Low-Cost, 315MHz, 345MHz, and 433.92MHz

ASK Transceiver with Fractional-N PLL

______________________________________________________________________________________ 11

Pin Description

PIN NAME FUNCTION

1 PAVDD

2 ROUT

3 TX/RX1

4 TX/RX2 Transmit/Receive Switch Pole. Typically connected to ground. See the Typical Application Circuit.

5 PAOUT

6 AVDD

7 LNAIN Low-Noise Amplifier Input. Must be AC-coupled.

8 LNASRC

9 LNAOUT

10 MIXIN+ Noninverting Mixer Input. Must be AC-coupled to the LNA output.

11 MIXIN- Inverting Mixer Input. Bypass to AVDD with a capacitor as close as possible to the LNA LC tank filter.

12 MIXOUT 330Ω Mixer Output. Connect to the input of the 10.7MHz filter.

13 IFIN- Inverting 330Ω IF Limiter-Amplifier Input. Bypass to GND with a capacitor.

14 IFIN+ Noninverting 330Ω IF Limiter-Amplifier Input. Connect to the output of the 10.7MHz IF filter. 15 PDMIN Minimum-Level Peak Detector for Demodulator Output 16 PDMAX Maximum-Level Peak Detector for Demodulator Output 17 DS- Inverting Data Slicer Input 18 DS+ Noninverting Data Slicer Input 19 OP+ Noninverting Op-Amp Input for the Sallen-Key Data Filter 20 DF Data-Filter Feedback Node. Input for the feedback capacitor of the Sallen-Key data filter.

21, 25 N.C. No Connection. Do not connect to this pin.

22 T/R

23 ENABLE

24 DATA Receiver Data Output/Transmitter Data Input

26 DVDD

27 HVIN

Power-Amplifier Supply Voltage. Bypass to GND with 0.01µF and 220pF capacitors placed as close as possible to the pin.

Envelope-Shaping Output. ROUT controls the power-amplifier envelope’s rise and fall times. Connect ROUT to the PA pullup inductor or optional power-adjust resistor. Bypass the inductor to GND as close as possible to the inductor with 680pF and 220pF capacitors, as shown in the Typical Application Circuit.

Transmit/Receive Switch Throw. Drive T/R high to short TX/RX1 to TX/RX2. Drive T/R low to disconnect TX/RX1 from TX/RX2. Functionally identical to TX/RX2.

Power-Amplifier Output. Requires a pullup inductor to the supply voltage (or ROUT if envelope shaping is desired), which can be part of the output-matching network to an antenna.

Analog Power-Supply Voltage. AVDD is connected to an on-chip +3.0V regulator in 5V operation. Bypass AVDD to GND with a 0.1µF and 220pF capacitor placed as close as possible to the pin.

Low-Noise Amplifier Source for External Inductive Degeneration. Connect an inductor to GND to set the LNA input impedance.

Low-Noise Amplifier Output. Must be connected to AVDD through a parallel LC tank filter. AC-couple to MIXIN+.

Transmit/Receive. Drive high to put the device in transmit mode. Drive low or leave unconnected to put the device in receive mode. It is internally pulled down.

Enable. Drive high for normal operation. Drive low or leave unconnected to put the device into shutdown mode.

Digital Power-Supply Voltage. Bypass to GND with a 0.01µF and 220pF capacitor placed as close as possible to the pin.

High-Voltage Supply Input. For 3V operation, connect HVIN to AVDD, DVDD, and PAVDD. For 5V operation, connect only HVIN to 5V. Bypass HVIN to GND with a 0.01µF and 220pF capacitor placed as close as possible to the pin.

Page 12

MAX7030

Low-Cost, 315MHz, 345MHz, and 433.92MHz ASK Transceiver with Fractional-N PLL

12 ______________________________________________________________________________________

Detailed Description

The MAX7030 315MHz, 345MHz, and 433.92MHz CMOS transceiver and a few external components provide a complete transmit and receive chain from the antenna to the digital data interface. This device is designed for transmitting and receiving ASK data. All transmit frequencies are generated by a fractional-Nbased synthesizer, allowing for very fine frequency steps in increments of f

XTAL

/4096. The receive LO is generated by a traditional integer-N-based synthesizer. Depending on component selection, data rates as high as 33kbps (Manchester encoded) or 66kbps (NRZ encoded) can be achieved.

Receiver

Low-Noise Amplifier (LNA)

The LNA is a cascode amplifier with off-chip inductive degeneration that achieves approximately 30dB of voltage gain that is dependent on both the antenna-matching network at the LNA input and the LC tank network between the LNA output and the mixer inputs.

The off-chip inductive degeneration is achieved by connecting an inductor from LNASRC to GND. This inductor sets the real part of the input impedance at LNAIN, allowing for a more flexible match for low-input impedances such as a PCB trace antenna. A nominal value for this inductor with a 50Ω input impedance is 12nH at 315MHz and 10nH at 434MHz, but the inductance is affected by PCB trace length. LNASRC can be shorted to ground to increase sensitivity by approximately 1dB, but the input match must then be reoptimized.

The LC tank filter connected to LNAOUT consists of L5 and C9 (see the

Typical Application Circuit

). Select L5 and C9 to resonate at the desired RF input frequency. The resonant frequency is given by:

where L

TOTAL

= L5 + L

PARASITICS

and C

TOTAL

= C9 +

PARASITICS

and C

PARASITICS

include inductance and capacitance of the PCB traces, package pins, mixerinput impedance, LNA-output impedance, etc. These parasitics at high frequencies cannot be ignored, and can have a dramatic effect on the tank filter center frequency. Lab experimentation should be done to optimize the center frequency of the tank. The total parasitic capacitance is generally between 5pF and 7pF.

Automatic Gain Control (AGC)

When the AGC is enabled, it monitors the RSSI output. When the RSSI output reaches 1.28V, which corresponds to an RF input level of approximately -55dBm, the AGC switches on the LNA gain-reduction attenuator. The attenuator reduces the LNA gain by 36dB, thereby reducing the RSSI output by about 540mV to 740mV. The LNA resumes high-gain mode when the RSSI output level drops back below 680mV (approximately -59dBm at the RF input) for a programmable interval called the AGC dwell time (see Table 1). The AGC has a hysteresis of approximately 4dB. With the AGC function, the RSSI dynamic range is increased, allowing the MAX7030 to reliably produce an ASK output for RF input levels up to 0dBm with a modulation depth of 18dB. AGC is not required and can be disabled (see Table 1).

Pin Description (continued)

PIN NAME FUNCTION

28 AGC2 AGC Enable/Dwell Time Control 2 (MSB). See Table 1. Bypass to GND with a 10pF capacitor.

29 AGC1 AGC Enable/Dwell Time Control 1. See Table 1. Bypass to GND with a 10pF capacitor.

30 AGC0 AGC Enable/Dwell Time Control 0 (LSB). See Table 1. Bypass to GND with a 10pF capacitor.

31 XTAL1 Crystal Input 1. Bypass to GND if XTAL2 is driven by an AC-coupled external reference.

32 XTAL2 Crystal Input 2. XTAL2 can be driven from an external AC-coupled reference.

— EP Exposed Pad. Solder evenly to the board’s ground plane for proper operation.

2π

TOTAL TOTAL

Page 13

MAX7030

Low-Cost, 315MHz, 345MHz, and 433.92MHz

ASK Transceiver with Fractional-N PLL

______________________________________________________________________________________ 13

AGC Dwell-Time Settings

The AGC dwell timer holds the AGC in low-gain state for a set amount of time after the power level drops below the AGC switching threshold. After that set amount of time, if the power level is still below the AGC threshold, the LNA goes into high-gain state. This is important for ASK since the modulated data may have a high level above the threshold and low level below the threshold, which without the dwell timer would cause the AGC to switch on every bit.

The MAX7030 uses the three AGC control pins (AGC0, AGC1, AGC2) to set seven user-controlled, dwell-timer settings. The AGC dwell time is dependent on the crystal frequency and the bit settings of the AGC control pins. To calculate the dwell time, use the following equation:

where K is an odd integer in decimal from 11 to 23, determined by the control pin settings shown in Table 1.

To calculate the value of K, use the following equation and use the next integer higher than the calculated result:

K ≥ 3.3 x log10(Dwell Time x f

XTAL

)

For Manchester Code (50% duty cycle), set the dwell time to at least twice the bit period. For nonreturn-tozero (NRZ) data, set the dwell to greater than the period of the longest string of zeros or ones. For example, using Manchester Code at 315MHz (f

XTAL

12.679MHz) with a data rate of 2kbps (bit period = 250µs), the dwell time needs to be greater than 500µs:

K ≥ 3.3 x log10(500µs x 12.679) ≈ 12.546

Choose the AGC pin settings for K to be the next oddinteger value higher than 12.546, which is 13. This says that AGC1 is set high and AGC0 and AGC2 are set low.

Mixer

A unique feature of the MAX7030 is the integrated image rejection of the mixer. This eliminates the need for a costly front-end SAW filter for many applications. The advantage of not using a SAW filter is increased sensitivity, simplified antenna matching, less board space, and lower cost.

The mixer cell is a pair of double-balanced mixers that perform an IQ downconversion of the RF input to the

10.7MHz intermediate frequency (IF) with low-side injection (i.e., fLO= fRF- fIF). The image-rejection circuit then combines these signals to achieve a typical 46dB of image rejection over the full temperature range. Lowside injection is required as high-side injection is not possible due to the on-chip image rejection. The IF output is driven by a source follower, biased to create a driving impedance of 330Ω to interface with an off-chip 330Ω ceramic IF filter. The voltage-conversion gain driving a 330Ω load is approximately 20dB. Note that the MIXIN+ and MIXIN- inputs are functionally identical.

Integer-N Phase-Locked Loop (PLL)

The MAX7030 utilizes a fixed-integer-N PLL to generate the receive LO. All PLL components, including the loop filter, voltage-controlled oscillator, charge pump, asynchronous 24x divider, and phase-frequency detector are integrated internally. The loop bandwidth is approximately 500kHz. The relationship between RF, IF, and reference frequencies is given by:

REF

= (f

- fIF)/24

Table 1. AGC Dwell Time Settings for MAX7030

AGC2 AGC1 AGC0 DESCRIPTION

0 0 0 AGC disabled, high gain selected

001 K = 11

010 K = 13

011 K = 15

100 K = 17

101 K = 19

110 K = 21

111 K = 23

Dwell Time

XTAL

Page 14

MAX7030

Low-Cost, 315MHz, 345MHz, and 433.92MHz ASK Transceiver with Fractional-N PLL

14 ______________________________________________________________________________________

Intermediate Frequency (IF)

The IF section presents a differential 330Ω load to provide matching for the off-chip ceramic filter. The internal six AC-coupled limiting amplifiers produce an overall gain of approximately 65dB, with a bandpass filter type response centered near the 10.7MHz IF frequency with a 3dB bandwidth of approximately 10MHz. For ASK data, the RSSI circuit demodulates the IF to baseband by producing a DC output proportional to the log of the IF signal level with a slope of approximately 15mV/dB.

Data Filter

The data filter for the demodulated data is implemented as a 2nd-order, lowpass, Sallen-Key filter. The pole locations are set by the combination of two on-chip resistors and two external capacitors. Adjusting the value of the external capacitors changes the corner frequency to optimize for different data rates. Set the corner frequency in kHz to approximately 3 times the fastest expected Manchester data rate in kbps from the transmitter (1.5 times the fastest expected NRZ data rate). Keeping the corner frequency near the data rate rejects any noise at higher frequencies, resulting in an increase in receiver sensitivity.

The configuration shown in Figure 1 can create a Butterworth or Bessel response. The Butterworth filter offers a very-flat-amplitude response in the passband and a rolloff rate of 40dB/decade for the two-pole filter. The Bessel filter has a linear phase response, which works well for filtering digital data. To calculate the value of the capacitors, use the following equations, along with the coefficients in Table 2:

where fCis the desired 3dB corner frequency.

For example, choose a Butterworth filter response with a corner frequency of 5kHz:

Choosing standard capacitor values changes CF1to 470pF and CF2to 220pF. In the

Typical Application Circuit

CF1and CF2are named C16 and C17, respectively.

Data Slicer

The data slicer takes the analog output of the data filter and converts it to a digital signal. This is achieved by using a comparator and comparing the analog input to a threshold voltage. The threshold voltage is set by the voltage on the DS- pin, which is connected to the negative input of the data slicer comparator.

Numerous configurations can be used to generate the data-slicer threshold. For example, the circuit in Figure 2 shows a simple method using only one resistor and one capacitor. This configuration averages the analog output of the filter and sets the threshold to approximately 50% of that amplitude. With this configuration, the threshold automatically adjusts as the analog signal varies, minimizing the possibility for errors in the digital data. The values of R and C affect how fast the threshold tracks the analog amplitude. Be sure to keep the corner frequency of the RC circuit much lower (about 10 times) than the lowest expected data rate.

With this configuration, a long string of NRZ zeros or ones can cause the threshold to drift. This configuration works best if a coding scheme, such as Manchester coding, which has an equal number of zeros and ones, is used.

Figure 3 shows a configuration that uses the positive and negative peak detectors to generate the threshold. This configuration sets the threshold to the midpoint between a high output and a low output of the data filter.

Figure 1. Sallen-Key Lowpass Data Filter

Table 2. Coefficients to Calculate CF1and C

100

Ω

()()()

ak f

4 100

Ω

()()()

1 000

=≈

FF1

1 414 100 3 14 5

( . )( )( . )( )

=≈

4 100 3 14 5

( )( )( . )( )

k kHz

Ω

1 414

k kHz

Ω

225

450

MAX7030

100kΩ

RSSI

DFOP+DS+

100kΩ

FILTER TYPE a b

Butterworth (Q = 0.707)

Bessel

(Q = 0.577)

1.414 1.000

1.3617 0.618

Page 15

MAX7030

Low-Cost, 315MHz, 345MHz, and 433.92MHz

ASK Transceiver with Fractional-N PLL

______________________________________________________________________________________ 15

Peak Detectors

The maximum peak detector (PDMAX) and minimum peak detector (PDMIN), with resistors and capacitors shown in Figure 3, create DC output voltages equal to the high- and low-peak values of the filtered demodulated signal. The resistors provide a path for the capacitors to discharge, allowing the peak detectors to dynamically follow peak changes of the data filter output voltages.

The maximum and minimum peak detectors can be used together to form a data slicer threshold voltage at a value midway between the maximum and minimum voltage levels of the data stream (see the

Data Slicer

section and Figure 3). Set the RC time constant of the peak detector combining network to at least 5 times the data period.

If there is an event that causes a significant change in the magnitude of the baseband signal, such as an AGC gain-switch or a power-up transient, the peak detectors may “catch” a false level. If a false peak is detected, the slicing level is incorrect. The MAX7030 peak detectors correct these problems by temporarily tracking the incoming baseband filter voltage when an AGC state switch occurs, or forcing the peak detectors to track the baseband filter output voltage until all internal circuits are stable following an enable pin low-to-high transition and also T/R pin high-to-low transition. The peak detectors exhibit a fast attack/slow decay response. This feature allows for an extremely fast startup or AGC recovery.

Transmitter

Power Amplifier (PA)

The PA of the MAX7030 is a high-efficiency, opendrain, switch-mode amplifier. The PA with proper output-matching network can drive a wide range of antenna impedances, which includes a small-loop PCB

trace and a 50Ω antenna. The output-matching network for a 50Ω antenna is shown in the

Typical Application

Circuit

. The output-matching network suppresses the carrier harmonics and transforms the antenna impedance to an optimal impedance at PAOUT (pin 5). The optimal impedance at PAOUT is 250Ω.

When the output-matching network is properly tuned, the PA transmits power with a high overall efficiency of up to 32%. The efficiency of the PA itself is more than 46%. The output power is set by an external resistor at PAOUT and is also dependent on the external antenna and antenna-matching network at the PA output.

Envelope Shaping

The MAX7030 features an internal envelope-shaping resistor, which connects between the open-drain output of the PA and the power supply (see the

Typical

Application Circuit

). The envelope-shaping resistor slows the turn-on/turn-off of the PA in ASK mode and results in a smaller spectral width of the modulated PA output signal.

Fractional-N Phase-Locked Loop (PLL)

The MAX7030 utilizes a fully integrated, fractional-N, PLL for its transmit frequency synthesizer. All PLL components, including the loop filter, are integrated internally. The loop bandwidth is approximately 200kHz.

Power-Supply Connections

The MAX7030 can be powered from a 2.1V to 3.6V supply or a 4.5V to 5.5V supply. If a 4.5V to 5.5V supply is used, then the on-chip linear regulator reduces the 5V supply to the 3V needed to operate the chip.

To operate the MAX7030 from a 3V supply, connect PAVDD, AVDD, DVDD, and HVIN to the 3V supply. When using a 5V supply, connect the supply to HVIN

Figure 3. Generating Data-Slicer Threshold Using the Peak Detectors

Figure 2. Generating Data-Slicer Threshold Using a Lowpass Filter

MAX7030

DATA

SLICER

DATA

DS- DS+

MAX7030

PEAK

DATA

SLICER

DATA

DET

PDMAX PDMIN

PEAK

DET

Page 16

only and connect AVDD, PAVDD, and DVDD together. In both cases, bypass DVDD, HVIN, and PAVDD to GND with 0.01µF and 220pF capacitors and bypass AVDD to GND with 0.1µF and 220pF capacitors. Bypass T/R, ENABLE, DATA, and AGC0-2 with 10pF capacitors to GND. Place all bypass capacitors as close as possible to the respective pins.

Transmit/

Receive

Antenna Switch

The MAX7030 features an internal SPST RF switch that, when combined with a few external components, allows the transmit and receive pins to share a common antenna (see the

Typical Application Circuit)

. In receive mode, the switch is open and the power amplifier is shut down, presenting a high impedance to minimize the loading of the LNA. In transmit mode, the switch closes to complete a resonant tank circuit at the PA output and forms an RF short at the input to the LNA. In this mode, the external passive components couple the output of the PA to the antenna and protect the LNA input from strong transmitted signals.

The switch state is controlled by the T/R pin (pin 22). Drive T/R high to put the device in transmit mode; drive T/R low to put the device in receive mode.

Crystal Oscillator (XTAL)

The XTAL oscillator in the MAX7030 is designed to present a capacitance of approximately 3pF between the XTAL1 and XTAL2 pins. In most cases, this corresponds to a 4.5pF load capacitance applied to the external crystal when typical PCB parasitics are added.

It is very important to use a crystal with a load capacitance that is equal to the capacitance of the MAX7030 crystal oscillator plus PCB parasitics. If a

crystal designed to oscillate with a different load capacitance is used, the crystal is pulled away from its stated operating frequency, introducing an error in the reference frequency. Crystals designed to operate with higher differential load capacitance always pull the reference frequency higher.

In actuality, the oscillator pulls every crystal. The crystal’s natural frequency is really below its specified frequency, but when loaded with the specified load capacitance, the crystal is pulled and oscillates at its specified frequency. This pulling is already accounted for in the specification of the load capacitance.

Additional pulling can be calculated if the electrical parameters of the crystal are known. The frequency pulling is given by:

where:

fpis the amount the crystal frequency is pulled in ppm.

Cmis the motional capacitance of the crystal.

CASE

is the case capacitance.

SPEC

is the specified load capacitance.

LOAD

is the actual load capacitance.

When the crystal is loaded as specified, i.e., C

LOAD

= C

SPEC

, the frequency pulling equals zero.

MAX7030

Low-Cost, 315MHz, 345MHz, and 433.92MHz ASK Transceiver with Fractional-N PLL

16 ______________________________________________________________________________________

Pin Configuration

⎛

⎜

CC CC

⎝

CASE LOAD CASE SPEC

− +

⎞

⎟ ⎠

TOP VIEW

DATA

ENABLE

T/R

N.C.

DVDD

HVIN

AGC2

AGC1

AGC0

XTAL1

XTAL2

N.C.DFOP+

MAX7030

DS+17DS-

18192021222324

7654321

PDMAX

PDMIN

IFIN+

IFIN-

MIXOUT

MIXIN-

MIXIN+

LNAOUT

ROUT

PAVDD

TX/RX1

THIN QFN

TX/RX2

PAOUT

AVDD

LNAIN

LNASRC

Page 17

MAX7030

Table 3. Component Values for Typical Application Circuit

Low-Cost, 315MHz, 345MHz, and 433.92MHz

ASK Transceiver with Fractional-N PLL

______________________________________________________________________________________ 17

Note: Component values vary depending on PCB layout.

COMPONENT

C1 220pF 220pF 10%

C2 680pF 680pF 10%

C3 6.8pF 12pF 5%

C4 6.8pF 10pF 5%

C5 10pF 22pF 5%

C6 220pF 220pF 10%

C7 0.1µF 0.1µF 10%

C8 100pF 100pF 5%

C9 1.8pF 2.7pF ±0.1pF

C10 100pF 100pF 5%

C11 220pF 220pF 10%

C12 100pF 100pF 5%

C13 1500pF 1500pF 10%

C14 0.047µF 0.047µF 10%

C15 0.047µF 0.047µF 10%

C16 470pF 470pF 10%

C17 220pF 220pF 10%

C18 220pF 220pF 10%

C19 0.01µF 0.01µF 10%

C20 100pF 100pF 5%

C21 100pF 100pF 5%

C22 220pF 220pF 10%

C23 0.01µF 0.01µF 10%

C24 0.01µF 0.01µF 10%

L1 22nH 27nH Coilcraft 0603CS

L2 22nH 30nH Coilcraft 0603CS

L3 22nH 30nH Coilcraft 0603CS

L4 10nH 12nH Coilcraft 0603CS

L5 16nH 30nH Murata LQW18A

L6 68nH 100nH Coilcraft 0603CS

R1 100kΩ 100kΩ 5%

R2 100kΩ 100kΩ 5%

R3 0Ω 0Ω —

Y1 17.63416MHz 12.67917MHz Crystal, 4.5pF load capacitance

Y2 10.7MHz ceramic filter 10.7MHz ceramic filter Murata SFECV10.7 series

VALUE FOR

433.92MHz RF

VALUE FOR

315MHz RF

DESCRIPTION

Page 18

MAX7030

Low-Cost, 315MHz, 345MHz, and 433.92MHz ASK Transceiver with Fractional-N PLL

18 ______________________________________________________________________________________

Typical Application Circuit

Chip Information

PROCESS: CMOS

PACKAGE

TYPE

PACKAGE

CODE

OUTLINE NO.

LAND

PATTERN NO.

32 Thin QFN-EP T3255+3

21-0140

90-0001

Package Information

For the latest package outline information and land patterns, go to www.maxim-ic.com/packages

. Note that a “+”, “#”, or “-” in the package code indicates RoHS status only. Package drawings may show a different suffix character, but the drawing pertains to the package regardless of RoHS status.

C21

XTAL2

LNAOUT

910

XTAL1

MIXIN+

C10

C20

C11

N.C.

DATA

ENABLE

N.C.

OP+

DS+

DS-

PDMAX

C15

T/R

C19

C18

25262728293032 31

HVIN

AGC0

AGC1

AGC2

DVDD

MAX7030

EXPOSED

PAD

MIXIN-

C12

MIXOUT

C13

IN OUTGND

IFIN-

IFIN+

PDMIN

C14

C1C2

*OPTIONAL POWER-ADJUST RESISTOR

R3*

3.0V

C23

C24

C22

PAVDD

ROUT

TX/RX1

TX/RX2

PAOUT

AVDD

LNAIN

LNASRC

C17

AGC0

AGC1

AGC2

DATA

ENABLE

TRANSMIT/ RECEIVE

C16

Page 19

MAX7030

Low-Cost, 315MHz, 345MHz, and 433.92MHz

ASK Transceiver with Fractional-N PLL

______________________________________________________________________________________ 19

Functional Diagram

LNAIN

LNASRC

XTAL1

XTAL2

MIXIN-MIXIN+LNAOUT

9 10 11 12

LNA

0°

FREQUENCY

DIVIDER

CRYSTAL

OSCILLATOR

PHASE

DETECTOR

90°

RX VCO

FREQUENCY

DIVIDER

IFIN+ IFIN-MIXOUT

IF LIMITING

AMPS

RSSI

100kΩ

DATA FILTER

100kΩ

OP+

DS+

PDMIN

HVIN

AVDD

CHARGE

PUMP

TX VCO

3.0V

REGULATOR

EXPOSED

PAD

ROUT PAVDD PAOUT T/R DVDD ENABLE

LOOP FILTER

MAX7030

∆Σ

MODULATOR

TX/RX1 TX/RX2

DIGITAL LOGIC

DATA

PDMAX

DS-

AGC0

AGC1

AGC2

DATA

Page 20

MAX7030

Low-Cost, 315MHz, 345MHz, and 433.92MHz ASK Transceiver with Fractional-N PLL

Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.

____________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600

Revision History

REVISION

NUMBER

0 5/05 Initial release —

1 9/08

2 6/09 Made correction in Power Amplifier (PA) section 15

3 11/10

REVISION

DATE

DESCRIPTION

Added + to each part to denote lead-free/RoHS-compliant package and explicitly calling out the odd frequency as contact factory for availability

Updated AC Electrical Characteristics, Absolute Maximum Ratings, and Package

Information

PAGES

CHANGED

2, 5, 18