Page 1
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General Description
The MAX5186 contains two 8-bit, simultaneous-update,
current-output digital-to-analog converters (DACs)
designed for superior performance in communications
systems requiring analog signal reconstruction with low
distortion and low-power operation. The MAX5189 provides equal specifications, with on-chip precision resistors for voltage output operation. The MAX5186/
MAX5189 are designed for a 10pVs glitch operation to
minimize unwanted spurious signal components at the
output. An on-board +1.2V bandgap circuit provides a
well-regulated, low-noise reference that can be disabled for external reference operation.
The MAX5186/MAX5189 are designed to provide a high
level of signal integrity for the least amount of power dissipation. Both DACs operate from a single supply voltage
of +2.7V to +3.3V. Additionally, these DACs have three
modes of operation: normal, low-power standby, and
complete shutdown, which provides the lowest possible
power dissipation with a 1µA (max) shutdown current. A
fast wake-up time (0.5µs) from standby mode to full DAC
operation allows power conservation by activating the
DACs only when required.
The MAX5186/MAX5189 are packaged in a 28-pin
QSOP and are specified for the extended (-40°C to
+85°C) temperature range. For higher resolution, dual
10-bit versions, refer to the MAX5180/MAX5183 data
sheet.
Applications
Signal Reconstruction of I and Q
Transmit Signals
Digital Signal Processing
Arbitrary Waveform Generation (AWG)
Imaging Applications
Features
♦ +2.7V to +3.3V Single-Supply Operation
♦ Wide Spurious-Free Dynamic Range: 70dB
at f
OUT
= 2.2MHz
♦ Fully Differential Outputs for Each DAC
♦ ±0.5% FSR Gain Mismatch
♦ ±0.15° Phase Mismatch
♦ Low-Current Standby or Full Shutdown Modes
♦ Internal +1.2V, Low-Noise Bandgap Reference
♦ Small 28-Pin QSOP Package
MAX5186/MAX5189
Dual, 8-Bit, 40MHz, Current/Voltage,
Simultaneous-Output DACs
________________________________________________________________ Maxim Integrated Products 1
19-1581; Rev 0; 12/99
Pin Configuration
Ordering Information
PART
MAX5186BEEI
MAX5189BEEI
TEMP. RANGE
-40°C to +85°C
-40°C to +85°C
PIN-PACKAGE
28 QSOP
28 QSOP
TOP VIEW
CREF1
OUT1P
OUT1N
AGND
AV
DACEN
CLK
N.C.
REN
DGND
DGND
1
2
3
4
5
DD
PD
CS
D0
MAX5186
6
MAX5189
7
8
9
10
11
12
13
14
QSOP
28
CREF2
27
OUT2P
26
OUT2N
25
REFO
24
REFR
23
DGND
22
DV
DD
21
D7
20
D6
19
D5
18
D4
17
D3
16
D2
15
D1
Page 2
MAX5186/MAX5189
Dual, 8-Bit, 40MHz, Current/Voltage,
Simultaneous-Output DACs
2 _______________________________________________________________________________________
ABSOLUTE MAXIMUM RATINGS
ELECTRICAL CHARACTERISTICS
(AVDD= DVDD= +3V ±10%, AGND = DGND = 0, f
CLK
= 40MHz, IFS= 1mA, 400Ω differential output, CL= 5pF, TA= T
MIN
to T
MAX
,
unless otherwise noted. Typical values are at T
A
= +25°C.)
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
AVDD, DVDDto AGND, DGND ................................ -0.3V to +6V
Digital Input to DGND.............................................. -0.3V to +6V
OUT1P, OUT1N, OUT2P, OUT2N, CREF1,
CREF2 to AGND .................................................. -0.3V to +6V
V
REF
to AGND ......................................................... -0.3V to +6V
AGND to DGND................................................... -0.3V to +0.3V
AV
DD
to DVDD.................................................................... ±3.3V
Maximum Current into Any Pin........................................... 50mA
Continuous Power Dissipation (T
A
= +70°C)
28-Pin QSOP (derate 9.00mW/°C above +70°C) ....... 725mW
Operating Temperature Ranges
MAX518_BEEI................................................. -40°C to +85°C
Storage Temperature Range .............................-65°C to +150°C
Lead Temperature (soldering, 10sec) .............................+300°C
Full-Scale Error
-4 +4MAX5189
57 70
PARAMETER SYMBOL MIN TYP MAX UNITS
-20 ±4 +20 LSB
Zero-Scale Error
-1 +1
LSB
Differential Nonlinearity DNL -1 ±0.25 +1 LSB
Output Settling Time 25 ns
Glitch Impulse 10 pVs
Spurious-Free Dynamic Range
to Nyquist
SFDR
72
dBc
Signal-to-Noise-Ratio to Nyquist
THD
-70
dB
8 Bits
Integral Nonlinearity INL -1 ±0.25 +1 LSB
-68 -63
SNR
52
dB
46 52
DAC-to-DAC Output Isolation -60 dB
Clock and Data Feedthrough 50 nVs
Output Noise 10
pA/√Hz
Gain Mismatch Between DAC
Outputs
±0.5 ±1 LSB
Phase Mismatch Between DAC
Outputs
±0.15 degrees
CONDITIONS
f
OUT
= 2.2MHz, f
CLK
= 40MHz
f
OUT
= 550kHz, f
CLK
= 40MHz
(Note 1)
MAX5186
Guaranteed monotonic
To ±0.5LSB error band
f
OUT
= 2.2MHz, f
CLK
= 40MHz
f
OUT
= 2.2MHz
f
OUT
= 550kHz, f
CLK
= 40MHz
f
OUT
= 550kHz, f
CLK
= 40MHz
All 0s to all 1s
f
OUT
= 2.2MHz
f
OUT
= 2.2MHz
Resolution N
Total Harmonic Distortion
to Nyquist
f
OUT
= 2.2MHz, f
CLK
= 40MHz
DYNAMIC PERFORMANCE
STATIC PERFORMANCE
Page 3
MAX5186/MAX5189
Dual, 8-Bit, 40MHz, Current/Voltage,
Simultaneous-Output DACs
_______________________________________________________________________________________ 3
ELECTRICAL CHARACTERISTICS (continued)
(AVDD= DVDD= +3V ±10%, AGND = DGND = 0, f
CLK
= 40MHz, IFS= 1mA, 400Ω differential output, CL= 5pF, TA= T
MIN
to T
MAX
,
unless otherwise noted. Typical values are at T
A
= +25°C.)
VIN= 0 or DV
DD
PD = 1, DACEN = X, digital inputs at 0 or DV
DD
(X = don’t care)
PD = 0, DACEN = 0, digital inputs at 0 or DV
DD
PD = 0, DACEN = 1, digital inputs at 0 or DV
DD
PD = 0, DACEN = 1, digital inputs at 0 or DV
DD
DACEN = 0, MAX5186 only
MAX5186 only
MAX5186 only
CONDITIONS
pF10C
IN
Digital Input Capacitance
µA±1I
IN
Digital Input Current
V0.8V
IL
Digital Input Voltage Low
V2V
IH
Digital Input Voltage High
µA0.5 1I
SHDN
Shutdown Current
mA1.0 1.5I
STANDBY
Standby Current
mA4.2 5.0IDV
DD
Digital Supply Current
V2.7 3.3DV
DD
Digital Power-Supply Voltage
mA2.7 5.0IAV
DD
Analog Supply Current
V2.7 3.3AV
DD
Analog Power-Supply Voltage
mA/mA8Current Gain (IFS/ I
REF
)
V-0.3 0.8Voltage Compliance of Output
mV400V
FS
Full-Scale Output Voltage
mV/V0.5Reference Supply Rejection
µA10I
REFOUT
Reference Output Drive
Capability
ppm/°C50TCV
REF
Output Voltage Temperature
Drift
V1.12 1.2 1.28V
REF
Output Voltage Range
µA-1 1Output Leakage Current
mA0.5 1 1.5I
FS
Full-Scale Output Current
Ω400R
L
DAC External Output Resistor
Load
UNITSMIN TYP MAXSYMBOLPARAMETER
ns10t
DS1
DAC1 DATA to CLK Rise Setup
Time
ns10t
DS2
DAC2 DATA to CLK Fall Setup
Time
ns0t
DH1
DAC1 CLK Rise to DATA Hold
Time
ns0t
DH2
DAC2 CLK Fall to DATA Hold
Time
ANALOG OUTPUT
TIMING CHARACTERISTICS
LOGIC INPUTS AND OUTPUTS
POWER REQUIREMENTS
REFERENCE
Page 4
MAX5186/MAX5189
Dual, 8-Bit, 40MHz, Current/Voltage,
Simultaneous-Output DACs
4 _______________________________________________________________________________________
ELECTRICAL CHARACTERISTICS (continued)
(AVDD= DVDD= +3V ±10%, AGND = DGND = 0, f
CLK
= 40MHz, IFS= 1mA, 400Ω differential output, CL= 5pF, TA= T
MIN
to T
MAX
,
unless otherwise noted. Typical values are at T
A
= +25°C.)
Note 1: Excludes reference and reference resistor (MAX5189) tolerance.
ns10t
CL
Clock Low Time
ns10t
CH
Clock High Time
ns25t
CLK
Clock Period
µs50PD Fall Time to V
OUT
µs0.5DACEN Rise Time to V
OUT
ns5
CS Fall to CLK Fall Time
ns5
CS Fall to CLK Rise Time
PARAMETER SYMBOL MIN TYP MAX UNITSCONDITIONS
Page 5
MAX5186/MAX5189
Dual, 8-Bit, 40MHz, Current/Voltage,
Simultaneous-Output DACs
_______________________________________________________________________________________ 5
Typical Operating Characteristics
(AVDD= DVDD= +3V, AGND = DGND = 0, 400Ω differential output, IFS= 1mA, CL= 5pF, TA = +25°C, unless otherwise noted.)
0.150
0.125
0.100
0.075
0.050
0.025
0
-0.025
-0.050
0 32 64 96 128 160 192 224 256
INTEGRAL NONLINEARITY
vs. INPUT CODE
MAX5186/9toc01
INPUT CODE
INL (LSB)
0.100
0.075
0.050
0.025
0
-0.025
-0.050
-0.075
0 32 64 96 128 160 192 224 256
DIFFERENTIAL NONLINEARITY
vs. INPUT CODE
MAX5186/9toc02
INPUT CODE
DNL (LSB)
2.45
2.47
2.51
2.49
2.53
2.55
2.5 3.53.0 4.0 4.5 5.0 5.5
ANALOG SUPPLY CURRENT
vs. SUPPLY VOLTAGE
MAX5186/9toc03
SUPPLY VOLTAGE (V)
SUPPLY CURRENT (mA)
MAX5189
MAX5186
1.5
2.0
3.0
2.5
3.5
4.0
-40 -15 10 35 60 85
ANALOG SUPPLY CURRENT
vs. TEMPERATURE
MAX5186/9toc04
TEMPERATURE (°C)
ANALOG SUPPLY CURRENT (mA)
MAX5186
MAX5189
0
2
6
4
8
10
2.5 3.53.0 4.0 4.5 5.0 5.5
DIGITAL SUPPLY CURRENT
vs. SUPPLY VOLTAGE
MAX5186/9toc05
SUPPLY VOLTAGE (V)
DIGITAL SUPPLY CURRENT (mA)
MAX5189
MAX5186
0
1
3
2
4
5
-40 -15 10 35 60 85
DIGITAL SUPPLY CURRENT
vs. TEMPERATURE
MAX5186/9toc06
TEMPERATURE (°C)
DIGITAL SUPPLY CURRENT (mA)
MAX5186
MAX5189
560
570
590
580
600
610
2.5 3.53.0 4.0 4.5 5.0 5.5
STANDBY CURRENT vs. SUPPLY VOLTAGE
MAX5186/9toc07
SUPPLY VOLTAGE (V)
STANDBY CURRENT (µA)
MAX5189
MAX5186
540
560
550
580
570
590
600
-40 10-15 35 60 85
STANDBY CURRENT vs. TEMPERATURE
MAX5186/9toc08
TEMPERATURE (°C)
STANDBY CURRENT (µA)
MAX5189
MAX5186
0.45
0.55
0.50
0.60
0.65
0.70
0.75
0.80
2.5 3.53.0 4.5
4.0
5.0 5.5
SHUTDOWN CURRENT vs. SUPPLY VOLTAGE
MAX5186/9toc09
SUPPLY VOLTAGE (V)
SHUITDOWN CURRENT (µA)
MAX5186
MAX5189
Page 6
MAX5186/MAX5189
Dual, 8-Bit, 40MHz, Current/Voltage,
Simultaneous-Output DACs
6 _______________________________________________________________________________________
Typical Operating Characteristics (continued)
(AVDD= DVDD= +3V, AGND = DGND = 0, 400Ω differential output, IFS= 1mA, CL= 5pF, TA = +25°C, unless otherwise noted.)
40
70
60
50
80
90
100
10 302515 20 35 40 45 50 55 60
MAX5186/9toc19
CLOCK FREQUENCY (MHz)
SPURIOUS-FREE DYNAMIC RANGE (dBc)
SPURIOUS-FREE DYNAMIC RANGE
vs. CLOCK FREQUENCY
DAC2
DAC1
1.23
1.24
1.26
1.25
1.27
1.28
2.5 3.53.0 4.0 4.5 5.0 5.5
INTERNAL REFERENCE VOLTAGE
vs. SUPPLY VOLTAGE
MAX5186/9toc11
SUPPLY VOLTAGE (V)
REFERENCE VOLTAGE (V)
MAX5186
MAX5189
1.23
1.24
1.26
1.25
1.27
1.28
-40 -15 10 35 60 85
INTERNAL REFERENCE VOLTAGE
vs. TEMPERATURE
MAX5186/9toc12
TEMPERATURE (°C)
REFERENCE VOLTAGE (V)
MAX5186
MAX5189
0
1
2
3
4
0 200100 400
300
500
OUTPUT CURRENT
vs. REFERENCE CURRENT
MAX5186/9toc13
REFERENCE CURRENT (µA)
OUTPUT CURRENT (mA)
DYNAMIC RESPONSE RISE TIME
MAX5186toc14
50ns/div
OUT_P
150mV/
div
OUT_N
150mV/
div
DYNAMIC RESPONSE FALL TIME
MAX5186/9toc15
50ns/div
OUT_P
150mV/
div
OUT_N
150mV/
div
SETTLING TIME
MAX5186/9toc16
12.5ns/div
OUT_N
100mV/
div
OUT_P
100mV/
div
0
-10
-20
-30
-40
-50
-60
-70
-80
-90
-100
-110
-120
0246
81012141618
20
FFT PLOT, DAC1
MAX5186/9toc17
OUTPUT FREQUENCY (MHz)
dBc
f
OUT
= 2.2MHz
f
CLK
= 40MHz
0
-10
-20
-30
-40
-50
-60
-70
-80
-90
-100
-110
-120
0246
81012141618
20
FFT PLOT, DAC2
MAX5186/9toc18
OUTPUT FREQUENCY (MHz)
dBc
f
OUT
= 2.2MHz
f
CLK
= 40MHz
Page 7
MAX5186/MAX5189
Dual, 8-Bit, 40MHz, Current/Voltage,
Simultaneous-Output DACs
_______________________________________________________________________________________ 7
Typical Operating Characteristics (continued)
(AVDD= DVDD= +3V, AGND = DGND = 0, 400Ω differential output, IFS= 1mA, CL= 5pF, TA = +25°C, unless otherwise noted.)
66
70
68
76
74
72
78
500 1100 1300700 900 1500 1700 1900 2100 2300
MAX5186/9toc20
OUTPUT FREQUENCY (kHz)
SFDR (dBc)
SPURIOUS-FREE DYNAMIC RANGE vs. OUTPUT
FREQUENCY AND CLOCK FREQUENCY, DAC1
f
CLK
= 50MHz
f
CLK
= 60MHz
f
CLK
= 20MHz
f
CLK
= 40MHz
f
CLK
= 10MHz
f
CLK
= 30MHz
66
72
70
68
74
76
78
500 1100 1300700 900 1500 1700 1900 2100 2300
MAX5186/9toc21
OUTPUT FREQUENCY (kHz)
SFDR (dBc)
SPURIOUS-FREE DYNAMIC RANGE vs. OUTPUT
FREQUENCY AND CLOCK FREQUENCY, DAC2
f
CLK
= 30MHz
f
CLK
= 10MHz
f
CLK
= 50MHz
f
CLK
= 60MHz
f
CLK
= 40MHz
f
CLK
= 20MHz
62.5
62.0
61.0
60.5
61.5
60.0
0 1500500 1000 2000 2500
SIGNAL-TO-NOISE + DISTORTION
vs. OUTPUT FREQUENCY
MAX5186/9toc23
OUTPUT FREQUENCY (kHz)
SINAD (dB)
DAC2
DAC1
0107.52.5 5 12.5 15 17.5
MAX5186/9toc24
OUTPUT FREQUENCY (MHz)
SFDR (dBc)
MULTITONE
SPURIOUS-FREE DYNAMIC RANGE
vs. OUTPUT FREQUENCY
-120
-90
-110
-60
-70
-40
-50
-30
-10
-20
0
-80
-100
SPURIOUS-FREE DYNAMIC RANGE
vs. FULL-SCALE OUTPUT CURRENT
74
72
70
68
SFDR (dBc)
66
64
62
60
0.5 0.75 1.0 1.25 1.5
FULL-SCALE OUTPUT CURRENT (mA)
MAX5186/89-26
Page 8
MAX5186/MAX5189
Dual, 8-Bit, 40MHz, Current/Voltage,
Simultaneous-Output DACs
8 _______________________________________________________________________________________
Pin Description
Reference InputREFR24
Digital GroundDGND23
Digital Supply, +2.7V to +3.3VDV
DD
22
Data Bit D7 (MSB)D721
7 PD
Power-Down Select
0: Enter DAC standby mode (DACEN = DGND) or power-up DAC (DACEN = DV
DD
).
1: Enter shutdown mode.
3 OUT1N Negative Analog Output, DAC1. Current output for MAX5186; voltage output for MAX5189.
Data Bits D1–D6D1–D615–20
Data Bit D0 (LSB)D014
Digital GroundDGND13
Digital GroundDGND12
Active-Low Reference Enable. Connect to DGND to activate on-chip +1.2V reference.
REN
11
No Connect. Do not connect to this pin.N.C.10
Clock inputCLK9
Active-Low Chip Select
CS
8
NAME FUNCTION
1 CREF1 Reference Bias Bypass, DAC1
2 OUT1P Positive Analog Output, DAC1. Current output for MAX5186; voltage output for MAX5189.
PIN
6 DACEN
DAC Enable, Digital Input
0: Enter DAC standby mode with PD = DGND.
1: Power-up DAC with PD = DGND.
X: Enter shutdown mode with PD = DVDD(X = don’t care).
5 AV
DD
Analog Positive Supply, +2.7V to +3.3V
4 AGND Analog Ground
Reference Bias Bypass, DAC2CREF228
Positive Analog Output, DAC2. Current output for MAX5186; voltage output for MAX5189.OUT2P27
Negative Analog Output, DAC2. Current output for MAX5186; voltage output for MAX5189.OUT2N26
Reference OutputREFO25
Page 9
MAX5186/MAX5189
Dual, 8-Bit, 40MHz, Current/Voltage,
Simultaneous-Output DACs
_______________________________________________________________________________________ 9
Detailed Description
The MAX5186/MAX5189 are dual, 8-bit digital-to-analog converters (DACs) capable of operating with clock
speeds up to 40MHz. Each of these dual converters
consists of separate input and DAC registers, followed
by a current source array capable of generating up to
1.5mA full-scale output current (Figure 1). An integrated +1.2V voltage reference and control amplifier determine the data converters’ full-scale output currents/
voltages. Careful reference design ensures close gain
matching and excellent drift characteristics. The
MAX5189’s voltage output operation features matched
400Ω on-chip resistors that convert the current array
current into a voltage.
Internal Reference and
Control Amplifier
The MAX5186/MAX5189 provide an integrated
50ppm/°C, +1.2V, low-noise bandgap reference that
can be disabled and overridden by an external reference voltage. REFO serves either as an external reference input or an integrated reference output. If REN is
connected to DGND, the internal reference is selected
and REFO provides a +1.2V output. Due to its limited
10µA output drive capability, REFO must be buffered
with an external amplifier if heavier loading is required.
The MAX5186/MAX5189 also employ a control amplifier
designed to simultaneously regulate the full-scale output current (IFS) for both outputs of the devices. The
output current is calculated as follows:
IFS= 8 · I
REF
where I
REF
is the reference output current (I
REF
=
V
REFO/RSET
) and IFSis the full-scale output current.
R
SET
is the reference resistor that determines the
amplifier’s output current on the MAX5186 (Figure 2).
This current is mirrored into the current source array
where it is equally distributed between matched current
segments and summed to valid output current readings
for the DACs.
The MAX5189 converts each output current (DAC1 and
DAC2) into an output voltage (V
OUT1
, V
OUT2
) with two
internal, ground-referenced 400Ω load resistors. Using
the internal +1.2V reference voltage, the MAX5189’s
integrated reference output-current resistor (R
SET
=
9.6kΩ) sets I
REF
to 125µA and IFSto 1mA.
External Reference
To disable the MAX5186/MAX5189’s internal reference,
connect REN to DVDD. A temperature-stable, external
reference may now be applied to drive the REFO pin to
set the full-scale output (Figure 3). Choose a reference
capable of supplying at least 150µA to drive the bias
circuit that generates the cascode current for the current array. For improved accuracy and drift performance, choose a fixed output voltage reference such
as the +1.2V, 25ppm/°C MAX6520 bandgap reference.
Standby Mode
To enter the lower power standby mode, connect digital inputs PD and DACEN to DGND. In standby, both
the reference and the control amplifier are active with
the current array inactive. To exit this condition, DACEN
must be pulled high with PD held at DGND. Both the
MAX5186/MAX5189 typically require 50µs to wake up
and let both outputs and reference settle.
Shutdown Mode
For lowest power consumption, the MAX5186/MAX5189
provide a power-down mode in which the reference,
control amplifier, and current array are inactive and the
DACs’ supply current is reduced to 1µA. To enter this
mode, connect PD to DVDD. To return to active mode,
connect PD to DGND and DACEN to DVDD. About 50µs
are required for the parts to leave shutdown mode and
settle to their outputs’ values prior to shutdown. Table 1
lists the power-down mode selection.
Timing Information
Both DAC cells residing in the MAX5186/MAX5189
write to their outputs simultaneously (Figure 4). The
input latch of the first DAC (DAC1) is loaded after the
clock signal transitions high. When the clock signal
transitions low, the input latch of the second DAC
(DAC2) is loaded. The contents of both input latches
are simultaneously shifted to the DAC registers, and
their outputs update at the rising edge of the next
clock.
Outputs
The MAX5186 outputs are designed to supply full-scale
output currents of 1mA into 400Ω loads in parallel with
a capacitive load of 5pF. The MAX5189 features integrated 400Ω resistors that restore the array currents to
proportional, differential voltages of 400mV. These differential output voltages can then be used to drive a
balun transformer or a low-distortion, high-speed operational amplifier to convert the differential voltage into a
single-ended voltage.
Page 10
MAX5186/MAX5189
Dual, 8-Bit, 40MHz, Current/Voltage,
Simultaneous-Output DACs
10 ______________________________________________________________________________________
Applications Information
Static and Dynamic
Performance Definitions
Integral Nonlinearity
Integral nonlinearity (INL) (Figure 5a) is the deviation of
the values on an actual transfer function from either a
best-straight-line fit (closest approximation to the actual
transfer curve) or a line drawn between the endpoints
of the transfer function once offset and gain errors have
been nullified. For a DAC, the deviations are measured
every single step.
Differential Nonlinearity
Differential nonlinearity (DNL) (Figure 5b) is the difference between an actual step height and the ideal value
of 1LSB. A DNL error specification of less than 1LSB
guarantees no missing codes and a monotonic transfer
function.
Offset Error
Offset error (Figure 5c) is the difference between the
ideal and the actual offset point. For a DAC, the offset
point is the step value when the digital input is zero.
This error affects all codes by the same amount and
can usually be compensated by trimming.
Gain Error
Gain error (Figure 5d) is the difference between the
ideal and the actual full-scale output voltage on the
transfer curve after nullifying the offset error. This error
alters the slope of the transfer function and corresponds to the same percentage error in each step.
Settling Time
Settling time is the amount of time required from the start
of a transition until the DAC output settles its new output
value to within the converter’s specified accuracy.
Figure 1. Functional Diagram
REN
1.2V REF
REFO
REFR
9.6k*
CLK
*INTERNAL 400Ω AND 9.6kΩ
RESISTORS FOR MAX5189 ONLY.
AV
DAC1 SWITCHES
DAC2 SWITCHES
OUTPUT
LATCHES
MSB
DECODE
INPUT
LATCHES
AGND CS DACEN PD
DD
CURRENT-
SOURCE ARRAY
OUTPUT
LATCHES
MSB
DECODE
INPUT
LATCHES
D7–D0
400Ω*
MAX5186
MAX5189
DV
DD
400Ω*
DGND
CREF1
CREF2
OUT1P
OUT1N
OUT2N
OUT2N
400Ω* 400Ω*
Page 11
MAX5186/MAX5189
Dual, 8-Bit, 40MHz, Current/Voltage,
Simultaneous-Output DACs
______________________________________________________________________________________ 11
Figure 2. Setting IFSwith the Internal +1.2V Reference and the Control Amplifier
Figure 3. MAX5186/MAX5189 with External Reference
OPTIONAL EXTERNAL BUFFER
FOR HEAVIER LOADS
REN
DGND
MAX4040
AGND
V
REF
I
=
REF
R
SET
*COMPENSATION CAPACITOR (C
REFO
C
COMP*
R
SET
AGND
= 100nF) **9.6kΩ REFERENCE CURRENT-SET RESISTOR
COMP
REFR
I
REF
+1.2V
BANDGAP
REFERENCE
**
R
SET
9.6k
INTERNAL TO MAX5189 ONLY. USE EXTERNAL
R
DV
REN
MAX5186
MAX5189
FOR MAX5186.
SET
DD
DGND
I
CURRENT-
SOURCE ARRAY
0.1µF10µF
FS
AV
DD
EXTERNAL
+1.2V
REFERENCE
REFO
REFR
MAX6520
AGND
AGND
R
SET
+1.2V
BANDGAP
REFERENCE
*
9.6k
MAX5186
MAX5189
*9.6kΩ REFERENCE CURRENT-SET RESISTOR
INTERNAL TO MAX5189 ONLY. USE EXTERNAL
FOR MAX5186.
R
SET
CURRENT-
SOURCE ARRAY
I
FS
Page 12
MAX5186/MAX5189
Dual, 8-Bit, 40MHz, Current/Voltage,
Simultaneous-Output DACs
12 ______________________________________________________________________________________
Figure 4. Timing Diagram
X = Don’t care
Table 1. Power-Down Mode Selection
Digital Feedthrough
Digital feedthrough is the noise generated on a DAC’s
output when any digital input transitions. Proper board
layout and grounding will significantly reduce this
noise, but there will always be some feedthrough
caused by the DAC itself.
Total Harmonic Distortion
Total harmonic distortion (THD) is the ratio of the RMS
sum of the input signal’s first five harmonics to the fundamental itself. This is expressed as:
where V
1
is the fundamental amplitude, and V2through
V5are the amplitudes of the 2nd- through 5th-order
harmonics.
Spurious-Free Dynamic Range
Spurious-free dynamic range (SFDR) is the ratio of RMS
amplitude of the fundamental (maximum signal component) to the RMS value of the next-largest distortion
component.
Differential to Single-Ended Conversion
The MAX4108 low-distortion, high-input bandwidth
amplifier may be used to generate a voltage from the
array current output of the MAX5186. The differential
voltage across OUT1P (or OUT2P) and OUT1N (or
OUT2N) is converted into a single-ended voltage by
designing an appropriate operational amplifier configuration (Figure 6).
AGND
High-Z
AGND
High-Z
MAX5189
MAX5186
ShutdownX1
Last state prior to standby modeWake-Up10
MAX5189
MAX5186
Standby00
OUTPUT STATE
POWER-DOWN
MODE
DACEN (DAC
ENABLE)
PD
(POWER-DOWN SELECT)
CLK
t
CLK
D0–D7
OUT1 N - 1
OUT2 N - 1 N N + 1
DAC1 DAC1DAC2 DAC2 DAC1 DAC2
t
DS1
t
DS2
t
DH1
t
CL
t
DH1
N N + 1
t
CH
THD 20 log
=
2
(V V V V )
2
⋅
2
+++
3
V
1
2
4
2
5
Page 13
MAX5186/MAX5189
Dual, 8-Bit, 40MHz, Current/Voltage,
Simultaneous-Output DACs
______________________________________________________________________________________ 13
I/Q Reconstruction in a QAM Application
The MAX5186/MAX5189’s low distortion supports analog reconstruction of in-phase (I) and quadrature (Q)
carrier components typically used in quadrature amplitude modulation (QAM) architectures where I and Q
data are interleaved on a common data bus. A QAM
signal is both amplitude and phase modulated, created
by summing two independently modulated carriers of
identical frequency but different phase (90° phase difference).
In a typical QAM application (Figure 7), the modulation
occurs in the digital domain and the MAX5186/
MAX5189’s dual DACs may be used to reconstruct the
analog I and Q components.
The I/Q reconstruction system is completed by a quadrature modulator that combines the reconstructed I and
Q components with in-phase and quadrature carrier
frequencies and then sums both outputs to provide the
QAM signal.
Grounding and Power-Supply Decoupling
Grounding and power-supply decoupling strongly influence the MAX5186/MAX5189’s performance. Unwanted
digital crosstalk may couple through the input, refer-
Figure 5a. Integral Nonlinearity
Figure 5c. Offset Error
Figure 5d. Gain Error
Figure 5b. Differential Nonlinearity
7
6
5
4
3
ANALOG OUTPUT VALUE
2
1
0
000 010001 011 100 101 110
AT STEP
001 (1/4 LSB )
DIGITAL INPUT CODE
AT STEP
011 (1/2 LSB )
111
6
5
4
3
2
ANALOG OUTPUT VALUE
1
0
000 010001 011 100 101
1 LSB
DIFFERENTIAL
LINEARITY ERROR (+1/4 LSB)
DIGITAL INPUT CODE
DIFFERENTIAL LINEARITY
ERROR (-1/4 LSB)
1 LSB
ACTUAL
OFFSET
POINT
IDEAL OFFSET
POINT
ACTUAL
DIAGRAM
IDEAL DIAGRAM
OFFSET ERROR
(+1 1/4 LSB)
DIGITAL INPUT CODE
3
2
1
ANALOG OUTPUT VALUE
0
000 010001 011
7
6
5
ANALOG OUTPUT VALUE
4
0
000 101100 110 111
IDEAL FULL-SCALE OUTPUT
GAIN ERROR
(-1 1/4 LSB)
IDEAL DIAGRAM
ACTUAL
FULL-SCALE
OUTPUT
DIGITAL INPUT CODE
Page 14
MAX5186/MAX5189
Dual, 8-Bit, 40MHz, Current/Voltage,
Simultaneous-Output DACs
14 ______________________________________________________________________________________
ence, power-supply, and ground connections, which
may affect dynamic specifications like signal-to-noise
ratio or SFDR. In addition, electromagnetic interference
(EMI) can either couple into or be generated by the
MAX5186/MAX5189. Therefore, grounding and powersupply decoupling guidelines for high-speed, high-frequency applications should be closely followed.
First, a multilayer printed circuit (PC) board with separate ground and power-supply planes is recommended. High-speed signals should be run on controlled
impedance lines directly above the ground plane.
Since the MAX5186/MAX5189 have separate analog
and digital ground buses (AGND and DGND, respectively), the PC board should also have separate analog
and digital ground sections with only one point con-
necting the two. Digital signals should run above the
digital ground plane, and analog signals should run
above the analog ground plane. Digital signals should
be kept far away from the sensitive analog reference
and clock input.
Both devices have two power-supply inputs: analog
VDD(AVDD) and digital VDD(DVDD). Each AVDDinput
should be decoupled with parallel 10µF and 0.1µF
ceramic-chip capacitors. These capacitors should be
as close to the pin as possible, and their opposite ends
should be as close to the ground plane as possible.
The DVDDpins should also have separate 10µF and
0.1µF capacitors adjacent to their respective pins. Try
to minimize analog load capacitance for proper operation. For best performance, it is recommended to
Figure 6. Differential to Single-Ended Conversion Using a Low-Distortion Amplifier
+3V
+
10µF
R
+3V
D0–D7
SET
0.1µF
CLK
REFO
0.1µF
REFR
**
+
10µF
AV
DD
MAX5186
MAX5189
0.1µF
DV
DD
CREF1
CREF2
OUT1P
OUT1N
OUT2P
AVDDAV
DD
0.1µF0.1µF
402Ω
402Ω
-5V
+5V
OUTPUT 1
MAX4108
+5V
OUTPUT 2
400Ω
400Ω
400Ω*
402Ω
*
402Ω
*
402Ω
402Ω
-5V
MAX4108
**MAX5186 ONLY
402Ω
OUT2N
REN AGNDDGND
400Ω
*
402Ω
*400Ω RESISTORS INTERNAL TO MAX5189 ONLY.
Page 15
MAX5186/MAX5189
Dual, 8-Bit, 40MHz, Current/Voltage,
Simultaneous-Output DACs
______________________________________________________________________________________ 15
bypass CREF1 and CREF2 with low-ESR 0.1µF capacitors to AVDD.
The power-supply voltages should also be decoupled
with large tantalum or electrolytic capacitors at the
point they enter the PC board. Ferrite beads with additional decoupling capacitors forming a pi network can
also improve performance.
Chip Information
TRANSISTOR COUNT: 9464
SUBSTRATE CONNECTED TO AGND
Figure 7. Using the MAX5186/MAX5189 for I/Q Signal Reconstruction
+3V +3V
I COMPONENT
DAC1
+3V
BP
FILTER
DIGITAL
SIGNAL
PROCESSOR
MAX5186
MAX5189
Q COMPONENT
DAC2
CARRIER
FREQUENCY
BP
FILTER
0°
QUADRATURE
MODULATOR
90°
IF
Σ
MAX2452
Page 16
MAX5186/MAX5189
Dual, 8-Bit, 40MHz, Current/Voltage,
Simultaneous-Output DACs
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are
implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
16 ____________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600
© 1999 Maxim Integrated Products Printed USA is a registered trademark of Maxim Integrated Products.
Package Information
QSOP.EPS
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