Datasheet MAX3680EAI Datasheet (Maxim)

_________________General Description

The MAX3680 deserializer is ideal for converting
622Mbps serial data to 8-bit-wide, 77Mbps parallel
data in ATM and SDH/SONET applications. Operating
from a single +3.3V supply, this device accepts PECL
serial-clock and data inputs, and delivers TTL clock
and data outputs. It also provides a TTL synchroniza­tion input that enables data realignment and reframing.

The MAX3680 is available in the extended-industrial
temperature range (-40°C to +85°C), in a 28-pin SSOP
package.

__________________________Applications

622Mbps SDH/SONET Transmission Systems
622Mbps ATM/SONET Access Nodes
Add/Drop Multiplexers
Digital Cross Connects

______________________________Features

♦ Single +3.3V Supply
♦ 622Mbps Serial to 77Mbps Parallel Conversion
♦ 165mW Power
♦ Synchronization Input for Data Realignment and

Reframing

♦ Differential 3.3V PECL Clock and Data Inputs
♦ TTL Data Outputs and Synchronization Input

MAX3680

+3.3V, 622Mbps, SDH/SONET

1:8 Deserializer with TTL Outputs

________________________________________________________________

Maxim Integrated Products

1

MAX3675

MAX3664

MAX3680

DATA

AND

CLOCK

RECOVERY

OVERHEAD

TERMINATION

LIMITING
AMP

PREAMP

100Ω

PHOTODIODE

VCC = +3.3V

V

CC

= +3.3V

SD+
SD-

THIS SYMBOL REPRESENTS A TRANSMISSION LINE OF CHARACTERISTIC IMPEDANCE Z0 = 50Ω.

V

CC

GND

130Ω 130Ω

82Ω 82Ω

VCC = +3.3V

130Ω 130Ω

82Ω 82Ω

VCC = +3.3V

SCLK+
SCLK-

SYNC

PCLK

PD7

PD6

PD5

PD4

PD3

PD2

PD1

PD0

___________________________________________________________________Typical Operating Circuit

19-1210; Rev 0; 3/97

PART

MAX3680EAI -40°C to +85°C

TEMP. RANGE PIN-PACKAGE

28 SSOP

________________Ordering Information

For free samples & the latest literature: http://www.maxim-ic.com, or phone [phone]

Pin Configuration appears at end of data sheet.

EVALUATION KIT

AVAILABLE

MAX3680

+3.3V, 622Mbps, SDH/SONET
1:8 Deserializer with TTL Outputs

2 _______________________________________________________________________________________

ABSOLUTE MAXIMUM RATINGS

DC ELECTRICAL CHARACTERISTICS

(VCC= +3.0V to +3.6V, TA= -40°C to +85°C, unless otherwise noted. Typical values are at VCC= +3.3V, TA= +25°C.)

Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.

Note 1: AC characteristics guaranteed by design and characterization.

Terminal Voltage (with respect to GND)

V

CC

...........................................................................-0.5V to 5V

PECL Inputs (SD+/-, SCLK+/-).................-0.5V to (V

CC

+ 0.5V)

TTL Input (SYNC) .....................................-0.5V to (V

CC

+ 0.5V)

TTL Outputs (PCLK, PD_).........................-0.5V to (V

CC

+ 0.5V)

Continuous Power Dissipation (T

A

= +85°C)

SSOP (derate 9.52mW/°C above +85°C) ......................619mW

Operating Temperature Range ...........................-40°C to +85°C

Storage Temperature Range.............................-65°C to +160°C

Lead Temperature (soldering, 10sec).............................+300°C

TTL outputs = high

VIN= V

IL(MAX)

VIN= V

IH(MAX)

VIN= V

IH(MAX)

VIN= V

IL(MAX)

Output sinking = 400µA

Output sourcing = 400µA

CONDITIONS

V0 0.44V

OL

Output Low Voltage

V2.4 V

CC

V

OH

Output High Voltage

VVCC- 1.16 VCC- 0.88V

IH

Input High Voltage

mA25 50 90I

CC

Supply Current

µA-10 10I

IL

Input Low Current

µA-10 10I

IH

Input High Current

V0.8V

IL

Input Low Voltage

V2.0V

IH

Input High Voltage

VVCC- 1.81 VCC- 1.48V

IL

Input Low Voltage

µA-10 10I

IH

Input High Current

µA-10 10I

IL

Input Low Current

UNITSMIN TYP MAXSYMBOLPARAMETER

CONDITIONS

ps50t

H

Serial Data Hold Time

ps800t

SU

MHz622f

SCLK

Maximum Serial Clock Frequency
Serial Data Setup Time

UNITS

MIN TYP MAX

SYMBOLPARAMETER

PECL INPUTS (SD+/-, SCLK+/-)

TTL INPUT AND OUTPUTS (SYNC, PCLK, PD_)

AC ELECTRICAL CHARACTERISTICS

(VCC= +3.0V to +3.6V, TA= +25°C, unless otherwise noted.) (Note 1)

VCC= 3.3V, CL= 18pF ps-200 500 1300t

CLK-Q

Parallel Clock to Data Output Delay

MAX3680

+3.3V, 622Mbps, SDH/SONET

1:8 Deserializer with TTL Outputs

_______________________________________________________________________________________

3

1.2

0

MAXIMUM SERIAL-CLOCK FREQUENCY

vs. TEMPERATURE

MAX3680-01

SERIAL CLOCK FREQUENCY (GHz)

-25

1.1

25 50

1.0

0.9

0.8
75

100

TEMPERATURE (°C)

1.3

-50

360

0

SERIAL DATA-SETUP TIME

vs. TEMPERATURE

MAX3680-02

SERIAL DATA-SETUP TIME (ps)

-25

320

25 50

280

240

200

75

100

TEMPERATURE (°C)

400

-50

340

0

SERIAL DATA-HOLD TIME

vs. TEMPERATURE

MAX3680-03

SERIAL DATA-HOLD TIME (ps)

-25

280

25 50

220

160

100

75

100

TEMPERATURE (°C)

400

-50

60

50

0

SUPPLY CURRENT
vs. TEMPERATURE

MAX3680-04

SUPPLY CURRENT (mA)

-25

40

25 50

30

10

20

0

75

100

TEMPERATURE (°C)

70

-50

VCC = 3.6V

VCC = 3.0V

VCC = 3.3V

__________________________________________Typical Operating Characteristics

(VCC= +3.0V to +3.6V, unless otherwise noted.)

MAX3680

_______________Detailed Description

The MAX3680 deserializer uses an 8-bit shift register,
8-bit parallel output register, 3-bit counter, PECL input
buffers, and TTL input/output buffers to convert
622Mbps serial data to 8-bit-wide, 77Mbps parallel
data (Figure 1).

The input shift register continuously clocks incoming
data on the positive transition of the serial clock (SCLK)
input signal. The 3-bit counter generates a parallel out­put clock (PCLK) by dividing down the serial clock fre­quency. The PCLK signal is used to clock the parallel
output register. During normal operation, the counter
divides the SCLK frequency by eight, causing the out­put register to latch every eight bits of incoming serial
data.

The synchronization input (SYNC) is used for data
realignment and reframing. When the SYNC signal is
pulsed high for at least two SCLK cycles, PCLK is
delayed by one SCLK cycle, causing the first incoming
bit of the serial input data stream to be dropped. This
realignment is guaranteed to occur within two PCLK
cycles of the SYNC rising edge.

See Figure 2 for the functional timing diagrams and
Figure 3 for the timing parameters diagram.

+3.3V, 622Mbps, SDH/SONET
1:8 Deserializer with TTL Outputs

4 _______________________________________________________________________________________

______________________________________________________________Pin Description

NAME FUNCTION

1, 2, 5, 8,

14, 18, 25

V

CC

+3.3V Supply Voltage

3 SD+ Noninverting PECL Serial Data Input. Data is clocked on the SCLK signal’s positive transition.

PIN

4 SD- Inverting PECL Serial Data Input. Data is clocked on the SCLK signal’s positive transition.
6 SCLK+ Noninverting PECL Serial Clock Input

10 SYNC

TTL Synchronization Pulse Input. Pulse high for at least two SCLK periods to shift the data align­ment by dropping one bit in the serial input data stream.

9, 11, 12, 16,

20, 23, 27

GND Ground

7 SCLK- Inverting PECL Serial Clock Input

15, 17, 19, 21,

22, 24, 26, 28

PD0–PD7

TTL Parallel Data Outputs. Data is updated on the falling edge of PCLK. See Figure 2 for the relation­ship between serial-data-bit position and output-data-bit assignment.

13 PCLK TTL Parallel Clock Output

Figure 1. Functional Diagram

SD+

SD-

SCLK+

SCLK-

SYNC

PECL

PECL

TTL

8-BIT

SHIFT

REGISTER

MAX3680

3-BIT

COUNTER

8-BIT

PARALLEL

OUTPUT

REGISTER

TTL

TTL

TTL

TTL

TTL

TTL

TTL

TTL

TTL

PD7

PD6

PD5

PD4

PD3

PD2

PD1

PD0

PCLK

MAX3680

+3.3V, 622Mbps, SDH/SONET

1:8 Deserializer with TTL Outputs

_______________________________________________________________________________________ 5

SCLK*

SD*

PCLK

PD7

PD6

PD5
PD4

D1- D0 D1

D8-

D1 D9

D7-

D2 D10

D6-

D3 D11

D5-

D4 D12

PD3

PD2

PD1
PD0

D4-

D5 D13

D3-

D6 D14

D2-

D7 D15

D1-

D0

D8

D2 D3 D4 D5 D6 D7 D9 D10 D11 D12 D13 D14 D15 D16 D17 D18D8

* SIGNAL SHOWN IS DIFFERENTIAL. FOR EXAMPLE, SCLK = (SCLK+) - (SCLK-).

Figure 2a. Functional Timing Diagram—Normal Operation

MAX3680

+3.3V, 622Mbps, SDH/SONET
1:8 Deserializer with TTL Outputs

6 _______________________________________________________________________________________

SCLK*

SD*

SYNC

PCLK

PD7

PD6

PD5
PD4

D1- D0 D1

D8- D1 D9

D7- D2 D10

D6- D3 D11

D5- D4 D12

PD3

PD2

PD1
PD0

D4- D5 D13

D3- D6 D14

D2- D7 D15

D1- D8 D16

D2 D3 D4 D5 D6 D7 D9 D10 D11 D12 D13 D14 D15 D16 D17 D18D8

* SIGNAL SHOWN IS DIFFERENTIAL. FOR EXAMPLE, SCLK = (SCLK+) - (SCLK-).

Figure 2b. Functional Timing Diagram—SYNC Operation

SCLK*

SD*

PCLK

PD0–PD7

* SIGNAL SHOWN IS DIFFERENTIAL. FOR EXAMPLE, SCLK = (SCLK+) - (SCLK-).

t

SCLK

= 1 / f

SCLK

t

SU

t

H

t

CLK-Q

Figure 3. Timing Parameters

MAX3680

+3.3V, 622Mbps, SDH/SONET

1:8 Deserializer with TTL Outputs

_______________________________________________________________________________________ 7

PECL Inputs

The serial data and clock PECL inputs (SD+, SD-,
SCLK+, SCLK-) require 50Ω termination to (VCC- 2V)
when interfacing with a PECL source (see

Alternative

PECL Input Termination

).

__________Applications Information

Alternative PECL Input Termination

Figure 4 shows alternative PECL input-termination
methods. Use Thevenin-equivalent termination when a
(VCC- 2V) termination voltage is not available. If AC
coupling is necessary, such as when interfacing with
an ECL-output device, use the ECL AC-coupling termi­nation.

Layout Techniques

For best performance, use good high-frequency layout
techniques. Filter voltage supplies and keep ground
connections short. Use multiple vias where possible.
Also, use controlled impedance transmission lines to
interface with the MAX3680 data inputs.

MAX3680

PECL
INPUTS

Z

O

= 50Ω

ZO = 50Ω

130Ω

82Ω

130Ω

82Ω

+3.3V

MAX3680

PECL
INPUTS

ZO = 50Ω

50Ω

Z

O

= 50Ω

1.6k

2.7k

1.6k

2.7k

+3.3V

-2V

50Ω

-2V

THEVENIN-EQUIVALENT TERMINATION

ECL AC-COUPLING TERMINATION

Figure 4. Alternative PECL Input Termination

28
27

26
25
24
23
22
21
20
19
18
17
16
15

1
2
3
4
5
6
7
8

9
10
11
12
13
14

PD7
GND
PD6
V

CC

PD5
GND

PD0

PD4
PD3
GND
PD2
V

CC

PD1
GND

V

CC

PCLK

GND

GND

SYNC

GND

V

CC

SCLK-

SCLK+

V

CC

SD-

SD+

V

CC

V

CC

SSOP

TOP VIEW

MAX3680

__________________Pin Configuration

___________________Chip Information

TRANSISTOR COUNT: 1346

Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are
implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.

8

___________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 [phone]

© 1997 Maxim Integrated Products Printed USA is a registered trademark of Maxim Integrated Products.

MAX3680

+3.3V, 622Mbps, SDH/SONET
1:8 Deserializer with TTL Outputs

________________________________________________________Package Information

SSOP.EPS