Page 1
_______________General Description
The MAX3270 is a complete Clock Recovery and Data
Retiming IC for 155Mbps and 622Mbps SDH/SONET
and ATM applications. The MAX3270 meets Bellcore
and CCITT jitter tolerance specifications ensuring errorfree data recovery. Recovered clock and data are
phase aligned using a fully integrated phase-locked
loop (PLL). An output frequency monitor (FM) is included to detect loss of PLL acquisition or a loss of input
data.
The MAX3270 has differential ECL input and output
interfaces, so it is less susceptible to noise in a highfrequency environment. The fully integrated PLL
includes an integrated phase-frequency detector that
eliminates the need for external references.
________________________Applications
155Mbps (STM-1/OC-3)/622Mbps (STM-4/
OC-12) SDH/SONET Transmission Systems
155Mbps/622Mbps ATM/SONET Access Nodes
Add/Drop Multiplexers
Cross-Connects
____________________________Features
♦ Supports Both 155Mbps and 622Mbps Clock
Recovery and Data Retiming
♦ Fully Integrated Phase/Frequency Detector
♦ Capable of Switching to an External Clock
♦ Differential 100K ECL Data and Clock I/Os
♦ Output Monitor Provides Lock Detection
♦ No External Reference Clock Required
Pin Configuration appears at end of data sheet.
MAX3270
155Mbps/622Mbps Clock Recovery and
Data Retiming IC with Fully Integrated
Phase/Frequency Detector
________________________________________________________________
Maxim Integrated Products
1
MAX3270
50Ω
50Ω
50Ω
50Ω 50Ω
450Ω
11
+5V
3
4
41
42
13
18
20
14
17219 3839
VTTL
SDIP
RCON
CRP
FILP
FILG
FILN
FM
RCOP
RDOP
RDON
26
25
31
30
2.2µF
20Ω
-4.5V
2.2µF
20Ω
28
9
8
10
6
SDIN
PHADJ
-2V
-2V
-2V
EXCS AND CRS ARE CONNECTED FOR
622Mbps OPERATION.
BYPASS SUPPLIES WITH 0.1µF AND 0.01µF CAPACITORS.
DECOUPLE AVEE1, AVEE2, AND GVEE SUPPLY PINS.
50Ω
50Ω
DVCC
DVCC
AVEE1
AVEE2
GVEE
DVEE
DVEE
DVEE
DVEE
DVEE
DVCC
DVCC
AVCC
AVCC
AVCC
AVCC
OVCC
OVCC
OVCC
OVCC
16 15 57 272932
-2V
+5V
24
VR
EXCS
CRS
RST
EXC
12
-4.5V-4.5V -4.5V
-4.5V
DIGITAL
SUPPLY
ANALOG SUPPLY
1
35 36 22 21 34
___________________________________________________Typical Operating Circuit
Call toll free 1-800-998-8800 for free samples or literature.
19-0379; Rev 0; 3/95
PART
MAX3270EMH -40°C to +85°C
TEMP. RANGE PIN-PACKAGE
44 MQFP
______________Ordering Information
Page 2
MAX3270
155Mbps/622Mbps Clock Recovery and
Data Retiming IC with Fully Integrated
Phase/Frequency Detector
2 _______________________________________________________________________________________
ABSOLUTE MAXIMUM RATINGS
ELECTRICAL CHARACTERISTICS
(VEE= -4.5V ±5%, VTTL = 5V ±5%, TA= -40°C to +85°C, unless otherwise noted.)
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
Supply Voltages
VTTL to GND .....................................................-0.5V to +8.0V
V
CC
to GND.......................................................-0.5V to +8.0V
V
EE
to GND........................................................-8.0V to +0.5V
SDIP, SDIN, EXC...................................................-8.0V to +0.5V
RDOP, RDON, RCOP, RCON, CRP.......................-8.0V to +0.5V
EXCS, RST, CRS....................................................-0.5V to +8.0V
FILP, FILG, FILN....................................................-8.0V to +0.5V
PHADJ, VR ............................................................-8.0V to +8.0V
FM .........................................................................-8.0V to +8.0V
Input Differential Voltage Level, SDIP, SDIN ......................+3.0V
Continuous Power Dissipation (T
A
= +85°C).......................1.3W
Operating Temperature Range ...........................-40°C to +85°C
Storage Temperature Range.............................-55°C to +150°C
Lead Temperature (soldering, 10sec).............................+300°C
VR = PHADJ = 0, T
A
= +25°C
VTTL = 5.00V, VIN = 0.8V
VTTL = 5.00V, VIN = 2V
Loaded with 50Ω to -2V
Loaded with 470Ω to V
EE
Loaded with 470Ω to V
EE
VIN= VOL(typ)
VIN= VOH(typ)
Loaded with 50Ω to -2V
CONDITIONS
µA010I
BIAS
Input Bias Current
µA040I
IL
Input Low Current
µA040I
IH
Input High Current
V0.8V
IL
Input Low Voltage
V2V
IH
Input High Voltage
mV-1830 -1705 -1620V
OL
Output Low Voltage
mV-1025 -955 -870V
OH
Output High Voltage
mV-1830 -1705 -1550V
OL
Output Low Voltage
mA2.4 5I
TTL
Static Supply Current from VTTL
V-4.725 -4.50 -4.275V
EE
V4.75 5.00 5.25V
TTL
Positive Voltage Supply
(with respect to ground)
Negative Voltage Supply
(with respect to ground)
mV-1025 -955 -870V
OH
Output High Voltage
nA-100 100I
IL
Input Low Current
µA0 100I
IH
Input High Current
mA150 210I
VEE
Static Supply Current from V
EE
mV-1165 -870V
IH
Input High Voltage
mV-1830 -1475V
IL
Input Low Voltage
UNITSMIN TYP MAXSYMBOLPARAMETER
PHASE ADJUST INPUTS: PHADJ, VR
TTL INPUTS: CRS, RST, EXCS
LOW-POWER ECL OUTPUT: CRP
ECL OUTPUTS: RCOP, RCON, RDOP, RDON
ECL INPUTS: EXC, SDIP, SDIN
Page 3
MAX3270
155Mbps/622Mbps Clock Recovery and
Data Retiming IC with Fully Integrated
Phase/Frequency Detector
_______________________________________________________________________________________ 3
AC ELECTRICAL CHARACTERISTICS (continued)
(VEE= -4.5V, VTTL = 5V, TA= 25°C, unless otherwise noted.)
PHADJ = 0
Loaded with 50Ω to -2V and
5pF to GND
FILP and FILN shorted
FILP - FILN = 1.6V
FILP - FILN = 1.6V
FILP and FILN open
FILP and FILN shorted,
PFD = neutral state
ft= 622.08MHz
CONDITIONS
rad/V2K
PHADJ
Phase Offset Sensitivity, ∆Φ/∆PHADJ
mA/V1.25GmTransconduction Gain of Filter Amplifier
mV/rad192KDPhase-Detector Gain
MHz/V75K
O
Incremental Tuning Sensitivity
(Incremental Slope, ∆f/∆Vt)
MHz622.08F
O
Frequency of VCO
V/V0.95 1.05GFMGain of the Monitor Amplifier
ps600tr, t
f
Transition Time 20% to 80%
kHz/V550K
OV
Frequency Sensitivity to
Power-Supply Voltage
MHz/V3.75 6K
O
Mean Frequency Sensitivity
MHz610DF
O
Frequency Range
dB21 26GOLFilter Amplifier Open-Loop Voltage Gain
MHz38.00 39.50F
O
Center Frequency
UNITSMIN TYP MAXSYMBOLPARAMETER
175
180
185
190
150
-40 80
VEE SUPPLY CURRENT
vs. TEMPERATURE
155
170
MAX3270-TOC9
TEMPERATURE (°C)
V
EE
SUPPLY CURRENT (mA)
0 40 60 100-20 20
165
160
-4.75V
-4.5V
-4.25V
__________________________________________Typical Operating Characteristics
PHADJ = 0, FILP and FILN shorted mV-35 35V
O
Output Offset Voltage of the
Monitor Amplifier
Loaded with 50Ω to -2V and
5pF to GND
ps100TDTime Difference between RDO and RCO
ECL OUTPUTS: RDOP, RDON, RCOP, RCON
VCO TEST PARAMETERS; CPR OUTPUT
PLL ELECTRICAL SPECIFICATIONS
PFD AND FILTER AMPLIFIER TEST LEVELS
38.8
38.9
39.0
38.3
0 60 80 100
CRP FREE-RUNNING FREQUENCY (VCO/16)
vs. DIE TEMPERATURE
38.4
38.7
MAX3270-TOC5
TEMPERATURE (°C)
FREQUENCY (MHz)
20 40 50 70 9010 30
38.6
38.5
MEASURED
Page 4
MAX3270
155Mbps/622Mbps Clock Recovery and
Data Retiming IC with Fully Integrated
Phase/Frequency Detector
4 _______________________________________________________________________________________
__________________________________________Typical Operating Characteristics
0.1
10 1k 10k 100k 1M
JITTER TOLERANCE
(155Mbps, 2
23
-1 PRBS)
1.0
10.0
MAX3270-TOC1
FREQUENCY (Hz)
AMPLITUDE (UI p-p)
100
DATA
BELLCORE
MASK
0.1
10 1k 10k 100k 1M
JITTER TOLERANCE
(622Mbps, 2
23
-1 PRBS)
1.0
10.0
MAX3270-TOC2
FREQUENCY (Hz
)
AMPLITUDE (UI p-p)
100
DATA
BELLCORE
MASK
Page 5
MAX3270
155Mbps/622Mbps Clock Recovery and
Data Retiming IC with Fully Integrated
Phase/Frequency Detector
_______________________________________________________________________________________
5
155Mbps RECOVERED CLOCK AND
RETIMED DATA (SINGLE ENDED)
DATA
CLOCK
2ns/div
622Mbps RECOVERED CLOCK AND
RETIMED DATA (SINGLE ENDED)
DATA
CLOCK
500ps/div
RECOVERED CLOCK JITTER
(155Mbps, 1-0 PATTERN, 4.7ps RMS)
Mean 40.65ns
RMS∆ 4.7ps
PkPk 38.4ps
µ±1σ 69.674%
µ±2σ 95.558%
µ±3σ 99.698%
10ps/div
RF = 20Ω
C
F
= 2.2µF
RECOVERED CLOCK JITTER
(155Mbps, 2
7
-1 PRBS, 5.1ps RMS)
Mean 40.61ns
RMS∆ 5.13ps
PkPk 45.6ps
µ±1σ 68.961%
µ±2σ 95.844%
µ±3σ 99.717%
10ps/div
RF = 20Ω
C
F
= 2.2µF
RECOVERED CLOCK JITTER
(622Mbps 2
7
-1 PRBS 9.0ps RMS)
Mean 38.68ns
RMS∆ 9.049ps
PkPk 79.4ps
µ±1σ 69.747%
µ±2σ 95.453%
µ±3σ 99.582%
10ps/div
RF = 20Ω
C
F
= 2.2µF
__________________________________________Typical Operating Characteristics
Page 6
MAX3270
155Mbps/622Mbps Clock Recovery and
Data Retiming IC with Fully Integrated
Phase/Frequency Detector
6 _______________________________________________________________________________________
______________________________________________________________Pin Description
Loop Filter Positive. This pin connects to an external filter.FILP9
Loop Filter Negative. This pin connects to an external filter.FILN10
TTL Positive Supply: +5.0VVTTL11
Negative Supply for VCO: -4.5VAVEE212
External Clock-Select TTL Input. A logical high selects the external clock.EXCS13
Ground for Input Buffers: 0VAVCC5
Frequency Monitor Output. This pin monitors the input voltage to the VCO. When the PLL is locked,
the pin will be ≅ 0V.
FM6
Guard-Ring Positive Supply to Epi: 0VAVCC7
Loop Filter Ground. This pin connects to an external filter.FILG8
Serial Data Input: 155Mbps or 622Mbps. Differential ECL Negative.SDIN4
Serial Data Input: 155Mbps or 622Mbps. Differential ECL Positive.SDIP3
PIN
Negative Supply for Input Buffers: -4.5VAVEE12
Guard-Ring Negative Supply to Substrate: -4.5VGVEE1
FUNCTIONNAME
14 EXC External Clock. Single-ended ECL input.
15, 16 AVCC Ground for VCO: 0V
17, 19, 38,
39
DVCC Digital Ground for Mux: 0V
18 CRS
Clock-Rate Select TTL Input. This selects the clock rate to be either 155Mbps or 622Mbps. A logichigh level selects the 622Mbps mode.
20 RST Resets all digital flip-flops, TTL input. Reset is assert when low.
21, 22, 34,
35, 36
DVEE Digital Negative Supply: -4.5V
23, 33, 37,
40, 43, 44
N.C. No Connection
24, 27, 29,
32
OVCC Output Driver Ground: 0V
25 RDON Negative Recovered Data Output, differential ECL output: 155Mbps or 622Mbps.
26 RDOP Positive Recovered Data Output, differential ECL output: 155Mbps or 622Mbps.
28 CRP Clock-Reference Output Divide-by-4. ECL low-power single-ended: 38Mbps or 155Mbps.
30 RCON Negative Recovered Clock Output, differential ECL output: 155Mbps or 622Mbps.
31 RCOP Positive Recovered Clock Output, differential ECL output: 155Mbps or 622Mbps.
41 PHADJ
Phase Adjust. This is an analog adjustment that varies the static phase between the input data and
the recovered clock. If not used, this input should be grounded. The range is from -1V to 1V.
42 VR Phase Reference Voltage: 0V. The PHADJ pin compares to this voltage. Set to ground.
Page 7
_______________Detailed Description
The block diagram of Figure 1 shows the MAX3270’s
architecture. The phase-locked loop (PLL) consists of a
phase/frequency detector (PFD), a loop filter amplifier,
and a voltage-controlled oscillator (VCO).
Phase Detector
The phase detector produces a voltage proportional to
the phase difference of the incoming data and the output of the recovered clock. Because of its feedback
nature, the PLL will drive the error voltage to zero, making the phase difference zero and aligning the recovered clock to the incoming data. An external
phase-adjustment pin (PHADJ) allows the user to vary
phase alignment.
Frequency Detector
A frequency detector is also incorporated into the PLL.
Frequency detection aids in the acquisition of the input
data; this frequency-aided acquisition is necessary during start-up conditions, since the input data stream and
VCO difference frequency may be outside the PLL
bandwidth. The input data stream is sampled by quadrature components of the VCO clock, generating a difference frequency. Depending on the rotation of the
difference frequency, the PFD will drive the VCO so that
the difference frequency is driven to zero. Once frequency acquisition is obtained, the frequency detector
will return to a neutral state.
Loop Filter and VCO
The PLL is a second-order transfer function whose
bandwidth is set by the loop filter. The VCO is integrated into the PLL and always operates at 622MHz. The
center frequency is tightly controlled by laser trimming,
limiting frequency drift when lock is lost. 155Mbps or
622Mbps mode is selected by the clock-rate select
(CRS) pin. CRS selects the inputs to multiplexer MUX2.
The internal VCO can be bypassed with an external
clock applied to the EXC input. The external clock
select (EXCS) controls the input selections to multiplexers MUX1 and MUX2.
MAX3270
155Mbps/622Mbps Clock Recovery and
Data Retiming IC with Fully Integrated
Phase/Frequency Detector
_______________________________________________________________________________________ 7
PHASE/FREQ
DETECTOR
VCO
622.08MHz
DIVIDE-
BY-4
CLK
OUTPUT
INPUT
MUX 3
MUX 2 MUX 1
SDIP
SDIN
FILTER
AMP
RST
PHADJ VR
FILPQFILN
D
RDOP
RDON
CRP
38/155MHz
RCOP
RCON
EXCS
EXC
RST
CRS
0
1
0
1
1
0
155MHz
622MHz
100k
ECL
100k
ECL
100k
ECL
MAX3270
FM
CLK
RECOVERED
DATA
RECOVERED
CLOCK
Figure 1. Block Diagram
Page 8
MAX3270
__________________Design Procedure
Selecting the Data Rate
The MAX3270 is intended for use in SDH/SONET systems operating at 155.52Mbps or 622.08Mbps data
rates. TTL inputs (CRS and EXCS) are provided for
selecting the recovered clock rate (Table 1). It is also
possible to switch to an externally supplied clock by
enabling the EXC input. The EXC input is a high-speed
single-ended ECL interface capable of handling serial
clock rates of 155MHz and 622MHz.
Setting the Loop Filter
The loop filter within the PLL consist of a transconductance amplifier and the external filter elements Rf and
Cf (Figure 2). The closed-loop bandwidth of a PLL can
be approximated by:
KDKOGm Rf
where KDis the gain of the phase detector, KO is the
gain of the VCO, and Gm is the transconductance of
the filter amplifier. Because this filter is an integrator, a
zero in the open-loop gain is required for stability. This
zero is set by the following equation:
wz= 1 / (Rf Cf)
where the recommended external values are Rf = 20Ω
and Cf = 2.2µF. To decrease the PLL’s closed-loop
bandwidth, reduce the value of Rf. Decreasing this
bandwidth will improve the MAX3270’s jitter transfer
performance but reduce jitter tolerance. The MAX3270
has been designed (using the recommended values of
Rf and Cf) to meet the Bellcore and CCITT specifications for jitter tolerance of a Network Element. Carefully
consider the application if a reduction in loop bandwidth is desired. By reducing Rf an order of magnitude,
the PLL’s bandwidth becomes more sensitive to the
internal tolerances of the IC. As a result, the loop bandwidth may have a wider variation. If Rf is reduced, then
Cf should also be increased to maintain loop stability
and minimize jitter peaking.
The MAX3270 is optimally designed to acquire lock
and to provide a bit-error rate (BER) of less than 10
-12
for long strings of consecutive zeros or ones. Using the
recommended external values for Rf = 20Ω and Cf =
2.2µF, measured results show that the MAX3270 can
tolerate more than 200 consecutive ones or zeros.
Figure 3 shows a bit stream of 213- 1 PRBS with 200
consecutive ones.
155Mbps/622Mbps Clock Recovery and
Data Retiming IC with Fully Integrated
Phase/Frequency Detector
8 _______________________________________________________________________________________
Table 1. MAX3270 Logic Table
EXCS CRS RCOP/RCON CRP
0 1 155.52Mbps 38.88Mbps
0 0 622.08Mbps 155.52Mbps
1 0 EXC EXC/4
1 1 EXC/4 EXC/16
100ns/div 2.532µs1.532µs
RECOVERED DATA OUTPUT
(2
13
-1 PRBS WITH 200 CONSECUTIVE ONES
BER <10
-
12
, 622Mbps)
PRBS
200 ONES
MAX3270
FILP
FILG FILN
Rf
Cf
Rf
Cf
F(s) =
____________
wz =
____
Rf = 20Ω
Cf = 2.2µF
Gm
(
___
+ 1
)
s
wz
Cf s
1
Rf Cf
Gm
F(s)
Figure 2. Loop Filter
Figure 3. Recovered Data Output
Page 9
Input and Output Termination
The MAX3270 data and clock I/Os (SDIP, SDIN, RDOP,
RDON, RCOP, RCON, and EXC) are open emitters,
designed to interface with ECL signal levels. It is important to bias these ports appropriately. A circuit that provides a Thevenin equivalent of 50Ω to -2V should be
used with fixed-impedance transmission lines for proper termination. Figure 4 shows some typical input and
output termination methods.
The serial data input signals (SDIP and SDIN) are the
differential inputs to an emitter coupled pair. As a result,
the MAX3270 can accept differential input signal levels
as low as 250mV. The serial input (SDIP) can also be
driven single-ended by externally biasing SDIN to the
center of the voltage swing (approximately -1.3V). Make
sure that the differential inputs and outputs each see the
same termination impedance for balanced operation.
CRP is also an open-emitter ECL output, but it requires
a termination resistor of 450Ω to -4.5V. If this output is
not used, reduce power by connecting CRP to V
EE
through a resistor valued at 10kΩ or more.
The MAX3270’s performance can be greatly affected
by circuit board layout and design. Use good high-frequency design techniques, including minimizing
ground inductances and using fixed-impedance transmission lines on the data and clock signals. Power-
supply decoupling should be placed as close to the
VEE and VTTL pins as possible. AVEE1, AVEE2 and
GVEE should each have their own bypass/decoupling
elements, independent of each other and any other -
4.5V supply. Make sure to isolate the inputs from the
outputs to reduce feedthrough.
__________Applications Information
Lock Detection
The MAX3270 has an output (FM) that monitors the input
voltage to the VCO. FM is an analog output that can be
used as a flag to indicate that the PLL is locked. Under
normal operation, the loop is locked and the FM output
is approximately equal to 0V. When the PLL is unlocked,
the VCO will drift. The FM output monitors this drift and
will equal approximately ±1V in the limit.
Phase Adjust
In some applications, the optimum alignment point
between the recovered clock and the serial data is not
at the center of the eye diagram. The MAX3270 has a
PHADJ input that can be used in these applications to
introduce a phase difference between the recovered
clock and the serial data. When no phase difference is
desired, this input should be set to 0V. The VR pin is the
reference input for PHADJ and is normally tied to GND.
MAX3270
155Mbps/622Mbps Clock Recovery and
Data Retiming IC with Fully Integrated
Phase/Frequency Detector
_______________________________________________________________________________________ 9
90.9Ω 90.9Ω
111Ω
450Ω
111Ω
Zo = 50Ω
Zo = 50Ω
90.9Ω 90.9Ω
111Ω 111Ω
Zo = 50Ω
Zo = 50Ω
-4.5V
-4.5V
-4.5V
50Ω
450Ω
50Ω
Zo = 50Ω
Zo = 50Ω
50Ω 50Ω
Zo = 50Ω
Zo = 50Ω
-2V
-4.5V
-2V
MAX3270
MAX3270
ECL
INPUTS
ECL
OUTPUTS
CRP
CRP
ECL
INPUTS
ECL
OUTPUTS
50Ω to -2V TERMINATION
THEVENIN EQUIVALENT TERMINATION
Figure 4. Typical Input and Output Terminations
Page 10
MAX3270
155Mbps/622Mbps Clock Recovery and
Data Retiming IC with Fully Integrated
Phase/Frequency Detector
10 ______________________________________________________________________________________
MQFP
TOP VIEW
MAX3270
OVCC
RCOP
RCON
OVCC
CRP
RDON
OVCC
N.C.
N.C.
RDOP
OVCC
AVEE1
SDIP
SDIN
AVCC
FM
FILP
FILN
VTTL
GVEE
FILG
AVCC
N.C.
VR
DVCC
PHADJ
N.C.
DVCC
N.C.
N.C.
DVEE
DVEE
DVEE
EXCS
EXC
CRS
AVCC
AVCC
DVCC
AVEE2
DVCC
RST
DVEE
DVEE
2221201918171615141312
23
24
25
26
27
28
29
30
31
32
33
3435363738394041424344
11
10
9
8
7
6
5
4
3
2
1
__________________Pin Configuration
Page 11
MAX3270
155Mbps/622Mbps Clock Recovery and
Data Retiming IC with Fully Integrated
Phase/Frequency Detector
______________________________________________________________________________________ 11
________________________________________________________Package Information
E3
E1
E
e
b
D3
D1
D
44-PIN MQFP
METRIC
QUAD FLAT PACK
DIM
A
A1
A2
b
C
D
D1
D3
E
E1
E3
e
L
α
MIN
2.032
0.102
1.930
0.305
0.102
12.954
9.906
12.954
9.906
0.660
0°
MAX
2.388
0.254
2.134
0.457
0.254
13.462
10.109
13.462
10.109
0.940
10°
MIN
0.080
0.004
0.076
0.012
0.004
0.510
0.390
0.510
0.390
0.025
0°
MAX
0.094
0.010
0.084
0.018
0.010
0.530
0.398
0.530
0.398
0.037
10°
MILLIMETERS INCHES
0.315 REF
3.429 REF
3.429 REF
0.800 REF
0.315 REF
0.315 REF
C
SEE DETAIL "A"
A
A2
A1
α
DETAIL "A"
L
21-0826A
Page 12
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are
implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
12
__________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 (408) 737-7600
© 1995 Maxim Integrated Products Printed USA is a registered trademark of Maxim Integrated Products.
MAX3270
155Mbps/622Mbps Clock Recovery and
Data Retiming IC with Fully Integrated
Phase/Frequency Detector
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are
implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
12
__________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 (408) 737-7600
© 1995 Maxim Integrated Products Printed USA is a registered trademark of Maxim Integrated Products.
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