The MAX17552/MAX17552A high-efficiency, high-voltage,
synchronous step-down DC-DC converters with integrated
MOSFETs operate over a 4V to 60V input voltage range.
The converters can deliver output current up to 100mA at
output voltages of 0.8V to 0.9 x VIN. The output voltage
is accurate to within ±1.75% over the -40°C to +125°C
temperature range.
The devices employ a peak-current-mode control
architecture with a MODE pin that can be used to operate
the device in pulse-width modulation (PWM) or pulsefrequency modulation (PFM) control schemes. PWM
operation provides constant frequency operation at all
loads and is useful in applications sensitive to variable
switching frequency. PFM operation disables negative
inductor current and additionally skips pulses at light
loads for high efficiency. The converters consume only
22µA of no-load supply current in PFM mode. The low-
resistance, on-chip MOSFETs ensure high efficiency at
full load and simplify PCB layout.
The devices offer programmable switching frequency to
optimize solution size and efficiency. Programmable softstart allows the user to reduce the inrush currents. During
overload, the MAX17552 implements a hysteretic cycleby-cycle peak-current-limit protection scheme, while the
MAX17552A implements a HICCUP-type overload protection scheme to protect the inductor and the internal FETs.
An EN/UVLO pin allows the user to turn on/off the device
at the desired input-voltage level. An open-drain RESET
pin allows output-voltage monitoring. The devices operate
over the -40°C to +125°C industrial temperature range
and is available in a compact 10-pin (3mm x 2mm) TDFN
and 10-pin (3mm x 3mm) μMAX® packages. Simulation
models are available.
Applications
● Industrial Sensors and Process Control
● 4mA–20mA Current-Loop Powered Sensors
● High-Voltage LDO Replacement
● Battery-Powered Equipment
● HVAC and Building Control
● General-Purpose Point of Load
Benets and Features
●
Eliminates External Components and Reduces Total Cost
• No Schottky—Synchronous Operation for High
Eciency and Reduced Cost
• Internal Compensation
• Fixed Internal 5.1ms or Programmable Soft-Start
• All-Ceramic Capacitors, Ultra-Compact Layout
● Reduces Number of DC-DC Regulators to Stock
• Wide 4V to 60V Input Voltage Range
• Adjustable 0.8V to 0.9 x VIN Output Voltages
• Delivers Up to 100mA Load Current
• 100kHz to 2.2MHz Adjustable Switching Frequency
Range with External Synchronization
• Congurable Between PFM and Forced-PWM
Modes
● Reduces Power Dissipation
• 22µA No Load Supply Current
• Peak Eciency > 90%
• PFM Feature for High Light-Load Eciency
• 1.2μA (typ) Shutdown Current
● Operates Reliably in Adverse Industrial Environments
• Peak Current-Limit Protection
● Built-In Output-Voltage Monitoring with Open-Drain
RESET Pin
• Programmable EN/UVLO Threshold
• Monotonic Startup into Prebiased Output
• Overtemperature Protection
• High Industrial -40°C to +125°C Ambient Operating
Temperature Range / -40°C to +150°C Junction
Temperature Range
Ordering Information appears at end of data sheet.
µMAX is a registered trademark of Maxim Integrated Products, Inc.
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these
or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect
device reliability.
Note 1: Junction temperature greater than +125°C degrades operating lifetimes.
Package Information
PACKAGE TYPE: 10 TDFN
Package Code T1032N+1
Outline Number21-0429
Land Pattern Number90-0082
THERMAL RESISTANCE, FOUR-LAYER BOARD
Continuous Power Dissipation (TA = +70°C)
(derate 14.9mW/°C above +70°C)
Junction to Ambient (θJA)67.3°C/W
Junction to Case (θJC) 18.2°C/W
, RESET to GND...................-0.3V to +70V
OUT
Junction Temperature ......................................................+150°C
Storage Temperature Range ............................ -65°C to +150°C
Lead Temperature (soldering, 10s) ................................. +300°C
Soldering Temperature (reflow) ....................................... +260°C
1188.7mW
PACKAGE TYPE: 10 µMAX
Package Code U10+5
Outline Number21-0061
Land Pattern Number90-0330
THERMAL RESISTANCE, FOUR-LAYER BOARD
Continuous Power Dissipation (TA = +70°C)
(derate 8.8mW/°C above +70°C)
Junction to Ambient (θJA)113.1°C/W
Junction to Case (θJC) 42°C/W
For the latest package outline information and land patterns (footprints), go to www.maximintegrated.com/packages. Note that a “+”,
“#”, or “-” in the package code indicates RoHS status only. Package drawings may show a different suffix character, but the drawing
pertains to the package regardless of RoHS status.
Package thermal resistances were obtained using the method described in JEDEC specification JESD51-7, using a four-layer board.
For detailed information on package thermal considerations, refer to www.maximintegrated.com/thermal-tutorial.
(VIN = 24V, V
TA = -40°C to +125°C, unless otherwise noted. Typical values are at TA = +25°C. All voltages are referenced to GND, unless otherwise
noted) (Note 2)
(VIN = 24V, V
TA = -40°C to +125°C, unless otherwise noted. Typical values are at TA = +25°C. All voltages are referenced to GND, unless otherwise
noted) (Note 2)
Switching Frequency Adjustable
Range
SYNC Input Frequency1.1 x f
SYNC Pulse Minimum O-Time40ns
SYNC Rising ThresholdV
HysteresisV
Number of SYNC Pulses to
Enable Synchronization
TIMING
Minimum On-Timet
Maximum Duty CycleD
Hiccup TimeoutMAX17552A51ms
RESET
FB Threshold for RESET RisingV
FB Threshold for RESET FallingV
RESET Delay after FB Reaches
95% Regulation
RESET Output Level LowI
RESET Output Leakage CurrentVFB = 1.01 x V
MODE
MODE PFM ThresholdV
MODE HysteresisV
MODE Internal Pullup Resistor
THERMAL SHUTDOWN
Thermal-Shutdown ThresholdTemperature rising160°C
Thermal-Shutdown Hysteresis20°C
Note 2: Limits are 100% tested at TA = +25°C. Limits over the operating temperature range and relevant supply voltage range are
1INSwitching Regulator Input. Connect a X7R 1µF ceramic capacitor from IN to GND for bypassing.
Active-High, Enable/Undervoltage-Detection Input. Pull EN/UVLO to GND to disable the regulator
2EN/UVLO
3RT/SYNC
4SS
5FB
6VOUT
output. Connect EN/UVLO to IN for always-on operation. Connect a resistor-divider between IN,
EN/UVLO, and GND to program the input voltage at which the device is enabled and turns on.
Oscillator Timing Resistor Input. Connect a resistor from RT/SYNC to GND to program the switching
frequency from 100kHz to 2.2MHz. See the Switching Frequency (RT/SYNC) section for details. An
external pulse can be applied to RT/SYNC through a coupling capacitor to synchronize the internal clock
to the external pulse frequency. See the External Synchronization section for details.
Soft-Start Capacitor Input. Connect a capacitor from SS to GND to set the soft-start time. Leave SS
unconnected for default 5.1ms internal soft-start.
Output Feedback Connection. Connect FB to a resistor-divider between V
output voltage. See the Adjusting the Output Voltage section for details.
External Bias Input for Internal Control Circuitry. Decouple to GND with a 0.22μF capacitor and connect to
output capacitor positive terminal with a 22.1Ω resistor for applications with an output voltage from 3.3V to
5V. Connect to GND for output voltages < 3.3V and > 5V. See the External Bias section for details.
RESET
SSEN/
V
OUT
+
1LXIN
EN/UVLO
RT/SYNC
5
FB
2
MAX17552/
3
SS
FB
MAX17552A
4
5
µMAX
10
9
GND
8
MODE
7
RESET
6
V
OUT
3mm x 3mm
and GND to set the
OUT
7RESET
pulls low if FB voltage drops below 92% of its set value. RESET goes high impedance 2ms after FB
voltage rises above 95% of its set value.
Open-Drain Reset Output. Pull up RESET to an external power supply with an external resistor. RESET
8MODE
9GND
10LX
PFM/PWM Mode-Selection Input. Connect MODE to GND to enable the xed-frequency PWM
operation. Leave MODE unconnected for light-load PFM operation.
Ground. Connect GND to the power ground plane. Connect all the circuit ground connections together at
a single point. See the PCB Layout Guidelines section.
Inductor Connection. Connect LX to the switching side of the inductor. LX is high impedance when the
device is in shutdown.
—EPExposed Pad (TDFN Only). Connect to the GND pin to the IC.
The MAX17552/MAX17552A high-efficiency, high-voltage,
synchronous step-down DC-DC converters with integrated
MOSFETs operate over a 4V to 60V input voltage range.
The converter can deliver output current up to 100mA at
output voltages of 0.8V to 0.9 x VIN. The output voltage
is accurate to within ±1.75% over -40°C to +125°C. The
converter consumes only 22µA of supply current in PFM
mode while regulating the output voltage at no load.
The devices use an internally compensated, peakcurrent-mode control architecture (see the Block
Diagram). On the rising edge of the internal clock, the
high-side pMOSFET turns on. An internal error amplifier
compares the feedback voltage to a fixed internal reference
voltage and generates an error voltage. The error voltage
is compared to a sum of the current-sense voltage and
a slope-compensation voltage by a PWM comparator to
set the “on-time.” During the on-time of the pMOSFET,
the inductor current ramps up. For the remainder of the
switching period (off-time), the pMOSFET is kept off and
the low-side nMOSFET turns on. During the off-time,
the inductor releases the stored energy as the inductor
current ramps down, providing current to the output.
Under overload conditions, cycle-by-cycle current-limit
feature limits inductor peak current by turning off the highside pMOSFET and turning on the low-side nMOSFET.
Mode Selection (MODE)
The devices feature a MODE pin for selecting either
forced-PWM or PFM mode of operation. If the MODE pin
is left unconnected, the devices operate in PFM mode
at light loads. If the MODE pin is grounded, the devices
operate in a constant-frequency forced-PWM mode at all
loads. Mode of operation can be changed on-the-fly during
normal operation of the device.
In PWM mode, the inductor current is allowed to go
negative. PWM operation is useful in frequency-sensitive
applications and provides fixed switching frequency at
all loads. However, the PWM mode of operation gives
lower efficiency at light loads compared to PFM mode of
operation.
PFM mode disables negative inductor current and additionally skips pulses at light loads for high efficiency. In
PFM mode, the inductor current is forced to a fixed peak
of 72mA (typ) (I
rises to 102% (typ) of the nominal voltage. Once the
output reaches 102% (typ) of the nominal voltage, both
high-side and low-side FETs are turned off and the device
) every clock cycle until the output
PFM
enters hibernate operation until the load discharges the
output to 101% (typ) of the nominal voltage. Most of
the internal blocks are turned off in hibernate operation
to save quiescent current. After the output falls below
101% (typ) of the nominal voltage, the devices come
out of hibernate operation, turns on all internal blocks,
and again commences the process of delivering pulses
of energy to the output until it reaches 102% (typ) of the
nominal output voltage. The devices naturally exit PFM
mode when the load current increases to a magnitude of
approximately:
I
- (ΔI/2)
PFM
where ΔI is the peak-peak ripple current in the output
inductor. The part enters PFM mode again if the load
current reduces to approximately (ΔI/2). See the Inductor
Selection section for details. The advantage of the PFM
mode is higher efficiency at light loads because of lower
current drawn from the supply.
Enable Input (EN/UVLO) and Soft-Start (SS)
When EN/UVLO voltage increases above 1.25V (typ), the
devices initiate a soft-start sequence and the duration of
the soft-start depends on the status of the SS pin voltage
at the time of power-up. If the SS pin is not connected,
the devices use a fixed 5ms internal soft-start to ramp
up the internal error-amplifier reference. If a capacitor is
connected from SS to GND, a 5μA current source charges
the capacitor and ramps up the SS pin voltage. The SS
pin voltage is used as reference for the internal error
amplifier. Such a reference ramp up allows the output
voltage to increase monotonically from zero to the final
set value independent of the load current.
EN/UVLO can be used as an input voltage UVLOadjustment input. An external voltage-divider between
INand EN/UVLO to GND adjusts the input voltage at
which the device turns on or turns off. See the Setting
the Input Undervoltage-Lockout Level section for details.
If input UVLO programming is not desired, connect EN/
UVLO to IN(see the Electrical Characteristicstable for
EN/UVLO rising and falling-threshold voltages). Driving
EN/UVLO low disables both power MOSFETs, as well as
other internal circuitry, and reduces INquiescent current
to below 1.2μA. The SS capacitor is discharged with an
internal pulldown resistor when EN/UVLO is low. If the
EN/UVLO pin is driven from an external signal source,
a series resistance of minimum 1kW is recommended to
be placed between the signal source output and the EN/
UVLO pin, to reduce voltage ringing on the line.
Switching frequency of the devices can be programmed
from 100kHz to 2.2MHz by using a resistor connected
from RT/SYNC to GND. The switching frequency (fSW)
is related to the resistor connected at the RT/SYNC pin
(RT) by the following equation, where RT is in kΩ and fSW
is in kHz:
Rf=
T
SW
The switching frequency in ranges of 130kHz to 160kHz
and 230kHz to 280kHz are not allowed for user programming to ensure proper configuration of the internal
adaptive-loop compensation scheme.
External Synchronization
The RT/SYNC pin can be used to synchronize the
device’s internal oscillator to an external system clock.
The external clock should be coupled to the RT/SYNC
pin through a 47pF capacitor, as shown in Figure 1. The
external clock logic high level should be higher than
3V, logic low level lower than 0.5V and the duty cycle
of the external clock should be in the range of 10% to
70%. External clock synchronization is allowed only in
PWM mode of operation (MODE pin connected to GND).
The RT resistor should be selected to set the switching
frequency 10% lower than the external clock frequency.
The external clock should be applied at least 500μs
after enabling the device, for proper configuration of the
internal loop compensation.
MAX17552/
R
T
MAX17552A
RT/SYNC
47pF
CLOCK
SOURCE
V
LOGIC-HIGH
V
LOGIC-LOW
DUTY
Figure 1. Synchronization to an External Clock
External Bias (V
The devices provide a V
blocks from a low-voltage supply. When the V
OUT
)
pin to power the internal
OUT
OUT
pin
voltage exceeds 3.1V, the devices draw switching and
quiescent current from this pin to improve the converter’s
efficiency. In applications with an output voltage setting
from 3.3V to 5V, V
should be decoupled to GND
OUT
with a ceramic capacitor, and should be connected to the
positive terminal of the output capacitor with a resistor
(R4, C1) as shown in the typical application circuits. In
the absence of R4 and C1, the absolute maximum rating of V
(-0.3V) can be exceeded under short-circuit
OUT
conditions, due to oscillations between the ceramic output
capacitor and the inductance of the short-circuit path. In
general, parasitic board or wiring inductance should be
minimized and the output voltage waveform under short
circuit operation should be verified to ensure that the
absolute maximum rating of V
is not exceeded. For
OUT
applications with an output voltage setting less than 3.3V
or greater than 5V, V
should be connected to GND.
OUT
Reset Output (RESET)
The devices include an open-drain RESET output to
monitor output voltage. RESET should be pulled up with
an external resistor to the desired external power supply.
RESET goes high impedance 2ms after the output rises
above 95% of its nominal set value and pulls low when
the output voltage falls below 92% of the set nominal
output voltage.
Startup Into a Prebiased Output
The devices support monotonic startup into a prebiased
output. When the device starts into a prebiased output,
both the high-side and low-side switches are turned off so
that the converter does not sink current from the output.
High-side and low-side switches do not start switching
until the PWM comparator commands the first PWM
pulse, at which point switching commences. The output
voltage is then smoothly ramped up to the target value
in alignment with the internal reference. Such a feature is
useful in applications where digital integrated circuits with
multiple rails are powered.
Operating Input Voltage Range
The maximum operating input voltage is determined
by the minimum controllable on-time, and the minimum
operating input voltage is determined by the maximum
duty cycle and circuit voltage drops. The minimum and
maximum operating input voltages for a given output voltage should be calculated as follows:
where V
the maximum load current, R
the inductor, fSW is the switching frequency (max), D
is the maximum duty cycle (0.9), and t
OUTOUTDCR
D
MAX
V
V
INMAX
is the steady-state output voltage, I
OUT
=
OUT
ONMINSW
×
is the DC resistance of
DCR
ONMIN
is
OUT
MAX
is the worst-
case minimum controllable switch on-time (128ns)
Overcurrent Protection
The MAX17552 implements a hysteretic cycle-by-cycle
peak-current limit protection scheme to protect the inductor
and internal FETs under output short circuit conditions.
When the inductor peak current exceeds 0.21A (typ), high
side switch is turned off and low side switch is turned
on to discharge the inductor current. Subsequent clock
pulses do not turn on the high-side switch until inductor
current discharges to 0.15A (typ). This operation continues until overload/short circuit is removed on the output.
Since the inductor current is bounded between two limits,
inductor current runaway never happens in this scheme.
Additionally, hysteretic negative peak current limit controls
the low-side switch negative current when it exceeds 0.1A
(typ).
The MAX17552A implements a HICCUP-type overload
protection scheme to protect the inductor and internal
FETs under output short-circuit conditions. When the
inductor peak current exceeds 0.21A (typ) 16 consecutive times, the part enters HICCUP mode. In this mode,
the part is initially operated with hysteretic cycle-by-cycle
peak-current limit that continues for a time period equal
to twice the soft-start time. The part is then turned off
for a fixed 51ms hiccup timeout period. This sequence
of hysteretic inductor current waveforms, followed by a
hiccup timeout period, continues until the short/overload
on the output is removed. Since the inductor current is
bound between two limits, inductor current runway never
happens.
Thermal-Overload Protection
Thermal-overload protection limits the total power dissipation in the IC. When the junction temperature exceeds
+160°C, an on-chip thermal sensor shuts down the
device, turns off the internal power MOSFETs, allowing
the device to cool down. The device turns on after the
junction temperature cools by 20°C.
Applications Information
Inductor Selection
A low-loss inductor having the lowest possible DC resistance
that fits in the allotted dimensions should be selected.
Calculate the required inductance from the equation:
L =
where L is inductance in μH, V
and fSW is the switching frequency in kHz. Calculate the
peak-peak ripple current (ΔI) in the output inductor from
the equation:
1000V1
××
OUT
∆=
I
fL
where L is inductance in μH, V
is input voltage and fSW is the switching frequency in kHz.
The saturation current rating of the inductor must exceed
the maximum current-limit value (I
ration current rating should be the maximum of either
0.235A or the value from the equation:
I0.15
=+
SAT
Vt
where L is inductance in H, V
voltage and t
ON-MIN
is worst case minimum on time
(128ns).
Once the L value is known, the next step is to select the
right core material. Ferrite and powdered iron are commonly available core materials. Ferrite cores have low
core losses and are preferred for high-efficiency designs.
Powdered iron cores have more core losses and are relatively cheaper than ferrite cores.
Input Capacitor Selection
Small ceramic input capacitors are recommended for the
IC. The input capacitor reduces peak current drawn from
the power source and reduces noise and voltage ripple
on the input caused by the switching circuitry. A minimum
of 1μF, X7R-grade capacitor in a package larger than 0805
is recommended for the input capacitor of the IC to keep the
input-voltage ripple under 2% of the minimum input voltage,
and to meet the maximum ripple-current requirements.
Small ceramic X7R-grade output capacitors are recommended for the devices. The output capacitor has two
functions. It stores sufficient energy to support the output
voltage under load transient conditions and stabilizes the
device’s internal control loop. Usually the output capacitor
is sized to support a step load of 50% of the maximum
output current in the application, such that the outputvoltage deviation is less than 3%. Calculate the minimum
required output capacitance from the following equations:
Frequency
Range
(kHz)
100 to 130
160 to 230
280 to 2200
Minimum Output
Capacitance
(μF)
50
V
OUT
25
V
OUT
17
V
OUT
It should be noted that dielectric materials used in ceramic
capacitors exhibit capacitance loss due to DC bias levels and
should be appropriately derated to ensure the required
output capacitance is obtained in the application.
Soft-Start Capacitor Selection
The devices offer a 5.1ms internal soft-start when the
SS pin is left unconnected. When adjustable soft-start
time is required, connect a capacitor from SS to GND
to program the soft-start time. The minimum soft-start time
is related to the output capacitance (C
voltage(V
) by the following equation.
OUT
OUT
where tSS is in milliseconds and C
) and the output
OUT
OUT
is in µF.
OUT
Soft-start time (tSS) is related to the capacitor connected at
SS (CSS) by the following equation:
C6.25 t=×
where tSS is in milliseconds and CSS is in nanofarads.
Setting the Input Undervoltage-Lockout Level
The devices offer an adjustable input undervoltagelockout level. Set the voltage at which the device turns on
with a resistive voltage-divider connected from IN to GND
(see Figure 2). Connect the center node of the divider to
EN/UVLO.
Choose R1 to be 3.3MΩ max and then calculate R2 as
follows:
×
R1 1.25
=
R2
(V- 1.25)
INU
where V
to turn on.
If the EN/UVLO pin is driven from an external signal
source, a series resistance of minimum 1kΩ is recommended to be placed between the signal source output
and the EN/UVLO pin to reduce voltage ringing on the
line.
The output voltage can be programmed from 0.8V to 0.9V
x VIN. Set the output voltage by connecting a resistordivider from output to FB to GND (see Figure 3). Choose
R2 in the range of 25kΩ to 100kΩ and calculate R1 with
the following equation:
V
OUT
=×
R1R 21
0.8
−
Transient Protection
In applications where fast line transients or oscillations
with a slew rate in excess of 15V/µs are expected during power-up or steady-state operation, the MAX17552/
MAX17552A should be protected with a series resistor
that forms a lowpass filter with the input ceramic capacitor
(Figure 4). These transients can occur in conditions such
as hot-plugging from a low-impedance source or due to
inductive load switching and surges on the supply lines.
Power Dissipation
At a particular operating condition, the power losses that
lead to temperature rise of the device are estimated as
follows:
PP-1 - (IR)
LOSSOUTOUTDCR
where P
OUT
OUTOUTOUT
is the output power, η is the efficiency of
power conversion, and R
1
η
=×
is the DC resistance of the
DCR
2
output inductor. See the Typical Operating Characteristics
for the power-conversion efficiency or measure the efficiency to determine the total power dissipation.
The junction temperature (TJ) of the device can be
estimated at any ambient temperature (TA) from the
following equation:
TTP=+θ ×
JAJALOSS
where θJA is the junction-to-ambient thermal impedance
of the package.
Junction temperature greater than +125°C degrades
operating lifetimes.
PCB Layout Guidelines
Careful PCB layout (Figure 5) is critical to achieve clean
and stable operation. The switching power stage requires
particular attention. Follow these guidelines for good PCB
layout:
● Place the input ceramic capacitor as close as possible
to VIN and GND pins
● Minimize the area formed by the LX pin and inductor
connection to reduce the radiated EMI
● Ensure that all feedback connections are short and
direct
● Route high-speed switching node (LX) away from the
signal pins
For a sample PCB layout that ensures the first-pass
success, refer to the MAX17552/MAX17552A evaluation
kit data sheet.
58/18Updated the Mode Selection (MODE) section. 14
REVISION
DATE
DESCRIPTION
Included small solution-size TOCs in Typical Operating Characteristics section
and updated Typical Application Circuit diagrams
Updated Features and Benets, Mode Selection (MODE), Setting the Input
Undervoltage-Lockout Level, and Power Dissipation sections. Updated the
Electrical Characteristics table global characteristics. Inserted new Note 1 and updated Absolute Maximum Ratings, and added TOC50 and TOC51.
PAGES
CHANGED
2, 6–10,
19, 20
1, 3–5,
11, 14,
17–18
For pricing, delivery, and ordering information, please visit Maxim Integrated’s online storefront at https://www.maximintegrated.com/en/storefront/storefront.html.
Maxim Integrated cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim Integrated product. No circuit patent licenses
are implied. Maxim Integrated reserves the right to change the circuitry and specications without notice at any time. The parametric values (min and max limits)
shown in the Electrical Characteristics table are guaranteed. Other parametric values quoted in this data sheet are provided for guidance.
Maxim Integrated and the Maxim Integrated logo are trademarks of Maxim Integrated Products, Inc.