Datasheet MAX1478C-D, MAX1478AAE Datasheet (Maxim)

General Description

The MAX1478 highly integrated, analog sensor signal
processor is optimized for piezoresistive sensor calibra­tion and compensation without any external compo­nents. It includes a programmable current source for
sensor excitation, a 3-bit programmable-gain amplifier
(PGA), a 128-bit internal EEPROM, and four 12-bit digi­tal-to-analog converters (DACs). Achieving a total error
factor within 1% of the sensor’s repeatability errors, the
MAX1478 compensates offset, offset temperature coeffi­cient, full-span output (FSO), FSO temperature coeffi­cient (FSO TC), and FSO nonlinearity of silicon
piezoresistive sensors.

The MAX1478 calibrates and compensates first-order
temperature errors by adjusting the offset and span of
the input signal via DACs, thereby eliminating the quan­tization noise associated with digital signal path solu­tions. Built-in testability features on the MAX1478 result
in the integration of three traditional sensor-manufactur­ing operations into one automated process:

• Pretest: Data acquisition of sensor performance

under the control of a host test computer.

• Calibration and compensation: Computation and

storage (in an internal EEPROM) of calibration and
compensation coefficients computed by the test
computer and downloaded to the MAX1478.

• Final test operation: Verification of transducer cali-

bration and compensation without removal from the
pretest socket.

Although optimized for use with piezoresistive sensors,
the MAX1478 may also be used with other resistive
sensors (i.e., accelerometers and strain gauges) with
some additional external components.

______________________Customization

For high-volume applications, Maxim can customize the
MAX1478 for unique requirements. With a dedicated
cell library consisting of more than 90 sensor-specific
functional blocks, Maxim can quickly provide cus­tomized MAX1478 solutions.

________________________Applications

Piezoresistive Pressure and Acceleration
Transducers and Transmitters
Manifold Absolute Pressure (MAP) Sensors
Automotive Systems
Hydraulic Systems
Industrial Pressure Sensors
Strain-Gauge Sensors
Industrial Temperature Sensors

Features

♦ Medium Accuracy (±1%), Single-Chip Sensor

Signal Conditioning

♦ Rail-to-Rail®Output

♦ Sensor Errors Trimmed Using Correction

Coefficients Stored in Internal EEPROM—
Eliminates Laser Trimming and Potentiometers

♦ Compensates Offset, Offset TC, FSO, FSO TC,

and FSO Linearity

♦ Programmable Current Source (0.1mA to 2.0mA)

for Sensor Excitation

♦ Fast Signal-Path Settling Time (<1ms)

♦ +5V Single Supply

♦ Accepts Sensor Outputs from +10mV/V to

+40mV/V

♦ Fully Analog Signal Path

Pilot Production System

To simplify your pressure sensor design, Maxim has
developed a fully automated pilot production system
that will smooth the difficult transition from prototype to
production. Details appear at the end of this data sheet.

MAX1478

1% Accurate, Digitally Trimmed,

Rail-to-Rail Sensor Signal Conditioner

________________________________________________________________ Maxim Integrated Products 1

19-1538; Rev 0; 9/99

*Dice are tested at TA= +25°C, DC parameters only.

Functional Diagram appears at end of data sheet.

Pin Configuration

Ordering Information

For free samples & the latest literature: http://www.maxim-ic.com, or phone [phone].
For small orders, phone [phone].

PART

MAX1478C/D

MAX1478AAE -40°C to +125°C

0°C to +70°C

TEMP. RANGE PIN-PACKAGE

Dice*

16 SSOP

Rail-to-Rail is a registered trademark of Nippon Motorola, Ltd.

EVALUATION KIT

AVAILABLE

TOP VIEW

1

SCLK I.C.

CS

2

I.C.

3

MAX1478

4

TEMP

FSOTC

5

DIO

6

WE

7

V

8

SS

SSOP

16

15

14

13

12

11

10

9

V

DD

INM

BDRIVE

INP

I.C.

OUT

ISRC

MAX1478

1% Accurate, Digitally Trimmed,
Rail-to-Rail Sensor Signal Conditioner

2 _______________________________________________________________________________________

ABSOLUTE MAXIMUM RATINGS

ELECTRICAL CHARACTERISTICS

(VDD= +5V, VSS= 0, TA= +25°C, unless otherwise noted.)

Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.

Supply Voltage, VDDto VSS......................................-0.3V to +6V

All Other Pins ...................................(V

SS

- 0.3V) to (VDD+ 0.3V)

Short-Circuit Duration, FSOTC, OUT, BDRIVE ...........Continuous

Continuous Power Dissipation (T

A

= +70°C)

16-Pin SSOP (derate 8.00mW/°C above +70°C) ..........640mW

Operating Temperature Range

MAX1478AAE .................................................-40°C to +125°C

Storage Temperature Range .............................-65°C to +150°C

Lead Temperature (soldering, 10sec) .............................+300°C

PARAMETER

SYMBOL MIN TYP MAX UNITS

Amplifier Gain Nonlinearity 0.01 %V

DD

Input-Referred Offset Tempco ±0.5 µV/°C

Input Impedance R

IN

1 MΩ

Output Step Response 1 ms

Common-Mode Rejection Ratio CMRR 90 dB

Input-Referred Adjustable Offset
Range

±150 mV

Supply Voltage V

DD

4.5 5.0 5.5 V

Supply Current I

DD

36mA

Input-Referred Adjustable FSO
Range

10 to 40 mV/V

Differential-Signal Gain Range 41 to 230 V/V

Minimum Differential Signal Gain 36 41 45 V/V

Differential-Signal Gain Tempco ±50 ppm/°C

Output Current Range

-0.45 0.45

(sink) (source)

mA

Output Noise 500 µV

RMS

CONDITIONS

(Note 5)

(Notes 2, 3)

63% of final value

Selectable in eight steps

TA= T

MIN

to T

MAX

From VSSto V

DD

At minimum gain (Note 4)

V

OUT

= (VSS+ 0.25V) to (VDD- 0.25V)

DC to 10Hz (gain = 41, source
impedance = 5kΩ)

(Note 1)

Output Voltage Swing VSS+ 0.05 V

DD -

0.05 VNo load

GENERAL CHARACTERISTICS

ANALOG INPUT (PGA)

ANALOG OUTPUT (PGA)

ELECTRICAL CHARACTERISTICS (continued)

(VDD= +5V, VSS= 0, TA= +25°C, unless otherwise noted.)

Note 1: Excludes the sensor or load current.
Note 2: All electronics temperature errors are compensated together with sensor errors.
Note 3: The sensor and the MAX1478 must always be at the same temperature during calibration and use.
Note 4: This is the maximum allowable sensor offset.
Note 5: This is the sensor’s sensitivity normalized to its drive voltage, assuming a desired full-span output of 4V and a bridge

voltage of 2.5V.

Note 6: Bit weight is ratiometric to V

DD

.

MAX1478

1% Accurate, Digitally Trimmed,

Rail-to-Rail Sensor Signal Conditioner

_______________________________________________________________________________________ 3

Typically 4600ppm/°C tempco

V

FSOTC

= 2.5V

No load

Input referred, VDD= 5V (Note 6)

CONDITIONS

kΩ100R

TEMP

Temperature-Dependent
Resistor

kΩ75R

FTC

FSO Trim Resistor

kΩ75R

ISRC

Current-Source Reference
Resistor

VV

SS

+ 1.3 VDD- 1.3V

BDRIVE

Bridge Voltage Swing

mA0.1 0.5 2.0I

BDRIVE

Bridge Current Range

µA-20 20Current Drive

VV

SS

+ 0.3 VDD- 1.3Output Voltage Swing

Bits3DAC Resolution

mV/bit9DAC Bit Weight

UNITSMIN TYP MAXSYMBOLPARAMETER

LSB±1.5DNLDifferential Nonlinearity

Bits12DAC Resolution

VV

SS

+ 1.3 VDD- 1.3V

ISRC

Reference Input Voltage Range
(ISRC)

DAC reference = V

BDRIVE

= 2.5V

DAC reference = VDD= 5.0V

mV/bit1.4

∆V

OUT

∆Code

Offset TC DAC Bit Weight

mV/bit2.8

∆V

OUT

∆Code

Offset DAC Bit Weight

DAC reference = V

BDRIVE

= 2.5V

DAC reference = VDD= 5.0V

mV/bit0.6

∆V

FSOTC

∆Code

FSO TC DAC Bit Weight

mV/bit1.22

∆V

ISRC

∆Code

FSO DAC Bit Weight

CURRENT SOURCE

DIGITAL-TO-ANALOG CONVERTERS

IRO DAC

FSOTC BUFFER

INTERNAL RESISTORS

_______________Detailed Description

The MAX1478 provides an analog amplification path for
the sensor signal. Calibration and temperature com­pensation are achieved by varying the offset and gain
of a programmable-gain amplifier (PGA) and by varying
the sensor bridge current. The PGA uses a switched­capacitor CMOS technology, with an input-referred
coarse offset trimming range of approximately ±63mV
(9mV steps). An additional output-referred fine offset
trim is provided by the Offset DAC (approximately

2.8mV steps). The PGA provides eight gain values from
+41V/V to +230V/V. The bridge current source is pro­grammable from 0.1mA to 2mA.

The MAX1478 uses four 12-bit DACs and one 3-bit
DAC, with calibration coefficients stored by the user in

an internal 128-bit EEPROM. This memory contains the
following information as 12-bit-wide words:

• Configuration register

• Offset calibration coefficient

• Offset temperature error-compensation coefficient

• FSO (full-span output) calibration coefficient

• FSO temperature error-compensation coefficient

• 24 user-defined bits for customer programming of

manufacturing data (e.g., serial number and date)

Figure 1 shows a typical pressure-sensor output and
defines the offset, full-scale, and FSO values as a func­tion of voltage.

MAX1478

1% Accurate, Digitally Trimmed,
Rail-to-Rail Sensor Signal Conditioner

4 _______________________________________________________________________________________

Pin Description

Positive Power-Supply Input. Connect a 0.1µF capacitor from VDDto V

SS.

V

DD

15

Current-Source Reference. An internal 75kΩ resistor (R

ISRC

) connects ISRC to VSS(see Functional

Diagram). Optionally, external resistors can be used in place of or in parallel with R

FTC

and R

ISRC

.

ISRC9

PGA Output VoltageOUT10
Positive Sensor Input. Input impedance >1MΩ. Rail-to-rail input range.INP12

Sensor Excitation Current Output. This current source drives the bridge.BDRIVE13
Negative Sensor Input. Input impedance >1MΩ. Rail-to-rail input range.INM14

Buffered FSOTC DAC Output. An internal 75kΩ resistor (R

FTC

) connects FSOTC to ISRC (see Functional

Diagram). Optionally, external resistors can be used in place of or in parallel with R

FTC

and R

ISRC

.

FSOTC5

Data Input/Output. Used only during programming/testing. Internally pulled to VSSwith a 1MΩ (typical)
resistor. High impedance when CS is low.

DIO6

Dual-Function Input Pin. Used to enable EEPROM erase/write operations. Also used to set the DAC refresh­rate mode. Internally pulled to V

DD

with a 1MΩ (typical) resistor. See the Chip-Select (CS) and Write-Enable

(WE) section.

WE7

Negative Power-Supply InputV

SS

8

Temperature Sensor Output. An internal temperature sensor (a 100kΩ, 4600ppm/°C TC resistor) that can
provide a temperature-dependent voltage.

TEMP4

Internally Connected. Leave unconnected.I.C.

3, 11,

16

PIN

Chip-Select Input. The MAX1478 is selected when this pin is high. When low, OUT and DIO become high
impedance. Internally pulled to V

DD

with a 1MΩ (typical) resistor. Leave unconnected for normal operation.

CS2

Data Clock Input. Used only during programming/testing. Internally pulled to VSSwith a 1MΩ (typical) resis­tor. Data is clocked in on the rising edge of the clock. The maximum SCLK frequency is 10kHz.

SCLK1

FUNCTIONNAME

FSO TC Compensation

Silicon piezoresistive transducers (PRTs) exhibit a large
positive input resistance tempco (TCR) so that, while
under constant current excitation, the bridge voltage
(V

BDRIVE

) increases with temperature. This depen-

dence of V

BDRIVE

on the sensor temperature can be
used to compensate the sensor temperature errors.
PRTs also have a large negative full-span output sensi­tivity tempco (TCS) so that, with constant voltage exci­tation, FSO will decrease with temperature, causing a
full-span output temperature coefficient (FSO TC) error.
However, if the bridge voltage can be made to increase
with temperature at the same rate that TCS decreases
with temperature, the FSO will remain constant.

FSO TC compensation is accomplished by resistor
R

FTC

and the FSOTC DAC, which modulate the excita­tion reference current at ISRC as a function of tempera­ture (Figure 3). FSO DAC sets V

ISRC

and remains
constant with temperature, while the voltage at FSOTC
varies with temperature. FSOTC is the buffered output
of the FSOTC DAC. The reference DAC voltage is
V

BDRIVE

, which is temperature dependent. The FSOTC
DAC alters the tempco of the current source. When the
tempco of the bridge voltage is equal in magnitude and
opposite in polarity to the TCS, the FSO TC errors are
compensated and FSO will be constant with tempera­ture.

Offset TC Compensation

Compensating offset TC errors involves first measuring
the uncompensated offset TC error, then determining
the percentage of the temperature-dependent voltage
V

BDRIVE

that must be added to the output summing

junction to correct the error. Use the Offset TC DAC to
adjust the amount of BDRIVE voltage that is added to
the output summing junction (Figure 2).

Analog Signal Path

The fully differential analog signal path consists of four
stages:

• Front-end summing junction for coarse offset correction

• 3-bit PGA with eight selectable gains ranging from

41 through 230

• Three-input-channel summing junction

• Differential to single-ended output buffer (Figure 2)

Coarse Offset Correction

The sensor output is first fed into a differential summing
junction (INM (negative input) and INP (positive input))
with a CMRR >90dB, an input impedance of approxi­mately 1MΩ, and a common-mode input voltage range
from VSSto VDD. At this summing junction, a coarse off­set-correction voltage is added, and the resultant volt­age is fed into the PGA. The 3-bit (plus sign)
input-referred Offset DAC (IRO DAC) generates the
coarse offset-correction voltage. The DAC voltage ref­erence is 1.25% of V

DD

; thus, a VDDof 5V results in a
front-end offset-correction voltage ranging from -63mV
to +63mV, in 9mV steps (Table 1). To add an offset to
the input signal, set the IRO sign bit high; to subtract an
offset from the input signal, set the IRO sign bit low.
The IRO DAC bits (C2, C1, C0, and IRO sign bit) are
programmed in the configuration register (see Internal
EEPROM section).

MAX1478

1% Accurate, Digitally Trimmed,

Rail-to-Rail Sensor Signal Conditioner

_______________________________________________________________________________________ 5

Figure 1. Typical Pressure-Sensor Output

Figure 2. Signal-Path Block Diagram

4.5

FULL-SPAN OUTPUT (FSO)

VOLTAGE (V)

0.5

OFFSET

P

MIN

P

MAX

PRESSURE

FULL SCALE (FS)

1.25% V

DD

IRO

DAC

INP

INM

BDRIVE

A2

V

A1 A0

PGA

DD

OFFTC

DAC

OFFSET

DAC

A = 2.3

A = 2.3

SOTC

±

OUT

ΣΣ

A = 1

±

SOFF

MAX1478

Table 1. Input-Referred Offset DAC
Correction Values

Programmable-Gain Amplifier

The PGA, which is used to set the coarse FSO, uses a
switched-capacitor CMOS technology and contains
eight selectable gain levels from 41 to 230, in incre­ments of 27 (Table 2). The output of the PGA is fed to
the output summing junction. The three PGA gain bits
A2, A1, and A0 are stored in the configuration register.

Output Summing Junction

The third stage in the analog signal path consists of a
summing junction for the PGA output, offset correction,
and offset TC correction. Both the offset and the offset
TC correction voltages are multiplied by a factor of 2.3
before being fed into the summing junction, increasing
the offset and offset TC correction range. The offset
sign bit and offset TC sign bit are stored in the configu­ration register. The offset sign bit determines if the off­set correction voltage is added to (sign bit is high) or
subtracted from (sign bit is low) the PGA output.
Negative offset TC errors require a logic high for the
offset TC sign bit. Alternately, positive offset TC errors
dictate a logic low for the offset TC sign bit. The output
of the summing junction is fed to the output buffer.

Output Buffer

OUT can drive 0.1µF of capacitance. The output is cur­rent limited and can be shorted to either V

DD

or V

SS

indefinitely. OUT can both source and sink current. A
load can be driven to either rail. The output can swing

very close to either supply while maintaining its
accuracy and stability. Maxim recommends putting a

0.1µF capacitor on the OUT pin in noisy environments.

Bridge Drive

Fine FSO correction is accomplished by varying the
sensor excitation current with the 12-bit FSO DAC
(Figure 3). Sensor bridge excitation is performed by a
programmable current source capable of delivering up
to 2mA. The reference current at ISRC is established by
resistor R

ISRC

and by the voltage at node ISRC (con­trolled by the FSO DAC). The reference current flowing
through this pin is multiplied by a current mirror (current
mirror gain AA ≅ 14) and then made available at
BDRIVE for sensor excitation. Modulation of this current
with respect to temperature can be used to correct
FSOTC errors, while modulation with respect to the out­put voltage (V

OUT

) can be used to correct FSO linearity

errors.

Digital-to-Analog Converters

The four 12-bit, sigma-delta DACs typically settle in
less than 100ms. The four DACs have a corresponding
memory register in EEPROM for storage of correction
coefficients.

Use the FSO DAC for fine FSO adjustments. The FSO
DAC takes its reference from VDDand controls V

ISRC

which, in conjunction with R

ISRC

, sets the baseline sen­sor excitation current. The Offset DAC also takes its ref­erence from VDDand provides a 1.22mV resolution with

1% Accurate, Digitally Trimmed,
Rail-to-Rail Sensor Signal Conditioner

6 _______________________________________________________________________________________

+7 1 1 1

IRO DAC

1

OFFSET

CORREC-

TION

% of V

DD

(%)

+1.25

OFFSET

CORREC-

TION AT

V

DD

= 5V

(mV)

+63

SIGN C1C2 C0VALUE

+6 1 1 1 0 +1.08 +54

+5 1 1 0 1 +0.90 +45

+4 1 1 0 0 +0.72 +36

+3 1 0 1 1 +0.54 +27

+2 1 0 1 0 +0.36 +18

+1 1 0 0 1 +0.18 +9

+0 1 0 0 0

0

0

-0 0 0 0 0

-1 0 0 0 1 -0.18 -9

-2 0 0 1 0 -0.36 -18

-3 0 0 1 1 -0.54 -27

-4 0 1 0 0 -0.72 -36

-5 0 1 0 1 -0.90 -45

-6 0 1 1 0 -1.08 -54

-7 0 1 1 1 -1.25 -63

A1

0 0 0

A2 A0

PGA

VALUE

0

PGA

GAIN

(V/V)

41

OUTPUT­REFERRED IRO
DAC STEP SIZE

(V

DD

= 5V) (V)

0.369

1 0 0 1 68 0.612

2 0 1 0 95 0.855

3 0 1 1 122 1.098

4 1 0 0 149 1.341

5 1 0 1 176 1.584

6 1 1 0 203 1.827

7 1 1 1 230 2.070

Table 2. PGA Gain Settings and IRO DAC
Step Size

0

0

a VDDof 5V. The output of the Offset DAC is fed into
the output summing junction where it is gained by
approximately 2.3, which increases the resulting out­put-referred offset correction resolution to 2.8mV.

Both the Offset TC and FSOTC DACs take their refer­ence from BDRIVE, a temperature-dependent voltage.
A nominal V

BDRIVE

of 2.5V results in a step size of

0.6mV. The Offset TC DAC output is fed into the output
summing junction where it is multiplied by approximate­ly 2.3, thereby increasing the Offset TC correction
range. The buffered FSOTC DAC output is available at
FSOTC and is connected to ISRC through R

FTC

to cor-

rect FSO TC errors.

Internal Resistors

The MAX1478 contains three internal resistors (R

ISRC

,

R

FTC

, and R

TEMP

) optimized for common silicon PRTs.

R

ISRC

(in conjunction with the FSO DAC) programs the

nominal sensor excitation current. R

FTC

(in conjunction
with the FSOTC DAC) compensates the FSO TC errors.
Both R

ISRC

and R

FTC

have a nominal value of 75kΩ. If

external resistors are used, R

ISRC

and R

FTC

can be dis­abled by resetting the appropriate bit (address 07h
reset to zero) in the configuration register (Table 3).

R

TEMP

is a high-tempco resistor with a TC of

+4600ppm/°C and a nominal resistance of 100kΩ at
+25°C. This resistor can be used with certain sensor
types that require an external temperature sensor.

Internal EEPROM

The MAX1478 has a 128-bit internal EEPROM arranged
as eight 16-bit words. The four uppermost bits for each
register are reserved. The internal EEPROM is used to
store the following (also shown in the memory map in
Table 4):

MAX1478

1% Accurate, Digitally Trimmed,

Rail-to-Rail Sensor Signal Conditioner

_______________________________________________________________________________________ 7

Figure 3. Bridge Excitation Circuit

Table 3. Configuration Register

Input-Referred Offset0Ah

Input-Referred Offset (LSB)

Input-Referred Offset (IRO) Sign Bit

0Bh

08h

Input-Referred Offset (MSB)09h

Reserved “0”06h

Internal Resistor (R

FTC

and R

ISRC

)

Selection

PGA Gain (LSB), A0

07h

04h

Reserved “0”05h

PGA Gain (MSB), A2

EEPROM

ADDRESS (hex)

02h

DESCRIPTION

PGA Gain, A1

Offset TC Sign Bit, SOTC (+ = 1)

03h

00h

Offset Sign Bit, SOFF (+ = 1)01h

V

DD

FSO
DAC

ISRC

ISRC

AA ≈ 14I

I

SRC

I = I

R

FTC

R

V

DD

= I

ISRC

BDRIVE

BDRIVE

EXTERNAL

SENSOR

FSOTC

DAC

FSOTC

MAX1478

• Configuration register (Table 3)

• 12-bit calibration coefficients for the Offset and FSO

DACs

• 12-bit compensation coefficients for the Offset TC

and FSOTC DACs

• Two general-purpose registers available to the user

for storing process information such as serial num­ber, batch date, and check sums

Program the EEPROM 1 bit at a time. The bits have
addresses from 0 to 127 (7F hex).

Configuration Register

The configuration register (Table 3) determines the
PGA gain, the polarity of the offset and offset TC coeffi­cients, and the coarse offset correction (IRO DAC). It
also enables/disables internal resistors (R

FTC

and

R

ISRC

).

DAC Registers

The Offset, Offset TC, FSO, and FSOTC registers store
the coefficients used by their respective calibration/
compensation DACs.

1% Accurate, Digitally Trimmed,
Rail-to-Rail Sensor Signal Conditioner

8 _______________________________________________________________________________________

Table 4. EEPROM Memory Map

EE Address
Contents

EE Address
Contents

EE Address
Contents

EE Address
Contents

EE Address
Contents

Reserved*

EE Address
Contents

EE Address
Contents

0E

0

0C

0

0F 0D

0

0A 080B 09 06 0407 05 02

1

00

Configuration

03 01

1E

0

1C

1

1F 1D

0

1A 181B 19 16 1417 15 12

1

10

MSB Offset LSB

13 11

2E

0

2C

0

2F 2D

1

2A 282B 29 26 2427 25 22

1

20

MSB Offset TC LSB

23 21

3E

0

3C

1

3F 3D

1

3A 383B 39 36 3437 35 32

1

30

MSB FSO LSB

33 31

4E

1

4C

0

4F 4D

0

4A 484B 49 46 4447 45 42

1

40

MSB FSOTC LSB

43 41

5E

0

5C

0

5F 5D

0

5A 585B 59 56 5457 55 52

0

50

0

53 51

6E

0

6C

0

6F 6D

0

6A 686B 69 66 6467 65 62

0

60

User-Defined Bits

63 61

7E

0

7C

0

7F 7D

0

7A 787B 79 76 7477 75 72

0

70

User-Defined Bits

73 71

Note: The MAX1478 processes the Reserved Bits in the EEPROM. If these bits are not properly programmed, the configuration

and DAC registers will not be updated correctly.

*The contents of the Reserved EE Address 50–5F must all be reset to zero.

= Reserved Bits

00000000000

Detailed Description of the Digital Lines

Chip Select (CS) and Write Enable (WE)

CS is used to enable OUT, control serial communica­tion, and force an update of the configuration and DAC
registers.

• A low on CS disables serial communication.

• A transition from low to high on CS forces an update

of the configuration and DAC registers from the
EEPROM when the U bit is zero.

• A transition from high to low on CS terminates pro-

gramming mode.

• A logic high on CS enables OUT and serial commu-

nication (see Communication Protocol section).

WE controls the refresh rate for the internal configura­tion and DAC registers from the EEPROM and enables
the erase/write operations. If communication has been
initiated (see Communication Protocol section), internal
register refresh is disabled.

• A low on WE disables the erase/write operations and

also disables register refreshing from the EEPROM.

• A high on WE selects a refresh rate of approximately

400 times per second and enables EEPROM
erase/write operations.

• It is recommended that WE be connected to V

SS

after the MAX1478 EEPROM has been programmed.

Serial Clock

Serial Clock (SCLK) must be driven externally. It is
used to input commands to the MAX1478 and read
EEPROM contents. Input data on DIO is latched on the
rising edge of SCLK. Noise on SCLK may disrupt com­munication. In noisy environments, place a capacitor
(0.01µF) between SCLK and VSS.

Data Input/Output

The data input/output (DIO) line is an input/output pin
used to issue commands to the MAX1478 (input mode)
or read the EEPROM contents (output mode).

In input mode (the default mode), data on DIO is
latched on each rising edge of SCLK. Therefore, data
on DIO must be stable at the rising edge of SCLK and
should transition on the falling edge of SCLK.

DIO will switch to output mode after receiving a READ
EEPROM command, and will return the data bit
addressed by the digital value in the READ EEPROM
command. After a low-to-high transition on CS, DIO
returns to input mode and is ready to accept more
commands.

Communication Protocol

To initiate communication, the first 6 bits on DIO after
CS transitions from low to high must be 1010U0
(defined as the INIT SEQUENCE). The MAX1478 will
then begin accepting 16-bit control words (Figure 4).

If the INIT SEQUENCE is not detected, all subsequent
data on DIO is ignored until CS again transitions from
low to high and the correct INIT SEQUENCE is received.

The U bit of the INIT SEQUENCE controls the updating
of the DACs and configuration register from the internal
EEPROM. If this bit is low (U = 0), all four internal DACs
and the configuration register will be updated from the
EEPROM on the next rising edge of CS (this is also the
default on power-up). If the U bit is high, the DACs and
configuration register will not be updated from the inter­nal EEPROM; they will retain their current value on any
subsequent CS rising edge. The MAX1478 continues to
accept control words until CS is brought low.

MAX1478

1% Accurate, Digitally Trimmed,

Rail-to-Rail Sensor Signal Conditioner

_______________________________________________________________________________________ 9

Figure 4. Communication Sequence

CS

t

MIN

200µs

SCLK

DIO

X

1

0

1 D0D0D1D1CM3

0U0

BEGIN

PROGRAMMING

SEQUENCE

16 CLK

CYCLES

CONTROL

WORD

16 CLK

CYCLES

CONTROL

WORD

n x 16 CLK

CYCLES

CM3

CONTROL

WORDS

MAX1478

Control Words

After receiving the INIT SEQUENCE on DIO, the MAX1478
begins latching in 16-bit control words, LSB first (Figure 5).
The first 12 bits (D0–D11) represent the data field. The
last 4 bits of the control word (the MSBs, CM0–CM3)
are the command field. The MAX1478 supports the
commands listed in Table 5.

ERASE EEPROM Command

When an ERASE EEPROM command is issued, all of
the memory locations in the EEPROM are reset to a
logic 0. The data field of the 16-bit word is ignored.

Important: An internal charge pump develops voltages
greater than 20V for EEPROM programming operations.
The EEPROM control logic requires 50ms to erase the
EEPROM. After sending a WRITE or ERASE command,
failure to wait 50ms before issuing another command
may result in data being accidentally written to the
EEPROM. The maximum number of ERASE EEPROM
cycles should not exceed 100.

BEGIN EEPROM WRITE Command

The BEGIN EEPROM WRITE command stores a logic
high at the memory location specified by the lower 7
bits of the data field (A0–A6). The higher bits of the
data field (A7–A11) are ignored (Figure 6). Note that to
write to the internal EEPROM, WE and CS must be high.

1% Accurate, Digitally Trimmed,
Rail-to-Rail Sensor Signal Conditioner

10 ______________________________________________________________________________________

Figure 5. Control-Word Timing Diagram

Figure 6. Timing Diagram for WRITE EEPROM Operation

Table 5. MAX1478 Commands

FUNCTION

ERASE EEPROM

CM20CM1

01h

HEX

CODE

CM3

0

CM0

1

BEGIN EEPROM WRITE at
Address

0 12h 0 0

READ EEPROM at Address 0 13h 0 1

Maxim Reserved 1 04h 0 0

END EEPROM WRITE at
Address

1 05h 0 1

WRITE Data to Configuration
Register

0 08h 1 0

WRITE Offset DAC 0 09h 1 1

WRITE Offset TC DAC 0 1Ah 1 0

WRITE FSO DAC 0 1Bh 1 1

WRITE FSOTC DAC 1 0Ch 1 0

No Operation 0 00h 0 0

Load Register

1
1
1
1
1

1
1
0
1
1

6h,

7h,
Dh,
Eh,

Fh

0
0
1
1
1

0
1
1
0
1

SCLK

LSB MSB MSBLSB

D0D3D1D4D2

DIO

LSB MSB MSBLSB

CS

WE

t

MIN

200µs

SCLK

DIO

X

1

0

1

INIT SEQUENCE

DATA

D6D9D7

D5

16-BIT CONFIGURATION WORD

16 CLK

CYCLES

A0 D0A0A1 D1A1CM3 CM3 CM30U0

BEGIN

EEPROM

WRITE

D10D8D11

T

WRITE

COMMAND

CM0 CM2 CM2 CM3

16 CLK

CYCLES

END

EEPROM

WRITE

t

WAIT

n x 16 CLK

CYCLES

n

COMMAND

WORDS

In addition, the EEPROM should only be written to at
T

A

= +25°C and VDD= 5V.

Writing to the internal EEPROM is a time-consuming
process and should only be required once. All calibra­tion/compensation coefficients are determined by writ­ing directly to the DAC and configuration registers. Use
the following procedure to write these calibration/com­pensation coefficients to the EEPROM:

1) Issue an ERASE EEPROM command.

2) Wait 50ms (t

WRITE

).

3) Issue an END EEPROM WRITE command at add­ress 00h.

4) Wait 1ms (t

WAIT

).

5) Issue a BEGIN EEPROM WRITE command
(Figure 7) at the address of the bit to be set.

6) Wait 50ms.

7) Issue an END EEPROM WRITE command (Figure 7)
using the same address as in Step 5.

8) Wait 1ms.

9) Return to Step 5 until all necessary bits have been
set.

10) Read EEPROM to verify that the correct calibra­tion/compensation coefficients have been stored.

READ EEPROM Command

The READ EEPROM command returns the bit stored at
the memory location addressed by the lower 7 bits of
the data field (A0–A6). The higher bits of the data field
(A7–A11) are ignored. Note that after a read command
has been issued, the DIO lines become an output and
the state of the addressed EEPROM location will be
available on DIO 200µs (t

READ

) after the falling edge of
the 16th SCLK cycle (Figure 8). After issuing the READ
EEPROM command, DIO returns to input mode on the
falling edge of CS. Reading the entire EEPROM
requires the READ EEPROM command be issued 128
times.

MAX1478

1% Accurate, Digitally Trimmed,

Rail-to-Rail Sensor Signal Conditioner

______________________________________________________________________________________ 11

Figure 7. Begin WRITE EEPROM and End WRITE EEPROM Timing Diagrams

Figure 8. READ EEPROM Timing Diagram

SCLK

LSB MSB MSB

DIO

A0 A1 A2 A3 A4 A5 A6 0 0 0 0 0

16-BIT COMMAND WORD – BEGIN EEPROM WRITE AT ADDRESS COMMAND

LSB MSB

SCLK

DATA

COMMAND

LSB

0

0

1

0

LSB MSB MSBLSB

DIO

A0 A1 A2 A3 A4 A5 A6 0 0 0 0 0

16-BIT COMMAND WORD – END EEPROM WRITE AT ADDRESS COMMAND

LSB MSB

CS

t

= 200µs

MIN

SCLK

DIO

INIT SEQUENCE

A0X1010U0A1A2A3 A4 A5 A6 0 0 0 0 0 0 0 X XEE DATA

DATA

16 CLOCK CYCLES

READ EEPROM AT ADDRESS COMMAND

DIO IS AN INPUT PIN

COMMAND

1

1

11

00

t

READ

DIO IS AN

OUTPUT PIN

MAX1478

Writing to the Configuration and DAC Registers

When writing to the configuration register or directly to
the internal 12-bit DACs, the data field (D0–D11) con­tains the data to be written to the respective register.
Note that all four DACs and the configuration register
can be updated without toggling the CS line. Every
register write command must be followed by a LOAD
REGISTER command.

__________Applications Information

Power-Up

At power-up, the following occurs:

1) The DAC and configuration registers are reset to
zero.

2) CS transitions from low to high after power-up (an
internal pull-up resistor ensures that this happens if
CS is left unconnected), and the EEPROM contents
are read and processed.

3) The DAC and configuration registers are updated
either once or approximately 400 times per second
(as determined by the state of WE).

4) The MAX1478 begins accepting commands in a ser­ial format on DIO immediately after receiving the INIT
SEQUENCE.

The MAX1478 is shipped with all memory locations in
the internal EEPROM uninitialized. Therefore, the
MAX1478 must be programmed for proper operation.

Compensation Procedure

The following compensation procedure was used to
obtain the results shown in Figure 9 and Table 8. It
assumes a pressure transducer with a +5V supply and
an output voltage that is ratiometric to the supply volt­age. The desired offset voltage (V

OUT

at P

MIN

) is 0.5V,

and the desired FSO voltage (V

OUT(P

MAX

)

- V

OUT(P

MIN

)

)

is 4V; thus, the full-scale output voltage (V

OUT

at P

MAX

)
will be 4.5V (see Figure 1). The procedure requires a
minimum of two test pressures (e.g., zero and full
scale) at two arbitrary test temperatures, T1and T2.
Ideally, T1and T2are the two points where we wish to
perform best linear fit compensation. The following out­lines a typical compensation procedure:

1) Perform Coefficient Initialization

2) Perform FSO Calibration

3) Perform FSOTC Compensation

4) Perform Offset TC Compensation

5) Perform Offset Calibration

Coefficient Initialization

Select the resistor values and the PGA gain to prevent
overload of the PGA and bridge current source. These
values depend on sensor behavior and require some
sensor characterization data, which may be available
from the sensor manufacturer. If not, the data can be
generated by performing a two-temperature, two-pres­sure sensor evaluation. The required sensor information
is shown in Table 6 and can be used to obtain the val­ues for the parameters listed in Table 7.

Table 6. Sensor Information for Typical
PRT

Selecting R

ISRC

When using an external resistor, use the equation
below to determine the value of R

ISRC

, and place the
resistor between ISRC and VSS. Since the 12-bit FSO
DAC provides considerable dynamic range, the R

ISRC

value need not be exact. Generally, any resistor value
within ±50% of the calculated value is acceptable. If
both the internal resistors R

ISRC

and R

FTC

are used, set
the IRS bit at EEPROM address bit 7 high. Otherwise,
set IRS low and connect external resistors as shown in
Figure 10.

where Rb(T) is the sensor input impedance at tempera­ture T1 (+25°C in this example).

1% Accurate, Digitally Trimmed,
Rail-to-Rail Sensor Signal Conditioner

12 ______________________________________________________________________________________

5kΩ at +25°C

TYPICAL

VALUES

Rb(T)

2600ppm/°C

Bridge Impedance

TCR

SENSOR

DESCRIPTION

Bridge Impedance
Tempco

PARAMETER

+1.5mV/V per
PSI at +25°C

S(T)

-2100ppm/°C

Sensitivity

TCS Sensitivity Tempco

+12mV/V at
+25°C

O(T)

-1000ppm/°C
of FSO

Offset

OTC Offset Tempco

0.1% FSO,
BSLF

S(p)

0 psi

Sensitivity Linearity Error
as % FSO, BSLF
(Best Straight-Line Fit)

P

MIN

Minimum Input Pressure

10 psiP

MAX

Maximum Input Pressure

R Rb(T

ISRC

≈

⋅

)

14 1

≈=

kk

⋅

14 5 70ΩΩ

Selecting R

FTC

When using an external resistor, use the equation
below to determine the value for R

FTC

, and place the
resistor between ISRC and FSOTC. Since the 12-bit
FSOTC DAC provides considerable dynamic range, the
R

FTC

value need not be exact. Generally, any resistor
value within ±50% of the calculated value is accept­able.

This approximation works best for bulk, micromachined,
silicon PRTs. Negative values for R

FTC

indicate uncon­ventional sensor behavior that cannot be compensated
by the MAX1478 without additional external circuitry.

Selecting the PGA Gain Setting

To select the PGA gain setting, first calculate
SensorFSO, the sensor full-span output voltage at T1:

SensorFSO = S · V

BDRIVE

· ∆P

= 1.5mV/V per PSI · 2.5V · 10 PSI

= 0.0375V

where S is the sensor sensitivity at T1, V

BDRIVE

is the

sensor excitation voltage (initially 2.5V), and ∆P is the
maximum pressure differential.

Then calculate the ideal gain using the following formula
and select the nearest gain setting from Table 2:

where OUTFSO is the desired calibrated transducer
full-span output voltage, and SensorFSO is the sensor
full-span output voltage at T1.

In this example, a PGA value of 2 (gain of +95V/V) is
the best selection.

Determining Input-Referred OFFSET

The input-referred offset (IRO) register is used to null
any front-end sensor offset errors prior to amplification
by the PGA. This reduces the possibility of saturating
the PGA and maximizes the useful dynamic range of
the PGA (particularly at the higher gain values).

First, calculate the ideal IRO correction voltage using
the following formula, and select the nearest setting
from Table 1:

where IROideal is the exact voltage required to perfect­ly null the sensor, O(T1) is the sensor offset voltage in
V/V at +25°C, and V

BDRIVE

(T1) is the nominal sensor
excitation voltage at +25°C. In this example, 30mV
must be subtracted from the amplifier front end to null
the sensor perfectly. From Table 1, select an IRO value
of 3 to set the IRO DAC to 27mV, which is nearest the
ideal value. To subtract this value, set the IRO sign bit
to 0. The residual output-referred offset error will be
corrected later with the Offset DAC.

Determining OFFTC COEF Initial Value

Generally, OFFTC COEF can initially be set to 0 since
the offset TC error will be compensated in a later step.
However, sensors with large offset TC errors may
require an initial coarse offset TC adjustment to prevent
the PGA from saturating during the compensation pro­cedure as temperature is increased. An initial coarse
offset TC adjustment is required for sensors with an off­set TC greater than about 10% of the FSO. If an initial

MAX1478

1% Accurate, Digitally Trimmed,

Rail-to-Rail Sensor Signal Conditioner

______________________________________________________________________________________ 13

A

PGA

Programmable-gain amplifier gain

R

ISRC

IRO

Internal (approximately 75kΩ) or user­supplied resistor that programs the nomi­nal sensor excitation current

Input-referred offset correction DAC
value

DESCRIPTION

IRO Sign

PARAMETER

Input-referred offset sign bit

IRS Internal resistor selection bit

OFF COEF Offset-correction DAC coefficient

OFF Sign Offset sign bit

OFFTC COEF Offset TC compensation DAC coefficient

OFFTC Sign Offset TC sign bit

FSO COEF FSO trim DAC coefficient

FSOTC COEF FSO TC compensation DAC coefficient

R

FTC

Internal (approximately 75kΩ) or user­supplied resistor that compensates
FSO TC errors

Table 7. Compensation Components and
Values

R

FTC

R 500ppm/ C

≅

≅

2600ppm/ C - -2100ppm/ C

⋅

ISRC

TCR - TCS

70k 500ppm/ C

°

||

⋅

Ω°

°°

||

70k

=Ω

A

PGA

IROideal - O T1 V T1

OUTFSO

=

SensorFSO

4V

==

0.0375V

=

- 0.012V/V 2.5V

=

- 30mV

=

+106V/V

⋅

() ()

[]

()

BDRIVE

⋅

MAX1478

coarse offset TC adjustment is required, use the follow­ing equation:

where OTC is the sensor offset TC error as a ppm/°C of
OUTFSO (Table 6), ∆T is the operating temperature
range in °C, and OFFTC COEF is the numerical decimal
value to be loaded into the DAC. For positive values,
set the OFFTC sign bit high; for negative values, set the
OFFTC sign bit low. If the absolute value of the OFFTC
COEF is larger than 4096, the sensor has a very large
offset TC error that the MAX1478 is unable to completely
correct.

FSO Calibration

Perform FSO calibration at room temperature with a full­scale sensor excitation.

1) Set FSOTC COEF to 1000.

2) At T1, adjust FSO DAC until V

BDRIVE

is about 2.5V.

3) Adjust Offset DAC (and OFFSET sign bit, if needed)
until the T1 offset voltage is 0.5V (see OFFSET
Calibration section).

4) Measure the full-span output (measuredV

FSO

).

5) Calculate the ideal bridge voltage, V

BIDEAL

(T1),

using the following equation:

Note: If V

BIDEAL

(T1) is outside the allowable bridge
voltage swing of (VSS+ 1.3V) to (VDD- 1.3V), readjust
the PGA gain setting. If V

BIDEAL

(T1) is too low,
decrease the PGA gain setting by one step and return
to Step 2. If V

BIDEAL

(T1) is too high, increase the PGA

gain setting by one step and return to Step 2.

6) Set V

BIDEAL

(T1) by adjusting the FSO DAC.

7) Readjust Offset DAC until the offset voltage is 0.5V
(see OFFSET Calibration section).

Three-Step FSOTC Compensation

Step 1

Use the following procedure to determine FSOTC
COEF; four variables, A–D, will be used:

1) Name the existing FSO DAC coefficient A.

2) Change FSOTC DAC to 3000.

3) Adjust FSO DAC until V

BDRIVE

(T1) is equal to

V

BIDEAL

(T1).

4) Name the existing FSO DAC coefficient B.

5) Readjust the offset voltage (by adjusting the Offset
DAC), if required, to 0.5V.

At this point, it is important that no other changes be
made to the Offset or Offset TC DACs until the Offset
TC Compensation step has been completed.

Step 2

To complete linear FSOTC compensation, take data
measurements at a second temperature, T2 (T2 > T1).
Perform the following steps:

1) Measure the full-span output (measuredV

FSO

(T2)).

2) Calculate V

BIDEAL

(T2) using the following equation:

3) Set V

BIDEAL

(T2) by adjusting the FSO DAC.

4) Name the current FSO DAC coefficient D.

5) Change FSOTC DAC to 1000.

6) Adjust FSO DAC until V

BDRIVE

is equal to

V

BIDEAL

(T2).

7) Name the FSO DAC coefficient C.

Step 3

Insert the data previously obtained from Steps 1 and 2
into the following equation to calculate FSOTC COEF:

1) Load this FSOTC COEF value into the FSOTC DAC.

2) Adjust the FSO DAC until V

BDRIVE

(T2) is equal to

V

BIDEAL

(T2).

This completes both FSO calibration and FSO TC com­pensation.









pp

1% Accurate, Digitally Trimmed,
Rail-to-Rail Sensor Signal Conditioner

14 ______________________________________________________________________________________

OFFTC COEF

VT V

BIDEAL BDRIVE




1

+



4096 V T

⋅

∆

OUT

=

V T 2.3

∆

BDRIVE

4096 OTC FSO T

≅

=

1

()

desiredV - measuredV T

()

TCS V 2.3 T

⋅⋅⋅

4096 -1000ppm/ C 4V

()

-2100

=

FSO FSO

measuredV T

()

⋅

()

⋅⋅

BDRIVE

⋅⋅

m/ C 2.5V 2.3

°

⋅

FSO

∆

∆

°

⋅

1

()

()

=

1

1357







FSOTC COEF

VT2 V

1

=

()

BIDEAL BDRIVE



desiredV - measuredV T2

+






FSO FSO

measuredV T2

1000 B -D 3000 C - A

=

()+()

B-D C-A

()

⋅

()

FSO

+

()

()

Offset TC Compensation

The offset voltage at T1 was previously set to 0.5V;
therefore, any variation from this voltage at T2 is an
offset TC error. Perform the following steps:

1) Measure the offset voltage at T2.

2) Use the following equation to compute the correc­tion required:

Note: CurrentOFFTC COEF is the current value
stored in the Offset TC DAC. If the Offset TC sign bit
(SOTC) is low, this number is negative.

3) Load this value into the Offset TC DAC.

4) If NewOFFTC COEF is negative, set the SOTC bit
low; otherwise, set it high.

Offset TC compensation is now complete.

Offset Calibration

At this point, the sensor should still be at temperature
T2. The final offset adjustment can be made at T2 or T1
by adjusting the Offset DAC (and optionally the offset
sign bit, SOFF) until the output (V

OUT(P

MIN

)

) reads 0.5V

at zero input pressure. Use the following procedure:

1) Set Offset DAC to zero (Offset COEF = 0).

2) Measure the voltage at OUT.

3) If V

OUT

is greater than the desired offset voltage
(0.5V in this example), set SOFF low; otherwise, set
it high.

4) Increase Offset COEF until V

OUT

equals the desired

offset voltage.

Offset calibration is now complete. Table 8 and Figure 9
compare an uncompensated input to a typical compen­sated transducer output.

MAX1478

1% Accurate, Digitally Trimmed,

Rail-to-Rail Sensor Signal Conditioner

______________________________________________________________________________________ 15

Typical Uncompensated Input (Sensor) Typical Compensated Transducer Output

Offset ..........................................................................±80% FSO

FSO................................................................................+15mV/V

Offset TC ......................................................................-17% FSO

Offset TC Nonlinearity ..................................................0.7% FSO

FSO TC.........................................................................-35% FSO

FSO TC Nonlinearity.....................................................0.5% FSO

Temperature Range...........................................-40°C to +125°C

V

OUT

...................................................Ratiometric to VDDat 5.0V

Offset at +25°C ......................................................0.500V ±5mV

FSO at +25°C .........................................................4.000V ±5mV

Offset Accuracy Over Temp Range ...........±28mV (±0.7% FSO)

FSO Accuracy Over Temp Range ..............±20mV (±0.5% FSO)

Table 8. MAX1478 Calibration and Compensation

Figure 9. Comparison of an Uncalibrated Sensor and a Temperature-Compensated Transducer

NewOFFTC COEF CurrentOFFTC COEF -











4096 V T - V T2

OFFSET OFFSET







2.3 V T - V T2

BDRIVE BDRIVE





=



1

() ( )

1

() ( )




















UNCOMPENSATED SENSOR ERROR

30

20

10

0

ERROR (% FSO)

-10

-20

OFFSET

-50 0 50 100 150

FSO

TEMPERATURE (°C)

COMPENSATION TRANSDUCER ERROR

0.8

0.6

0.4

0.2

0

-0.2

ERROR (% SPAN)

-0.4

-0.6

-0.8

-50 0 50 100 150

FSO

OFFSET

TEMPERATURE °(C)

MAX1478

Ratiometric Output Configuration

Ratiometric output configuration provides an output that
is proportional to the power-supply voltage. When used
with ratiometric A/D converters, this output provides
digital pressure values independent of supply voltage.
Most automotive and some industrial applications
require ratiometric outputs.

The MAX1478 provides a high-performance ratiometric
output with a minimum number of external components
(Figure 10). These external components include the fol­lowing:

• One power-supply bypass capacitor (C1)

• Two optional resistors, one from FSOTC to ISRC, and

another from ISRC to VSS, depending on the sensor
type

• One optional capacitor (C2) from BDRIVE to V

SS

Test System Configuration

The MAX1478 is designed to support an automated
production pressure-temperature test system with inte­grated calibration and temperature compensation.
Figure 11 shows the implementation concept for a low­cost test system capable of testing up to 12 transducer
modules connected in parallel. The test system shown
in Figure 11 includes a dedicated test bus consisting of
four wires:

• Two power-supply lines

• Two serial-interface lines: DIO (input/output) and

SCLK (clock)

• An individual V

OUT

line

For simultaneous testing of more than 12 sensor mod­ules, use buffers to prevent overloading the data bus. A
digital multiplexer controls the chip-select signal for
each transducer.

1% Accurate, Digitally Trimmed,
Rail-to-Rail Sensor Signal Conditioner

16 ______________________________________________________________________________________

Figure 10. Basic Ratiometric Output Configuration

BDRIVE

C2

0.1µF

INM

INP

+5V

V

OFFSET

Σ

(IRODAC)

PGA

DD

MAX1478

OUT

C1

0.1µF

SENSOR

ISRC

V

DD

R

R

ISRC

R

FTC

CS

WE

SCLK

DIO

FTC

R

ISRC

V

SS

128-BIT

EEPROM

DIGITAL

INTERFACE

12-BIT D/A - OFFSET

CONFIGURATION REGISTER

A = 1

12-BIT D/A - OFFSET TC

12-BIT D/A - FSO

12-BIT D/A - FSOTC

TEMP

FSOTC

TEMP

V

SS

MAX1478 Evaluation

____________________________________ Development Kit

To expedite the development of MAX1478-based trans­ducers and test systems, Maxim has produced the
MAX1478 evaluation kit (EV kit). First-time users of the
MAX1478 are strongly encouraged to use this kit. The
MAX1478 EV kit is designed to facilitate manual pro­gramming of the MAX1478 and includes the following:

1) Evaluation Board with a silicon pressure sensor.

2) Design/Applications Manual, which describes in
detail the architecture and functionality of the
MAX1478. This manual was developed for test engi­neers familiar with data acquisition of sensor data
and provides sensor compensation algorithms and
test procedures.

3) MAX1478 Communication Software, which enables
programming of the MAX1478 from a computer (IBM
compatible), one module at a time.

4) Interface Adapter and Cable, which allow the con-
nection of the evaluation board to a PC parallel port.

MAX1478 Pilot

_______________________________ P r oduction System

For volume applications, Maxim has developed a fully
automated pilot production system. The system con­sists of the Maxim 14XXDASBOARD and one or more
14XXMUXBOARD modules, a DVM, an environmental
chamber, and a pressure controller. Only the
14XXDASBOARD and the 14XXMUXBOARD modules
are available through Maxim. The user must acquire the

MAX1478

1% Accurate, Digitally Trimmed,

Rail-to-Rail Sensor Signal Conditioner

______________________________________________________________________________________ 17

Figure 11. Automated Test System Concept

DIGITAL

MULTIPLEXER

DVM

VOUT

SCLK

DIO

CS[1:N]

+5V

MODULE 1

V

DD

SCLK

DIO

CS
BDRIVE
INP
INM

OUT

CS1

MAX1478

V

SS

V

DD

N

MODULE 2

SCLK

DIO

BDRIVE
INP
INM

OUT

CS2

CS

MAX1478

V

SS

MODULE N

V

DD

SCLK

DIO

BDRIVE
INP
INM

OUT

TEST
OVEN

CSN

CS

MAX1478

V

SS

MAX1478

1% Accurate, Digitally Trimmed,
Rail-to-Rail Sensor Signal Conditioner

18 ______________________________________________________________________________________

Chip Information

TRANSISTOR COUNT: 7708

SUBSTRATE CONNECTED TO VSS.

DVM, the environmental chamber, and the pressure con­troller through other vendors.

The 14XXDASBOARD, in conjunction with the
14XXMUXBOARD modules, allows the user to compen­sate up to 112 units. IEEE-488 commands select the
active DUT and communicate with the MAX14XX appli­cation circuits. All system voltage measurements are
multiplexed for use with a single external DVM. Each
DUT interfaces to the 14XXMUXBOARD through a general­purpose transition board, which provides digital inter­face signals and low-noise analog inputs. The
14XXDASBOARD is required to operate the
14XXMUXBOARD. All driver software is incorporated
into the 14XXDASBOARD firmware. Sensor compensa­tion procedure is implemented using National
Instruments’ LabView program. Customers may have to
adapt portions of the compensation procedure if they
are using a pressure controller, oven, or DVM that is
different from the type for which the system was
designed.

The system will be available free to all customers who
order MAX14XX. Minimum order quantities apply.
Contact factory for details.

Functional Diagram

Block Diagram

BDRIVE

INP

INM

ISRC

V

R

FTC

R

ISRC

V

SS

CS

WE

SCLK

DIO

V

DD

MAX1478

PGA

12-BIT D/A - OFFSET TC

12-BIT D/A - OFFSET

CONFIGURATION REGISTER

12-BIT D/A - FSO

12-BIT D/A - FSOTC

TEMP

Σ

DD

128-BIT
EEPROM

DIGITAL

INTERFACE

OFFSET

(IRODAC)

A = 1

OUT

FSOTC

TEMP

V

SS

MAX14XX PILOT TESTER

MAX14XX DAS/MUX

IEEE-488 BUS

PRESSURE

CONTROLLER

DMM

ONE CABLE/DUT

TEMP CHAMBER

DUT

#1

DUT

#112

MAX1478

1% Accurate, Digitally Trimmed,

Rail-to-Rail Sensor Signal Conditioner

______________________________________________________________________________________ 19

Package Information

SSOP.EPS

MAX1478

1% Accurate, Digitally Trimmed,
Rail-to-Rail Sensor Signal Conditioner

Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are
implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.

20 ____________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600

© 1999 Maxim Integrated Products Printed USA is a registered trademark of Maxim Integrated Products.

NOTES