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General Description
The MAX1205 is a 14-bit, monolithic, analog-to-digital
converter (ADC) capable of conversion rates up to
1Msps. This integrated circuit, built on a CMOS process, uses a fully differential, pipelined architecture
with digital error correction and a short self-calibration
procedure that corrects for capacitor and gain mismatches and ensures 14-bit linearity at full sample
rates. An on-chip track/hold (T/H) maintains superb
dynamic performance up to the Nyquist frequency. The
MAX1205 operates from a single +5V supply.
The fully differential inputs allow an input swing of
±V
REF
. The reference is also differential, with the positive reference (RFPF) typically connected to +4.096V
and the negative reference (RFNF) connected to analog ground. Additional sensing pins (RFPS, RFNS) are
provided to compensate for any resistive-divider action
that may occur due to finite internal and external resistances in the reference traces and the on-chip resistance of the reference pins. A single-ended input is
also possible using two operational amplifiers.
The power dissipation is typically 257mW at +5V, at a
sampling rate of 1Msps. The device employs a CMOScompatible, 14-bit parallel, two’s complement output
data format. For higher sampling rates, the MAX1201 is
a 2.2Msps pin-compatible upgrade to the MAX1205.
The MAX1205 is available in an MQFP package, and
operates over the commercial (0°C to +70°C) and the
extended (-40°C to +85°C) temperature ranges.
Applications
Imaging
Communications
Medical
Scanners
Data Acquisition
Features
♦ Monolithic, 14-Bit, 1Msps ADC
♦ +5V Single Supply
♦ SNR of 80dB for f
IN
= 500kHz
♦ SFDR of 87dB for f
IN
= 500kHz
♦ Low Power Dissipation: 257mW
♦ On-Demand Self-Calibration
♦ Differential Nonlinearity Error: ±0.3LSB
♦ Integral Nonlinearity Error: ±1.2LSB
♦ Three-State, Two’s Complement Output Data
MAX1205
+5V Single-Supply, 1Msps, 14-Bit
Self-Calibrating ADC
________________________________________________________________
Maxim Integrated Products
1
OE
DAV
CLK
DV
DD
DGND
DGND
DV
DD
TEST1
TEST2
TEST3
D0
ST_CAL
AGND
AV
DD
AGND
AGND
AV
DD
DOR
D13
D12
D11
D10
1
2
3
4
5
6
7
8
9
10
11
1213141516171819202122
4443424140393837363534
33
32
31
30
29
28
27
26
25
24
23
D9D8D7
D6
DRV
DD
DGND
D5D4D3D2D1
END_CAL
INN
N.C.
N.C.
INP
RFNS
RFNF
RFPS
RFPFCMTEST0
TOP VIEW
MQFP
MAX1205
19-4794; Rev 0; 11/98
PART
MAX1205CMH
MAX1205EMH -40°C to +85°C
0°C to +70°C
TEMP. RANGE PIN-PACKAGE
44 MQFP
44 MQFP
EVALUATION KIT
AVAILABLE
Pin Configuration
Ordering Information
MAX1205
+5V Single-Supply, 1Msps, 14-Bit
Self-Calibrating ADC
2 _______________________________________________________________________________________
ABSOLUTE MAXIMUM RATINGS
ELECTRICAL CHARACTERISTICS
(AVDD= +5V ±5%, DVDD= DRVDD= +3.3V, V
RFPS
= +4.096V, V
RFNS
= AGND, VCM= +2.048V, VIN= -0.5dBFS, f
CLK
= 2.048MHz,
digital output load ≤ 20pF, T
A
= T
MIN
to T
MAX
, unless otherwise noted. Typical values are at TA= +25°C.) (Note 1)
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
AVDDto AGND, DGND..........................................................+7V
DV
DD
to DGND, AGND..........................................................+7V
DRV
DD
to DGND, AGND .......................................................+7V
INP, INN, RFPF, RFPS, RFNF, RFNS,
CLK, CM.................................(AGND - 0.3V) to (AV
DD
+ 0.3V)
Digital Inputs to DGND............................-0.3V to (DV
DD
+ 0.3V)
Digital Output (DAV) to DGND..............-0.3V to (DRV
DD
+ 0.3V)
Other Digital Outputs to DGND.............-0.3V to (DRV
DD
+ 0.3V)
Continuous Power Dissipation (TA= +70°C)
44-Pin MQFP (derate 11.11mW/°C above +70°C)........889mW
Operating Temperature Ranges (T
A
)
MAX1205CMH .....................................................0°C to +70°C
MAX1205EMH ..................................................-40°C to +85°C
Storage Temperature Range.............................-65°C to +150°C
Lead Temperature (soldering, 10sec).............................+300°C
REFERENCE/EXTERNAL
TRANSFER CHARACTERISTICS
DYNAMIC SPECIFICATIONS (Note 6)
ANALOG INPUT
To full-scale step (0.006%)
ns
3
t
AD
Aperture Delay
ns
410
t
OVR
ns
100
t
ACQ
Acquisition Time
Overvoltage Recovery Time
MHz
3.3
Full-Power Bandwidth
MHz
78
Small-Signal Bandwidth
After calibration, guaranteed
f
SAMPLE
=
f
CLK
/
2
LSB
-1 ±0.3 +1
DNLDifferential Nonlinearity
LSB
±1.2
INL
Bits
14
RES
Resolution (no missing codes)
(Note 5)
Integral Nonlinearity
f
SAMPLE
Cycles
4
Conversion Time (Pipeline
Delay/Latency)
Msps
1.024
f
SAMPLE
Maximum Sampling Rate
%FSR
-0.2 ±0.003 +0.2
Offset Error
%FSR
-5 -3.0 +5
Gain Error
µV
RMS
75
Input-Referred Noise
Differential
Single-ended
Per side in track mode
CONDITIONS
±4.096 ±4.5
V
4.096 4.5
V
IN
Input Voltage Range
(Notes 2, 3)
Ω
700 1000
Reference Input Resistance
kΩ
55
R
I
Input Resistance (Note 4)
pF
21
C
I
Input Capacitance (Note 3)
V
4.096 4.5
V
REF
Reference Voltage (Note 3)
UNITSMIN TYP MAXSYMBOLPARAMETER
MAX1205
+5V Single-Supply, 1Msps, 14-Bit
Self-Calibrating ADC
_______________________________________________________________________________________ 3
ELECTRICAL CHARACTERISTICS (continued)
(AVDD= +5V ±5%, DVDD= DRVDD= +3.3V, V
RFPS
= +4.096V, V
RFNS
= AGND, VCM= +2.048V, VIN= -0.5dBFS, f
CLK
= 2.048MHz,
digital output load ≤ 20pF, T
A
= T
MIN
to T
MAX
, unless otherwise noted. Typical values are at TA= +25°C.) (Note 1)
dB
55Gain
55Offset
PSRRPower-Supply Rejection Ratio
sec0.1Warm-Up Time
mW257 377PDSSPower Dissipation
10pF loads on D0–D13 and DAV mA0.1 0.6I(DRVDD)Output Drive Supply Current
V3 DV
DD
DRV
DD
Output Drive Supply Voltage
V4.75 5 5.25AV
DD
Analog Supply Voltage
V3 5.25DV
DD
Digital Supply Voltage
mA0.4 1.2I(DVDD)Digital Supply Current
fIN= 504.5kHz
fIN= 300.5kHz
fIN= 99.5kHz
fIN= 504.5kHz
fIN= 300.5kHz
fIN= 99.5kHz
fIN= 300.5kHz
fIN= 504.5kHz
fIN= 99.5kHz
87
Spurious-Free Dynamic Range
(Note 5)
88SFDR dB
84 91
78
79
dB
-86 -80
THD
Total Harmonic Distortion
(Note 5)
-85
-84
dB
77 82
SINAD
Signal-to-Noise Ratio plus
Distortion (Note 5)
CONDITIONS UNITSMIN TYP MAXSYMBOLPARAMETER
fIN= 504.5kHz
fIN= 300.5kHz
fIN= 99.5kHz
80
81.5
dB
78 83
SNR
Signal-to-Noise Ratio
(Note 5)
mA51 70I(AVDD)Analog Supply Current
POWER REQUIREMENTS
MAX1205
+5V Single-Supply, 1Msps, 14-Bit
Self-Calibrating ADC
4 _______________________________________________________________________________________
CL= 20pF
CONDITIONS
ns187 244 301t
CH
Clock High Time
ns488t
CLK
ns4 / f
SAMPLE
t
CONV
Conversion Time
Clock Period
ns16 75t
REL
Bus Relinquish Time
ns16 75t
AC
Data Access Time
ns187 244 301t
CL
Clock Low Time
ns70 150t
OD
Output Delay
ns1 / f
CLK
t
DAV
DAV Pulse Width
ns65 145t
S
CLK-to-DAV Rising Edge
UNITSMIN TYP MAXSYMBOLPARAMETER
DIGITAL INPUTS AND OUTPUTS
(AVDD= +5V ±5%, DVDD= DRVDD= +3.3V, TA= T
MIN
to T
MAX
, unless otherwise noted. Typical values are at TA= +25°C.)
I
SOURCE
= 200µA
V
IN_
= 0 or DV
DD
CONDITIONS
4Input Capacitance
DV
DD
- 0.8
V
IH
0.8V
IL
Input Low Voltage
Input High Voltage
DV
DD
DV
DD
- 0.4 - 0.03
V
OH
Output High Voltage
0.8CLK
VIL
CLK Input Low Voltage
AV
DD
- 0.8
CLK
VIH
CLK Input High Voltage
9C
CLK
CLK Input Capacitance
±0.1 ±10I
IN_
Digital Input Current
MIN TYP MAX
SYMBOLPARAMETER
-10 ±1 +10I
CLK
Clock Input Current
±0.1 ±10I
LEAKAGE
Three-State Leakage Current
3.5C
OUT
Three-State Output Capacitance
µA
µA
pF
pF
V
V
V
V
V
pF
µA
UNITS
TIMING CHARACTERISTICS
(AVDD= +5V ±5%, DVDD= DRVDD= +3.3V, f
CLK
= 2.048MHz, TA= T
MIN
to T
MAX
, unless otherwise noted. Typical values are at
T
A
= +25°C.) (Note 1)
nst
CLK
/ 2t
ACQ
Acquisition Time
Note 1: Reference inputs driven by operational amplifiers for Kelvin-sensed operation.
Note 2: For unipolar mode, the analog input voltage V
INP
must be within 0V and V
REF
, V
INN
= V
REF
/ 2; where V
REF
= V
RFPS
- V
RFNS
.
For differential mode, the analog inputs INP and INN must be within 0V and V
REF
; where V
REF
= V
RFPS
- V
RFNS
. The com-
mon mode of the inputs INP and INN is V
REF
/ 2.
Note 3: Minimum and maximum parameters are not tested. Guaranteed by design.
Note 4: R
I
varies inversely with sample rate.
Note 5: Calibration remains valid for temperature changes within ±20°C and power-supply variations ±5%.
Note 6: All AC specifications are shown for the differential mode.
ST_CAL = 1, Figure 8
f
CLK
cycles
17,400t
CAL
Calibration Time
I
SINK
= 1.6mA 70 400V
OL
Output Low Voltage mV
MAX1205
+5V Single-Supply, 1Msps, 14-Bit
Self-Calibrating ADC
_______________________________________________________________________________________
5
-1.25
-1.00
-0.75
-0.50
-0.25
0
0.25
0.50
0.75
1.00
1.25
-8192 -4096-2048-6144 0 2048 4096 6144 8192
INTEGRAL NONLINEARITY vs.
TWO’S COMPLEMENT OUTPUT CODE
MAX1205-01
TWO’S COMPLEMENT OUTPUT CODE
INL (LSB)
-1.0
-0.5
0
0.5
1.0
-8192 -4096-2048-6144 0 2048 4096 6144 8192
DIFFERENTIAL NONLINEARITY vs.
TWO’S COMPLEMENT OUTPUT CODE
MAX1205-02
TWO’S COMPLEMENT OUTPUT CODE
DNL (LSB)
30
50
40
80
70
60
110
100
90
120
-80 -50 -40-70 -60 -30 -20 -10 0
SINGLE-TONE SPURIOUS-FREE DYNAMIC RANGE
vs. INPUT AMPLITUDE (f
IN
= 99.5kHz)
MAX1205-03
INPUT AMPLITUDE (dBFS)
SFDR (dB)
dBFS
dBc
82
64
1 100010010
SIGNAL-TO-NOISE RATIO PLUS
DISTORTION vs. INPUT FREQUENCY
70
66
78
74
84
72
68
80
76
MAX1205-04
INPUT FREQUENCY (kHz)
SINAD (dB)
AIN = -0.5dBFS
AIN = -6dBFS
AIN = -20dBFS
-90
1 100010010
TOTAL HARMONIC DISTORTION
vs. INPUT FREQUENCY
-84
-88
-76
-80
-82
-86
-78
MAX1205-05
INPUT FREQUENCY (kHz)
THD (dB)
AIN = -20dBFS
AIN = -6dBFS
AIN = -0.5dBFS
60
1 100010010
SIGNAL-TO-NOISE RATIO
vs. INPUT FREQUENCY
85
70
65
80
75
MAX1205-06
INPUT FREQUENCY (kHz)
SNR (dB)
AIN = -0.5dBFS
AIN = -6dBFS
AIN = -20dBFS
Typical Operating Characteristics
(AVDD= +5V ±5%, DVDD= DRVDD= +3.3V, V
RFPS
= +4.096V, V
RFNS
= AGND, VCM= +2.048V, differential input, f
CLK
= 2.048MHz,
calibrated, TA= +25°C, unless otherwise noted.)
85
80
0.1 1
SIGNAL-TO-NOISE RATIO PLUS DISTORTION
vs. SAMPLING RATE (f
IN
= 99.5kHz)
81
MAX1205-07
SAMPLE RATE (Msps)
SINAD (dB)
82
83
84
AIN = -0.5dBFS
0
-105
-120
-135
-90
-75
-60
-45
-30
-15
0 200100 300 400 500 600
TYPICAL FFT
(f
IN
= 99.5kHz, 2048 VALUE RECORD)
MAX1205-08
FREQUENCY (kHz)
AMPLITUDE (dBFS)
MAX1205
+5V Single-Supply, 1Msps, 14-Bit
Self-Calibrating ADC
6 _______________________________________________________________________________________
0
-105
-120
-135
-90
-75
-60
-45
-30
-15
0 200100 300 400 500 600
TYPICAL FFT
(f
IN
= 504.5kHz, 2048 VALUE RECORD)
MAX1205-09
FREQUENCY (kHz)
AMPLITUDE (dBFS)
Typical Operating Characteristics (continued)
(AVDD= +5V ±5%, DVDD= DRVDD= +3.3V, V
RFPS
= +4.096V, V
RFNS
= AGND, VCM= +2.048V, differential input, f
CLK
= 2.048MHz,
calibrated, TA= +25°C, unless otherwise noted.)
1 100010010
EFFECTIVE NUMBER OF BITS
vs. INPUT FREQUENCY
MAX1205-10
INPUT FREQUENCY (kHz)
ENOB (Bits)
10.0
10.5
11.0
11.5
12.0
12.5
13.0
13.5
14.0
AIN = -0.5dBFS
AIN = -6dBFS
AIN = -20dBFS
Pin Description
PIN
Digital Input to Start Calibration.
ST_CAL = 0: Normal conversion mode.
ST_CAL = 1: Start self-calibration.
ST_CAL1
FUNCTIONNAME
Analog GroundAGND2, 4, 5
Data Out-of-Range BitDOR7
Analog Power Supply, +5V ±5%AV
DD
3, 6
Bit 12D129
Bit 10D1011
Bit 11D1110
Bit 13 (MSB)D138
Bit 8D813
Bit 6D615
Bit 7D714
Digital GroundDGND17, 28, 29
Bit 4D419
Bit 5D518
Digital Power Supply for the Output Drivers, +3V to +5.25V, DRVDD≤ DV
DD
DRV
DD
16
Bit 9D912
Bit 2D221
Bit 3D320
Bit 0 (LSB)D023
Bit 1D122
Test Pin 3. Leave unconnected.
TEST324
MAX1205
+5V Single-Supply, 1Msps, 14-Bit
Self-Calibrating ADC
_______________________________________________________________________________________ 7
Pin Description (continued)
PIN
Test Pin 2. Leave unconnected.
TEST225
FUNCTIONNAME
Digital Power Supply, +3V to +5.25VDV
DD
27, 30
Test Pin 1. Leave unconnected.
TEST126
Data Valid Clock Output. This clock can be used to transfer the data to a memory or any other
data-acquisition system.
DAV32
Input Clock. Receives power from AVDDto reduce jitter.CLK31
Test Pin 0. Leave unconnected.
TEST034
Output Enable Input.
OE = 0: D0-D13 and DOR are high impedance.
OE = 1: All bits are active.
OE33
Positive Reference Voltage. Force input.RFPF36
Common-Mode Voltage. Analog Input. Drive midway between positive and negative reference voltages.CM35
Negative Reference Voltage. Force input.RFNF38
Positive Reference Voltage. Sense input.RFPS37
Not Connected. No internal connection.N.C.41, 42
Positive Input VoltageINP40
Digital Output for End of Calibration.
END_CAL = 0: Calibration in progress.
END_CAL = 1: Normal conversion mode.
END_CAL44
Negative Input VoltageINN43
Negative Reference Voltage. Sense input.RFNS39
_______________Detailed Description
Converter Operation
The MAX1205 is a 14-bit, monolithic, analog-to-digital
converter (ADC) capable of conversion rates up to
1Msps. It uses a multistage, fully differential pipelined
architecture with digital error correction and self-calibration to provide typically greater than 91dB spuriousfree dynamic range at a 1Msps sampling rate. Its
signal-to-noise ratio, harmonic distortion, and intermodulation products are also consistent with 14-bit accuracy up to the Nyquist frequency. This makes the device
suitable for applications such as imaging, scanners,
data acquisition, and digital communications.
Figure 1 shows the simplified, internal structure of the
ADC. A switched-capacitor pipelined architecture is
used to digitize the signal at a high throughput rate.
The first four stages of the pipeline use a low-resolution
quantizer to approximate the input signal. The multiplying digital-to-analog converter (MDAC) stage is used to
subtract the quantized analog signal from the input.
The residue is then amplified with a fixed gain and
passed on to the next stage. The accuracy of the converter is improved by a digital calibration algorithm
which corrects for mismatches between the capacitors
in the switched capacitor MDAC. Note that the pipeline
introduces latency of four sampling periods between
the input being sampled and the output appearing at
D13–D0.
While the device can handle both single-ended and differential inputs (see
Requirements for Reference and
Analog Signal Inputs
), the latter mode of operation will
guarantee best THD and SFDR performance. The differential input provides the following advantages compared to a single-ended operation:
• Twice as much signal input span
• Common-mode noise immunity
• Virtual elimination of the even-order harmonics
• Less stringent requirements on the input signal
processing amplifiers
MAX1205
+5V Single-Supply, 1Msps, 14-Bit
Self-Calibrating ADC
8 _______________________________________________________________________________________
Requirements for Reference
and Analog Signal Inputs
Fully differential switched-capacitor circuits (SC) are
used for both the reference and analog inputs (Figure 2).
This allows either single-ended or differential signals to
be used in the reference and/or analog signal paths.
The signal voltage on these pins (INP, INN, RFN_,
RFP_) should never exceed the analog supply rail,
AVDD, and should not fall below ground.
Choice of Reference
It is important to choose a low-noise reference, such as
the MAX6341, which can provide both excellent load
regulation and low temperature drift. The equivalent
input circuit for the reference pins is shown in Figure 3.
Note that the reference pins drive approximately 1kΩ of
resistance on chip. They also drive a switched capacitor of 21pF. To meet the dynamic performance, the reference voltage is required to settle to 0.0015% within
one clock cycle. Accomplish this by choosing an
appropriate driving circuit (Figure 4). The capacitors at
the reference pins (RFPF, RFNF) provide the dynamic
charge required during each clock cycle, while the op
amps ensure accuracy of the reference signals. These
capacitors must have low dielectric-absorption characteristics, such as polystyrene or teflon capacitors.
The reference pins can be connected to either singleended or differential voltages within the specified maximum levels. Typically the positive reference pin (RFPF)
would be driven to 4.096V, and the negative reference
pin (RFNF) connected to analog ground. There are
sense pins, RFPS and RFNS, which can be used with
RFPF
INP
INN
RFPF
CM
CM
RFNF
Figure 2. Simplified MDAC Architecture
RFPF
RFPS
RFNF
RFNS
Figure 3. Equivalent Input at the Reference Pins. The sense
pins should not draw any DC current.
STAGE1
7
DAV
INP
CM AV
DD
RFN_RFP_ AGND
INN
CLK
DV
DD
DGND
DRV
DD
ST_CAL
DOR
D13–D0
17
ADC
ADC MDAC
8X
S/H
STAGE2 STAGE3 STAGE4
CORRECTION AND
CALIBRATION LOGIC
END_CAL
OE
OUTPUT DRIVERS
CLOCK
GENERATOR
MAX1205
Figure 1. Internal Block Diagram
external amplifiers to compensate for any resistive drop
on these lines, internal or external to the chip. Ensure a
correct reference voltage by using proper Kelvin connections at the sense pins.
Common-Mode Voltage
The switched capacitor input circuit at the analog input
allows signals between AGND and the analog power
supply. Since the common-mode voltage has a strong
influence on the performance of the ADC, the best
results are obtained by choosing VCMto be at half the
difference between the reference voltages V
RFP
and
V
RFN
. Achieve this by using a resistive divider between
the two reference potentials. Figure 4 shows a typical
driving circuit for good dynamic performance.
Analog Signal Conditioning
For single-ended inputs the negative analog input pin
(INN) is connected to the common-mode voltage pin
(CM), and the positive analog input pin (INP) is connected to the input.
To take full advantage of the ADC’s superior AC performance up to the Nyquist frequency, drive the chip with
differential signals. In communication systems, the signals may inherently be available in differential mode.
Medical and/or other applications may only provide sin-
gle-ended inputs. In this case, convert the singleended signals into differential ones by using the circuit
recommended in Figure 5. Use low-noise, wideband
amplifiers such as the MAX4108 to maintain the signal
purity over the full-power bandwidth of the MAX1205
input.
Lowpass or bandpass signals may be required to
improve the signal-to-noise-and-distortion ratio of the
incoming signal. For low-frequency signals (<100kHz),
active filters may be used. For higher frequencies, passive filters are more convenient.
Single-Ended to Differential
Conversion Using Transformers
An alternative single-ended to differential-ended conversion method is a balun transformer such as the
CTX03-13675 from Coiltronics. An important benefit of
these transformers is their ability to level-shift singleended signals referred to ground on the primary side to
optimum common-mode voltages on the secondary
side. At frequencies below 20kHz, the transformer core
begins to saturate, causing odd-order harmonics.
Clock Source Requirements
Pipelined ADCs typically need a 50% duty cycle clock.
To avoid this constraint, the MAX1205 provides a
MAX1205
+5V Single-Supply, 1Msps, 14-Bit
Self-Calibrating ADC
_______________________________________________________________________________________ 9
RFP = 4.096V
RFN = 0V
5k
5k
MAX410
CHIP BOUNDARY
CM
RFNS
RFNF
RFPS
RFPF
MAX410
MAX410
Figure 4. Drive Circuit for the Reference Pins and the CommonMode Pin
MAX4108
INP
INN
CM
V-
V+
IN
CM
V+
V-
MAX4108
Figure 5. A simple circuit generates differential signals from a
single-ended input referred to analog ground. The commonmode voltage at INP and INN is the same as CM.
MAX1205
divide-by-two circuit, which relaxes this requirement.
The clock generator should be chosen commensurate
with the frequency range, amplitude, and slew rate of
the signal source. If the slew rate of the input signal is
small, the jitter requirement on the clock is relaxed.
However, if the slew rate is high, the clock jitter needs
to be kept at a minimum. For a full-scale amplitude
input sine wave, the maximum possible signal-to-noise
ratio (SNR) due completely to clock jitter is given by:
For example, if fINis 0.5MHz and σ
JITTER
is 20ps RMS,
then the SNR limit due to jitter is about 84dB. Generating
such a clock source requires a low-noise comparator
and a low-phase-noise signal generator. The clock circuit shown in Figure 6 is a possible solution.
Calibration Procedure
Since the MAX1205 is based on a pipelined architecture, low-resolution quantizers (“coarse ADCs”) are
used to approximate the input signal. MDACs of the
same resolution are then used to reconstruct the input
signal, which is subtracted from the input and the
residue amplified by the SC gain stage. This residue is
then passed on to the next stage.
The accuracy of the MAX1205 is limited by the precision of the MDAC, which is strongly dependent on the
matching of the capacitors used. The mismatch
between the capacitors is determined and stored in an
on-chip memory, which is later used during the conversion of the input signal.
During the calibration procedure, the clock must be
running continuously. ST_CAL (start of calibration) is
initiated by a positive pulse with a minimum width of
four clock cycles, but no longer than about 17,400
clock cycles (Figure 8).
The ST_CAL input may be asynchronous with the clock,
since it is retimed internally. With ST_CAL activated,
END_CAL goes low one or two clock cycles later and
remains low until the calibration is complete. During this
period, the reference voltages must be stable to less
than 0.01%; otherwise the calibration will be invalid.
During calibration, the analog inputs INP and INN are
not used; however, better performance is achieved if
these inputs are static. Once END_CAL goes high (indicating that the calibration procedure is complete), the
ADC is ready for conversion.
Once calibrated, the MAX1205 is insensitive to small
changes (<5%) in power-supply voltage or temperature. Following calibration, if the temperature changes
more than ±20°C, the device should be recalibrated to
maintain optimum performance.
SNR
f
MAX
IN
JITTER
=
1
2π σ
+5V Single-Supply, 1Msps, 14-Bit
Self-Calibrating ADC
10 ______________________________________________________________________________________
MAX961
CLK
V+
V+
0.1µF
0.1µF
0.1µF
1k
1k
CLK_IN
5k
Figure 6. Clock Generation Circuit Using a Low-Noise
Comparator
t
S
tCHt
CL
N
CLK
AIN
SAMPLE
CLOCK
DAV
N-3 N-2 N-1 N N+1
D0–D13
N+1
N+2
N+3
N+4
N+5
t
OD
Figure 7. Main Timing Diagram
CLK
ST_CAL
END_CAL
min 4 t
CLK
~17,400 CLK Cycles
Figure 8. Timing for Start and End of Calibration
Z Z
DOR
D0–D13
OE
t
AC
t
REL
Figure 9. Timing for Bus Access and Bus Relinquish—
Controlled by Output Enable (OE)
Two’s Complement Output
The MAX1205 outputs data in two’s complement format. Table 1 shows how to convert the various fullscale inputs into their two’s complement output codes.
Applications Information
Signal-to-Noise Ratio (SNR)
For a waveform perfectly reconstructed from digital
samples, the theoretical maximum SNR is the ratio of
full-scale analog input (RMS value) to the RMS quantization error (residual error). The ideal, theoretical minimum analog-to-digital noise is caused by quantization
error only and results directly from the ADC’s resolution
(N bits):
SNR
(MAX)
= (6.02N + 1.76)dB
In reality, there are other noise sources besides quantization noise including thermal noise, reference noise,
clock jitter, etc. Therefore, SNR is computed by taking
the ratio of the RMS signal to the RMS noise, which
includes all spectral components minus the fundamental, the first nine harmonics, and the DC offset.
Signal-to-Noise Plus Distortion (SINAD)
SINAD is the ratio of the fundamental input frequency’s
RMS amplitude to all other ADC output signals:
SINAD (dB) = 20log [(Signal
RMS
/ (Noise +
Distortion)
RMS
]
Effective Number of Bits (ENOB)
ENOB indicates the global accuracy of an ADC at a
specific input frequency and sampling rate. An ideal
ADC’s error consists of quantization noise only. With an
input range equal to the full-scale range for the ADC,
the effective number of bits can be calculated as follows:
ENOB = (SINAD - 1.76) / 6.02
Total Harmonic Distortion (THD)
THD is the ratio of the RMS sum of the first nine harmonics of the input signal to the fundamental itself. This
is expressed as:
where V1is the fundamental amplitude, and V2through
V9are the amplitudes of the 2nd through 9th order harmonics.
Spurious-Free
Dynamic Range (SFDR)
SFDR is the ratio of RMS amplitude of the fundamental
(maximum signal component) to the RMS value of the
next largest spurious component, excluding DC offset.
Grounding and
Power-Supply Decoupling
Grounding and power-supply decoupling strongly influence the performance of the MAX1205. At 14-bit resolution, unwanted digital crosstalk may couple through
the input, reference, power-supply, and ground connections; this adversely affects the SNR or SFDR. In
addition, electromagnetic interference (EMI) can either
couple into or be generated by the MAX1205.
Therefore, grounding and power-supply decoupling
guidelines should be closely followed.
THD 20log
V V V V
V
2
2
3
2
4
2
9
2
=
+ + + ⋅⋅⋅+
1
MAX1205
+5V Single-Supply, 1Msps, 14-Bit
Self-Calibrating ADC
______________________________________________________________________________________ 11
0111....1111
TWO’S COMPLEMENT
0111....1111
ONE’S COMPLEMENT
1111....1111+FSR - 1LSB
SCALE OFFSET BINARY
Table 1. Two’s Complement Conversion
0110....0000 0110....00001110....0000+3/4FSR
0100....0000 0100....0000
0010....0000 0010....00001010....0000+1/4FSR
1100....0000+1/2FSR
0000....0000 0000....0000
— 1111....1111—-0
1110....0000 1101....1111
1100....0000 1011....11110100....0000
1000....0000+0
-1/2FSR
0110....0000-1/4FSR
1010....0000 1001....11110010....0000-3/4FSR
1000....0001 1000....0000
1000....0000 —0000....0000-FSR
0000....0001-FSR + 1LSB
MAX1205
+5V Single-Supply, 1Msps, 14-Bit
Self-Calibrating ADC
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are
implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
12
____________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600
© 1998 Maxim Integrated Products Printed USA is a registered trademark of Maxim Integrated Products.
First, a multilayer printed circuit board (PCB) with separate ground and power-supply planes is recommended. Run high-speed signal traces directly above the
ground plane. Since the MAX1205 has separate analog
and digital ground buses (AGND and DGND respectively), the PCB should also have separate analog and
digital ground sections connected at only one point
(star ground). Digital signals should run above the digital ground plane and analog signals should run above
the analog ground plane. Digital signals should be kept
far away from the sensitive analog inputs, reference
inputs senses, common-mode input, and clock input.
The MAX1205 has three power-supply inputs: analog
VDD(AVDD), digital VDD(DVDD), and drive V
DD
(DRVDD).
Each AVDDinput should be decoupled with parallel
ceramic-chip capacitors of values 0.1µF and 0.001µF,
with these capacitors as close to the pin as possible and
with the shortest possible connection to the ground
plane. The DVDDpins should also have separate 0.1µF
capacitors adjacent to their respective pins, as should the
DRVDDpin. Minimize the digital load capacitance.
However, if the total load capacitance on each digital output exceeds 20pF, the DRVDDdecoupling capacitor
should be increased or, preferably, digital buffers should
be added.
The power-supply voltages should be decoupled with
large tantalum or electrolytic capacitors at the point
they enter the PCB. Ferrite beads with additional
decoupling capacitors forming a pi-network may
improve performance.
The analog power-supply input (AVDD) for the
MAX1205 is typically +5V while the digital supplies can
vary from +5V to +3V. Usually, DVDDand DRVDDpins
are connected to the same power supply. Note that the
DVDDsupply voltage must be greater than or equal to
the DRVDDvoltage. For example, a digital +3.3V supply
could be connected to DRVDDwhile a cleaner +5V
supply is connected to DVDD, resulting in slightly
improved performance. Alternatively, the +3.3V supply
could be connected to both DRVDDand DVDD.
However, the +3.3V supply should not be connected to
DVDDwhile the +5V supply is connected to DRV
DD
(Table 2).
Table 2. Power-Supply Voltage Combinations
___________________Chip Information
TRANSISTOR COUNT: 56,577
SUBSTRATE CONNECTED TO: AGND
AV
DD
(V) ALLOWED/NOT ALLOWED
Allowed+5
Allowed
Not Allowed
+5
+5
Allowed
DRV
DD
(V)
+3.3
+5
+5
+5 +3.3
DV
DD
(V)
+3.3
+5
+3.3
+5
Package Information
MQFP44.EPS
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