Datasheet MAX1185 Datasheet (MAXIM)

For pricing, delivery, and ordering information, please contact Maxim Direct at 1-888-629-4642,
or visit Maxim’s website at www.maxim-ic.com.

General Description

The MAX1185 is a 3V, dual 10-bit analog-to-digital con­verter (ADC) featuring fully-differential wideband track­and-hold (T/H) inputs, driving two pipelined, nine-stage
ADCs. The MAX1185 is optimized for low-power, high
dynamic performance applications in imaging, instru­mentation, and digital communication applications. This
ADC operates from a single 2.7V to 3.6V supply, con­suming only 105mW while delivering a typical signal-to­noise ratio (SNR) of 59.5dB at an input frequency of

7.5MHz and a sampling rate of 20Msps. Digital outputs
A and B are updated alternating on the rising (CHA)
and falling (CHB) edge of the clock. The T/H driven
input stages incorporate 400MHz (-3dB) input ampli­fiers. The converters may also be operated with single­ended inputs. In addition to low operating power, the
MAX1185 features a 2.8mA sleep mode as well as a
1µA power-down mode to conserve power during idle
periods.

An internal 2.048V precision bandgap reference sets
the full-scale range of the ADC. A flexible reference
structure allows the use of this internal or an externally
derived reference, if desired for applications requiring
increased accuracy or a different input voltage range.

The MAX1185 features parallel, multiplexed, CMOS­compatible three-state outputs. The digital output for­mat can be set to two’s complement or straight offset
binary through a single control pin. The device provides
for a separate output power supply of 1.7V to 3.6V for
flexible interfacing. The MAX1185 is available in a 7mm
x 7mm, 48-pin TQFP package, and is specified for the
extended industrial (-40°C to +85°C) temperature
range.

Pin-compatible, nonmultiplexed. high-speed versions of
the MAX1185 are also available. Refer to the MAX1180
data sheet for 105Msps, the MAX1181 data sheet for
80Msps, the MAX1182 data sheet for 65Msps, the
MAX1183 data sheet for 40Msps, and the MAX1184
data sheet for 20Msps.

Applications

High Resolution Imaging

I/Q Channel Digitization

Multichannel IF Sampling

Instrumentation

Video Application

Ultrasound

Features

o Single 3V Operation
o Excellent Dynamic Performance:

59.5dB SNR at f

IN

= 7.5MHz

74dB SFDR at f

IN

= 7.5MHz

o Low Power:

35mA (Normal Operation)

2.8mA (Sleep Mode)
1µA (Shutdown Mode)

o 0.02dB Gain and 0.25° Phase Matching
o Wide ±1Vp-p Differential Analog Input Voltage

Range

o 400MHz, -3dB Input Bandwidth
o On-Chip 2.048V Precision Bandgap Reference
o Single 10-Bit Bus for Multiplexed, Digital Outputs
o User-Selectable Output Format—Two’s

Complement or Offset Binary

o 48-Pin TQFP Package with Exposed Pad for

Improved Thermal Dissipation

MAX1185

Dual 10-Bit, 20Msps, 3V, Low-Power ADC with

Internal Reference and Multiplexed Parallel Outputs

________________________________________________________________

Maxim Integrated Products

1

Pin Configuration

19-2175; Rev 3; 5/11

Ordering Information

*

EP = Exposed pad.

+

Denotes a lead(Pb)-free/RoHS-compliant package.

/V denotes an automotive qualified part.

Pin-Compatible Versions table at end of data sheet.

PART

TEMP

RANGE

MAX1185ECM -40°C to +85°C 48 TQFP-EP*

MAX1185ECM+ -40°C to +85°C 48 TQFP-EP*

MAX1185ECM/V+ -40°C to +85°C 48 TQFP-EP*

PIN-PACKAGE

REFN

REFP

REFIN

REFOUT

D9A/B

D8A/B

D7A/B

D6A/B

D5A/B

D4A/B

D3A/B

D2A/B

4847464544434241403938

COM

1

V

2

DD

GND

3

INA+

4

INA-

5

V

6

DD

GND

7

INB-

8

INB+

9

GND

10

V

11

DD

CLK

12

1314151617181920212223

GND

NOTE: THE PIN 1 INDICATOR FOR LEAD-FREE
PACKAGES IS REPLACED BY A "+" SIGN.

EP

DDVDD

V

MAX1185

PD

T/B

GND

SLEEP

48 TQFP-EP

OE

N.C.

N.C.

N.C.

37

24

N.C.

36

D1A/B
D0A/B

35

OGND

34

OV

33

DD

OV

32

DD

OGND

31

A/B

30

N.C.

29

N.C.

28

N.C.

27

N.C.

26

N.C.

25

MAX1185

Dual 10-Bit, 20Msps, 3V, Low-Power ADC with
Internal Reference and Multiplexed Parallel Outputs

2 _______________________________________________________________________________________

ABSOLUTE MAXIMUM RATINGS

ELECTRICAL CHARACTERISTICS

(VDD= 3V, OVDD= 2.5V, 0.1µF and 1µF capacitors from REFP, REFN, and COM to GND; REFOUT connected to REFIN through a
10kΩ resistor, V

IN

= 2Vp-p (differential w.r.t. COM), CL= 10pF at digital outputs (Note 1), f

CLK

= 20MHz, TA= T

MIN

to T

MAX

, unless

otherwise noted. Typical values are at T

A

= +25°C.) (Note 2)

Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.

VDD, OVDDto GND ...............................................-0.3V to +3.6V

OGND to GND.......................................................-0.3V to +0.3V

INA+, INA-, INB+, INB- to GND ...............................-0.3V to V

DD

REFIN, REFOUT, REFP, REFN, COM,

CLK to GND............................................-0.3V to (V

DD

+ 0.3V)

OE, PD, SLEEP, T/B, D9A/B–D0A/B,

A/B to OGND .......................................-0.3V to (OV

DD

+ 0.3V)

Continuous Power Dissipation (T

A

= +70°C)
48-Pin TQFP-EP (derate 30.4mW/°C

above +70°C)............................................................2430mW

Operating Temperature Range ...........................-40°C to +85°C

Junction Temperature......................................................+150°C

Storage Temperature Range .............................-60°C to +150°C

Lead Temperature (soldering, 10s) .................................+300°C

Soldering Temperature (reflow)

Lead(Pb)-free..............................................................+260°C

Containing lead(Pb) ....................................................+240°C

DC ACCURACY

Resolution 10 Bits

Integral Nonlinearity INL fIN = 7.5MHz ±0.5 ±1.5 LSB

Differential Nonlinearity DNL fIN = 7.5MHz, no missing codes guaranteed ±0.25 ±1.0 LSB

Offset Error < ±1 ±1.9 % FS

Gain Error 0 ±2% FS

ANALOG INPUT

Differential Input Voltage
Range

Common-Mode Input Voltage
Range

Input Resistance R

Input Capacitance C

CONVERSION RATE

Maximum Clock Frequency f

Data Latency

DYNAMIC CHARACTERISTICS

Signal-to-Noise Ratio
(Note 3)

Signal-to-Noise and Distortion
(Note 3)

Spurious-Free Dynamic Range
(Note 3)

PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS

V

DIFF

V

CLK

SNR

SINAD

SFDR

Differential or single-ended inputs ±1.0 V

CM

Switched capacitor load 100 kΩ

IN

IN

CHA 5

CHB 5.5

f

INA or B

f

INA or B

f

INA or B

f

INA or B

f

INA or B

f

INA or B

= 7.5MHz, TA = +25°C 57.3 59.5

= 12MHz 59.4

= 7.5MHz, TA = +25°C 57 59.4

= 12MHz 59.2

= 7.5MHz, TA = +25°C 64 74

= 12MHz 72

20 MHz

VDD/2

± 0.5

5pF

V

Clock

cycles

dB

dB

dBc

MAX1185

Dual 10-Bit, 20Msps, 3V, Low-Power ADC with

Internal Reference and Multiplexed Parallel Outputs

_______________________________________________________________________________________ 3

ELECTRICAL CHARACTERISTICS (continued)

(VDD= 3V, OVDD= 2.5V, 0.1µF and 1µF capacitors from REFP, REFN, and COM to GND; REFOUT connected to REFIN through a
10kΩ resistor, V

IN

= 2Vp-p (differential w.r.t. COM), CL= 10pF at digital outputs (Note 1), f

CLK

= 20MHz, TA= T

MIN

to T

MAX

, unless

otherwise noted. Typical values are at T

A

= +25°C.) (Note 2)

Total Harmonic Distortion
(First 4 Harmonics) (Note 3)

Third-Harmonic Distortion
(Note 3)

Intermodulation Distortion IMD

Small-Signal Bandwidth Input at -20dBFS, differential inputs 500 MHz

Full-Power Bandwidth FPBW Input at -0.5dBFS, differential inputs 400 MHz

Aperture Delay t

Aperture Jitter t

Overdrive Recovery Time For 1.5x full-scale input 2 ns

Differential Gain ±1%

Differential Phase ±0.25 D egr ees

Output Noise INA+ = INA- = INB+ = INB- = COM 0.2 LSB

INTERNAL REFERENCE

Reference Output Voltage REFOUT

Reference Temperature
Coefficient

Load Regulation 1.25 mV/mA

BUFFERED EXTERNAL REFERENCE (V

REFIN Input Voltage V

Positive Reference Output
Voltage

Negative Reference Output
Voltage

Differential Reference Output
Voltage Range

REFIN Resistance R

PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS

f

REF

REFIN

INA or B

f

INA or B

f

INA or B

f

INA or B

f

INA or B

f

I N A o r B

= 2.048V)

REF

THD

HD3

AD

AJ

TC

REFIN

V

REFP

V

REFN

ΔVREF ΔV

REFIN

= 7.5MHz, TA = +25°C -72 -64

= 12MHz -71

= 7.5MHz -74

= 12MHz -72

= 11.9852MHz at -6.5dBFS,
= 12.8934M H z at - 6.5d BFS ( N ote 4)

= V

REFP

- V

REFN

-76 dBc

1ns

2ps

2.048
±3%

60 ppm/°C

2.048 V

2.012 V

0.988 V

0.95 1.024 1.10 V

> 50 MΩ

dBc

dBc

RMS

RMS

V

MAX1185

Dual 10-Bit, 20Msps, 3V, Low-Power ADC with
Internal Reference and Multiplexed Parallel Outputs

4 _______________________________________________________________________________________

ELECTRICAL CHARACTERISTICS (continued)

(VDD= 3V, OVDD= 2.5V, 0.1µF and 1µF capacitors from REFP, REFN, and COM to GND; REFOUT connected to REFIN through a
10kΩ resistor, V

IN

= 2Vp-p (differential w.r.t. COM), CL= 10pF at digital outputs (Note 1), f

CLK

= 20MHz, TA= T

MIN

to T

MAX

, unless

otherwise noted. Typical values are at T

A

= +25°C.) (Note 2)

Maximum REFP, COM Source
Current

Maximum REFP, COM Sink
Current

Maximum REFN Source Current I

Maximum REFN Sink Current I

UNBUFFERED EXTERNAL REFERENCE (V

REFP, REFN Input Resistance

Differential Reference Input
Voltage

COM Input Voltage V

REFP Input Voltage V

REFN Input Voltage V

DIGITAL INPUTS (CLK, PD, OE, SLEEP, T/B)

Input High Threshold V

Input Low Threshold V

Input Hysteresis V

Input Leakage

Input Capacitance C

DIGITAL OUTPUTS (D0A/B–D9A/B, A/B)

Output-Voltage Low V

Output-Voltage High V

Three-State Leakage Current I

Three-State Output Capacitance C

PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS

I

SOURCE

I

SINK

SOURCE

SINK

R

REFP

R

REFN

ΔV

REF

COM

REFP

REFN

IH

IL

HYST

I

IH

I

IL

IN

OLISINK

OH

LEAK

OUT

= AGND, reference voltage applied to REFP, REFN, and COM)

REFIN

,

Measured between REFP and COM, and
REFN and COM

ΔV

= V

REF

CLK

PD, OE, SLEEP, T/B

REFP

- V

REFN

0.8

x V

0.8

x OV

DD

CLK

PD, OE, SLEEP, T/B

VIH = OV

DD

or V

(CLK) ±5

DD

VIL = 0 ±5

= -200µA 0.2 V

OV

I

SOURCE

OE = OV
OE = OV

= 200µA

DD

DD

DD

- 0.2

5mA

-250 µA

250 µA

-5 mA

4kΩ

1.024

±10%

VDD/2
±10%

V

+

COM

ΔV

/2

REF

V

-

COM

/2

ΔV

REF

DD

0.2

x V

DD

0.2

x OV

DD

0.1 V

5pF

±10 µA

5pF

V

V

V

V

V

V

µA

V

MAX1185

Dual 10-Bit, 20Msps, 3V, Low-Power ADC with

Internal Reference and Multiplexed Parallel Outputs

_______________________________________________________________________________________ 5

ELECTRICAL CHARACTERISTICS (continued)

(VDD= 3V, OVDD= 2.5V, 0.1µF and 1µF capacitors from REFP, REFN, and COM to GND; REFOUT connected to REFIN through a
10kΩ resistor, V

IN

= 2Vp-p (differential w.r.t. COM), CL= 10pF at digital outputs (Note 1), f

CLK

= 20MHz, TA= T

MIN

to T

MAX

, unless

otherwise noted. Typical values are at T

A

= +25°C.) (Note 2)

Note 1: Equivalent dynamic performance is obtainable over full OVDDrange with reduced CL.
Note 2: Specifications at ≥ +25°C are guaranteed by production test and < +25°C are guaranteed by design and characterization.
Note 3: SNR, SINAD, THD, SFDR, and HD3 are based on an analog input voltage of -0.5dBFS referenced to a ±1.024V full-scale

input voltage range.

Note 4: Intermodulation distortion is the total power of the intermodulation products relative to the individual carrier. This number is

6dB or better, if referenced to the two-tone envelope.

Note 5: Digital outputs settle to V

IH

, VIL. Parameter guaranteed by design.

Note 6: With REFIN driven externally, REFP, COM, and REFN are left unconnected while powered down.

POWER REQUIREMENTS

Analog Supply Voltage Range V

Output Supply Voltage Range OV

Analog Supply Current I

Output Supply Current I

Power Dissipation PDISS

Power-Supply Rejection Ratio PSRR

TIMING CHARACTERISTICS

CLK Rise to CHA Output Data
Valid

CLK Fall to CHB Output Data
Valid

Clock Rise/Fall to A/B Rise/Fall
Time

Output Enable Time t

Output Disable Time t

CLK Pulse Width High t

CLK Pulse Width Low t

Wake-Up Time t

CHANNEL-TO-CHANNEL MATCHING

Crosstalk f

Gain Matching f

Phase Matching f

PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS

DD

DD

Operating, f

VDD

OVDD

t

DOA

t

DOB

t

DA/B

ENABLE

DISABLE

CH

WAKE

Sleep mode 2.8
Shutdown, clock idle, PD = OE = OV

Operating, CL = 15pF,
f

INA or B

Sleep mode 100
Shutdown, clock idle, PD = OE = OV

Operating, f

Sleep mode 8.4
Shutdown, clock idle, PD = OE = OV

Offset ±0.2 mV/V

Gain ±0.1 %/V

Figure 3 (Note 5) 5 8 ns

Figure 3 (Note 5) 5 8 ns

Figure 4 10 ns

Figure 4 1.5 ns

Figure 3, clock period: 50ns

Figure 3, clock period: 50ns

CL

Wake-up from sleep mode (Note 6) 0.51

Wake-up from shutdown (Note 6) 1.5

INA or B

INA or B

INA or B

= 7.5MHz at -0.5dBFS 35 50

INA or B

DD

= 7.5MHz at -0.5dBFS

DD

= 7.5MHz at -0.5dBFS 105 150

INA or B

DD

= 7.5MHz at -0.5dBFS -70 dB

= 7.5MHz at -0.5dBFS 0.02 ±0.2 dB

= 7.5MHz at -0.5dBFS 0.25 D eg r ees

2.7 3.0 3.6 V

1.7 2.5 3.6 V

115µA

9mA

210

345µW

6ns

25 ± 7.5

25 ± 7.5

mA

µA

mW

ns

ns

µs

MAX1185

Dual 10-Bit, 20Msps, 3V, Low-Power ADC with
Internal Reference and Multiplexed Parallel Outputs

6 _______________________________________________________________________________________

Typical Operating Characteristics

(VDD= 3V, OVDD= 2.5V, V

REFIN

= 2.048V, differential input at -0.5dBFS, f

CLK

= 20MHz, CL≈ 10pF, TA= +25°C, unless otherwise noted.)

-100

-80

-90

-60

-70

-40

-50

-30

-10

-20

0

023415679810

FFT PLOT CHA (DIFFERENTIAL INPUT,

8192-POINT DATA RECORD)

MAX1185 toc01

ANALOG INPUT FREQUENCY (MHz)

AMPLITUDE (dB)

CHA

f

CLK

= 20.0005678MHz

f

INA

= 5.9742906MHz

f

INB

= 7.5343935MHz

A

INA

= -0.525dBFS

HD3

HD2

-100

-80

-90

-60

-70

-40

-50

-30

-10

-20

0

0 23415679810

FFT PLOT CHB (DIFFERENTIAL INPUT,

8192-POINT DATA RECORD)

MAX1185 toc02

ANALOG INPUT FREQUENCY (MHz)

AMPLITUDE (dB)

CHB

f

CLK

= 20.0005678MHz

f

INA

= 5.9742906MHz

f

INB

= 7.5243935MHz

A

INA

= -0.462dBFS

HD3

HD2

-100

-80

-90

-60

-70

-40

-50

-30

-10

-20

0

0 2341 567 9810

FFT PLOT CHA (DIFFERENTIAL INPUT,

8192-POINT DATA RECORD)

MAX1185 toc03

ANALOG INPUT FREQUENCY (MHz)

AMPLITUDE (dB)

CHA

f

CLK

= 20.0005678MHz

f

INA

= 7.5343935MHz

f

INB

= 11.9852035MHz

A

INA

= -0.489dBFS

HD3

HD2

-100

-80

-90

-60

-70

-40

-50

-30

-10

-20

0

02341 567 9810

FFT PLOT CHB (DIFFERENTIAL INPUT,

8192-POINT DATA RECORD)

MAX1185 toc04

ANALOG INPUT FREQUENCY (MHz)

AMPLITUDE (dB)

CHB

f

CLK

= 20.0005678MHz

f

INA

= 7.5343935MHz

f

INB

= 11.9852035MHz

A

INA

= -0.471dBFS

HD3

HD2

-100

-80

-90

-60

-70

-40

-50

-30

-10

-20

0

0 2341 567 9810

TWO-TONE IMD PLOT (DIFFERENTIAL INPUT,

8192-POINT DATA RECORD)

MAX1185 toc05

ANALOG INPUT FREQUENCY (MHz)

AMPLITUDE (dB)

IM2

IM3

IM3

f

CLK

= 20.0005678MHz

f

IN1

= 11.9852035MHz

f

IN2

= 12.8934324MHz

A

IN

= -6.5dBFS

f

IN2

f

IN1

57

56

55

59

58

60

61

0 5 10 15 20 25 30 35 40 45

SIGNAL-TO-NOISE RATIO

vs. ANALOG INPUT FREQUENCY

MAX1185 toc06

ANALOG INPUT FREQUENCY (MHz)

SNR (dB)

CHA

CHB

62

60

58

54

56

0 5 10 15 20 25 30 35 40 45

SIGNAL-TO-NOISE AND DISTORTION

vs. ANALOG INPUT FREQUENCY

MAX1185 toc07

ANALOG INPUT FREQUENCY (MHz)

SINAD (dB)

CHB

CHA

-72

-76

-80

-68

-64

-60

TOTAL HARMONIC DISTORTION
vs. ANALOG INPUT FREQUENCY

MAX1185 toc08

ANALOG INPUT FREQUENCY (MHz)

THD (dBc)

0 5 10 15 20 25 30 35 40 45

CHA

CHB

60

64

72

68

76

80

SPURIOUS-FREE DYNAMIC RANGE

vs. ANALOG INPUT FREQUENCY

MAX1185 toc09

ANALOG INPUT FREQUENCY (MHz)

SFDR (dBc)

0 5 10 15 20 25 30 35 40 45

CHA

CHB

MAX1185

Dual 10-Bit, 20Msps, 3V, Low-Power ADC with

Internal Reference and Multiplexed Parallel Outputs

_______________________________________________________________________________________

7

Typical Operating Characteristics (continued)

(VDD= 3V, OVDD= 2.5V, V

REFIN

= 2.048V, differential input at -0.5dBFS, f

CLK

= 20MHz, CL≈ 10pF, TA= +25°C, unless otherwise noted

-8

-4

-6

0

-2

4

2

6

1 10 100 1000

FULL-POWER INPUT BANDWIDTH

vs. ANALOG INPUT FREQUENCY, SINGLE-ENDED

MAX1185 toc10

ANALOG INPUT FREQUENCY (MHz)

GAIN (dB)

-8

-4

-6

0

-2

4

2

6

1 10 100 1000

SMALL-SIGNAL INPUT BANDWIDTH

vs. ANALOG INPUT FREQUENCY, SINGLE-ENDED

MAX1185 toc11

ANALOG INPUT FREQUENCY (MHz)

GAIN (dB)

VIN = 100mV

P-P

35

45

40

55

50

60

65

-20 0

SIGNAL-TO-NOISE RATIO

vs. ANALOG INPUT POWER (f

IN

= 7.53MHz)

MAX1185 toc12

ANALOG INPUT POWER (dBFS)

SNR (dB)

-12-16 -8 -4

35

45

40

55

50

60

65

-20 0

SIGNAL-TO-NOISE PLUS DISTORTION

vs. ANALOG INPUT POWER (f

IN

= 7.53MHz)

MAX1185 toc13

ANALOG INPUT POWER (dBFS)

SINAD (dB)

-12-16 -8 -4

-85

-80

-75

-65

-70

-60

-55

-20 -12-16 -8 -4 0

TOTAL HARMONIC DISTORTION

vs. ANALOG INPUT POWER (f

IN

= 7.53MHz)

MAX1185 toc14

ANALOG INPUT POWER (dBFS)

THD (dBc)

60

55

75

70

65

85

80

90

-20 -12-16 -8 -4 0

SPURIOUS-FREE DYNAMIC RANGE

vs. ANALOG INPUT POWER (f

IN

= 7.53MHz)

MAX1185 toc15

ANALOG INPUT POWER (dBFS)

SFDR (dBc)

-0.3

-0.2

-0.1

0

0.1

0.2

0.3

0 256128 384 512 640 768 896 1024

INTEGRAL NONLINEARITY

(BEST END-POINT FIT)

MAX1185 toc16

DIGITAL OUTPUT CODE

INL (LSB)

-0.3

-0.2

-0.1

0

0.1

0.2

0.3

0 256128 384 512 640 768 896 1024

DIFFERENTIAL NONLINEARITY

MAX1185 toc17

DIGITAL OUTPUT CODE

DNL (LSB)

-0.1

-0.2

0.1

0

0.3

0.2

0.4

-40 85

GAIN ERROR vs. TEMPERATURE

MAX1185 toc18

TEMPERATURE (°C)

GAIN ERROR (%FS)

10-15 35 60

CHB

CHA

MAX1185

Dual 10-Bit, 20Msps, 3V, Low-Power ADC with
Internal Reference and Multiplexed Parallel Outputs

8 _______________________________________________________________________________________

Typical Operating Characteristics (continued)

(VDD= 3V, OVDD= 2.5V, V

REFIN

= 2.048V, differential input at -0.5dBFS, f

CLK

= 20MHz, CL≈ 10pF, TA= +25°C, unless otherwise noted.)

OFFSET ERROR vs. TEMPERATURE

0.2

0.1

0

-0.1

-0.2

OFFSET ERROR (%FS)

-0.3

-0.4

-40 85

0.25
OE = PD = OV

0.20

0.15

(μA)

VDD

I

0.10

CHA

TEMPERATURE (°C)

ANALOG POWER-DOWN CURRENT

vs. ANALOG SUPPLY VOLTAGE

DD

CHB

10-15 35 60

MAX1185 toc19

MAX1185 toc22

ANALOG SUPPLY CURRENT

vs. ANALOG SUPPLY VOLTAGE

38

37

36

(mA)

VDD

I

35

34

33

2.70 3.002.85 3.15 3.30 3.45 3.60
VDD (V)

SNR/SINAD, -THD/SFDR
vs. CLOCK DUTY CYCLE

80

SFDR

74

68

62

SNR

f

INA/B

THD

= 7.53MHz

MAX1185 toc20

MAX1185 toc23

ANALOG SUPPLY CURRENT

vs. TEMPERATURE

38

36

34

(mA)

VDD

I

32

30

28

-40 10-15 35 60 85
TEMPERATURE (°C)

INTERNAL REFERENCE VOLTAGE

vs. ANALOG SUPPLY VOLTAGE

2.0100

2.0080

2.0060

(V)

REFOUT

V

2.0040

MAX1185 toc21

MAX1185 toc24

0.05

0

2.70 3.002.85 3.15 3.30 3.45 3.60
VDD (V)

SNR/SINAD, -THD/SFDR (dB, dBc)

50

35 40 45 50 55 60 65 70

CLOCK DUTY CYCLE (%)

SINAD

2.0020

2.0000

2.70 3.002.85 3.15 3.30 3.45 3.60

56

INTERNAL REFERENCE VOLTAGE

2.014

vs. TEMPERATURE

2.010

2.006

(V)

REOUT

V

2.002

1.998

1.994

-40 85

10-15 35 60

TEMPERATURE (°C)

MAX1185 toc25

OUTPUT NOISE HISTOGRAM (DC INPUT)

70,000

63,000

56,000

49,000

42,000

35,000

COUNTS

28,000

21,000

14,000

7,000

0

0

N-2

64,515

869

N

N-1

DIGITAL OUTPUT CODE

152

N+1

VDD (V)

MAX1185 toc26

0

N+2

MAX1185

Dual 10-Bit, 20Msps, 3V, Low-Power ADC with

Internal Reference and Multiplexed Parallel Outputs

_______________________________________________________________________________________

9

Pin Description

PIN NAME FUNCTION

1 COM Common-Mode Voltage Input/Output. Bypass to GND with a ≥ 0.1µF capacitor.

2, 6, 11, 14, 15 V

3, 7, 10, 13, 16 GND Analog Ground

4 INA+ Channel A Positive Analog Input. For single-ended operation, connect signal source to INA+.

5 INA- Channel A Negative Analog Input. For single-ended operation, connect INA- to COM.

8 INB- Channel B Negative Analog Input. For single-ended operation, connect INB- to COM.

9 INB+ Channel B Positive Analog Input. For single-ended operation, connect signal source to INB+.

12 CLK Converter Clock Input

17 T/B

18 SLEEP

19 PD

20 OE

21–29 N.C. Do not connect.

30 A/B

31, 34 OGND Output Driver Ground

32, 33 OV

35 D0A/B

36 D1A/B

37 D2A/B

38 D3A/B

39 D4A/B

40 D5A/B

DD

DD

Analog Supply Voltage. Bypass each supply pin to GND with a 0.1µF capacitor. Analog
supply accepts a 2.7V to 3.6V input range.

T/B selects the ADC digital output format.
High: Two’s complement.
Low: Straight offset binary.

Sleep Mode Input.
High: Deactivates the two ADCs, but leaves the reference bias circuit active.
Low: Normal operation.

Power-Down Input.
High: Power-down mode.
Low: Normal operation.

Output Enable Input.
High: Digital outputs disabled.
Low: Digital outputs enabled.

A/B Data Indicator. This digital output indicates CHA data (A/B = 1) or CHB data (A/B = 0)
to be present on the output. A/B follows the external clock signal with typically 6ns delay.

Output Driver Supply Voltage. Bypass each supply pin to OGND with a 0.1µF capacitor. Output
driver supply accepts a 1.7V to 3.6V input range.

Three-State Digital Output, Bit 0 (LSB). Depending on status of A/B, output data reflects
channel A or channel B data.

Three-State Digital Output, Bit 1. Depending on status of A/B, output data reflects channel A
or channel B data.

Three-State Digital Output, Bit 2. Depending on status of A/B, output data reflects channel A
or channel B data.

Three-State Digital Output, Bit 3. Depending on status of A/B, output data reflects channel A
or channel B data.

Three-State Digital Output, Bit 4. Depending on status of A/B, output data reflects channel A
or channel B data.

Three-State Digital Output, Bit 5. Depending on status of A/B, output data reflects channel A
or channel B data.

Detailed Description

The MAX1185 uses a nine-stage, fully-differential,
pipelined architecture (Figure 1) that allows for high­speed conversion while minimizing power consumption.
Samples taken at the inputs move progressively through
the pipeline stages every half-clock cycle. Including the
delay through the output latch, the total clock-cycle
latency is five clock cycles.

1.5-bit (2-comparator) flash ADCs convert the held input
voltages into a digital code. The digital-to-analog con­verters (DACs) convert the digitized results back into
analog voltages, which are then subtracted from the
original held input signals. The resulting error signals
are then multiplied by two and the residues are passed
along to the next pipeline stages, where the process is
repeated until the signals have been processed by all
nine stages. Digital error correction compensates for
ADC comparator offsets in each of these pipeline
stages and ensures no missing codes.

Both input channels are sampled on the rising edge of
the clock and the resulting data is multiplexed at the
output. CHA data is updated on the rising edge (five
clock cycles later) and CHB data is updated on the
falling edge (5.5 clock cycles later) of the clock signal.
The A/B indicator follows the clock signal with a typical
delay time of 6ns and remains high when CHA data is
updated and low when CHB data is updated.

Input Track-and-Hold (T/H) Circuits

Figure 2 displays a simplified functional diagram of the
input track-and-hold (T/H) circuits in both track and hold
mode. In track mode, switches S1, S2a, S2b, S4a, S4b,
S5a, and S5b are closed. The fully differential circuits
sample the input signals onto the two capacitors (C2a
and C2b) through switches S4a and S4b. S2a and S2b
set the common mode for the amplifier input, and open
simultaneously with S1, sampling the input waveform.
Switches S4a and S4b are then opened before switches
S3a and S3b connect capacitors C1a and C1b to the out­put of the amplifier and switch S4c is closed. The result­ing differential voltages are held on capacitors C2a and
C2b. The amplifiers are used to charge capacitors C1a
and C1b to the same values originally held on C2a and
C2b. These values are then presented to the first stage
quantizers and isolate the pipelines from the fast-chang­ing inputs. The wide input bandwidth T/H amplifiers allow
the MAX1185 to track and sample/hold analog inputs of
high frequencies (> Nyquist). Both ADC inputs (INA+,
INB+, INA-, and INB-) can be driven either differentially or
single-ended. Match the impedance of INA+ and INA- as
well as INB+ and INB- and set the common-mode volt­age to midsupply (VDD/2) for optimum performance.

MAX1185

Dual 10-Bit, 20Msps, 3V, Low-Power ADC with
Internal Reference and Multiplexed Parallel Outputs

10 ______________________________________________________________________________________

Pin Description (continued)

PIN NAME FUNCTION

41 D6A/B

42 D7A/B

43 D8A/B

44 D9A/B

45 REFOUT

46 REFIN Reference Input. V

47 REFP

48 REFN

— EP Exposed Pad. Connect to analog ground.

Three-State Digital Output, Bit 6. Depending on status of A/B, output data reflects channel A
or channel B data.

Three-State Digital Output, Bit 7. Depending on status of A/B, output data reflects channel A
or channel B data.

Three-State Digital Output, Bit 8. Depending on status of A/B, output data reflects channel A
or channel B data.

Three-State Digital Output, Bit 9 (MSB). Depending on status of A/B, output data reflects
channel A or channel B data.

Internal Reference Voltage Output. May be connected to REFIN through a resistor or a
resistor-divider.

= 2 x (V

REFIN

Positive Reference Input/Output. Conversion range is ± (V
a > 0.1µF capacitor.

Negative Reference Input/Output. Conversion range is ± (V
a > 0.1µF capacitor.

REFP

- V

). Bypass to GND with a > 1nF capacitor.

REFN

- V

REFP

REFN

- V

REFP

REFN

). Bypass to GND with

). Bypass to GND with

MAX1185

Dual 10-Bit, 20Msps, 3V, Low-Power ADC with

Internal Reference and Multiplexed Parallel Outputs

______________________________________________________________________________________ 11

Figure 1. Pipelined Architecture—Stage Blocks

Figure 2. MAX1185 T/H Amplifiers

V

IN

T/H

Σ

V

OUT

x2

V

IN

T/H

Σ

V

OUT

x2

FLASH

ADC

T/H

V

INA

DAC

1.5 BITS

STAGE 1 STAGE 2

DIGITAL CORRECTION LOGIC

10

S4a

INA+

S4c

STAGE 8 STAGE 9

INTERNAL BIAS

S2a

C2a

S1

2-BIT FLASH

ADC

OUTPUT

MULTIPLEXER

D0A/B–D9A/B

C1a

COM

S5a

FLASH

ADC

T/H

V

INB

10

S3a

DAC

1.5 BITS

STAGE 1 STAGE 2

DIGITAL CORRECTION LOGIC

OUT

2-BIT FLASH

ADC

STAGE 8 STAGE 9

10

INA-

INB+

INB-

S4b

S4a

S4b

S4c

C2b

INTERNAL BIAS

INTERNAL BIAS

S2a

C2a

S1

C2b

INTERNAL BIAS

S2b

S2b

C1b

C1a

C1b

COM

COM

COM

S5b

S5a

S5b

S3b

S3a

S3b

OUT

OUT

OUT

HOLD

TRACK

HOLD

TRACK

MAX1185

CLK

INTERNAL
NONOVERLAPPING
CLOCK SIGNALS

MAX1185

Dual 10-Bit, 20Msps, 3V, Low-Power ADC with
Internal Reference and Multiplexed Parallel Outputs

12 ______________________________________________________________________________________

Analog Inputs and Reference

Configurations

The full-scale range of the MAX1185 is determined by the
internally generated voltage difference between REFP
(VDD/2 + V

REFIN

/4) and REFN (VDD/2 - V

REFIN

/4). The
full-scale range for both on-chip ADCs is adjustable
through the REFIN pin, which is provided for this purpose.

REFOUT, REFP, COM (VDD/2), and REFN are internally
buffered low-impedance outputs.

The MAX1185 provides three modes of reference operation:

• Internal reference mode

• Buffered external reference mode

• Unbuffered external reference mode

In internal reference mode, connect the internal refer­ence output REFOUT to REFIN through a resistor (e.g.,
10kΩ) or resistor-divider, if an application requires a
reduced full-scale range. For stability and noise filtering
purposes, bypass REFIN with a > 10nF capacitor to
GND. In internal reference mode, REFOUT, COM, REFP,
and REFN become low-impedance outputs.

In buffered external reference mode, adjust the reference
voltage levels externally by applying a stable and accu­rate voltage at REFIN. In this mode, COM, REFP, and
REFN become outputs. REFOUT may be left open or con­nected to REFIN through a > 10kΩ resistor.

In unbuffered external reference mode, connect REFIN to
GND. This deactivates the on-chip reference buffers for
REFP, COM, and REFN. With their buffers shut down,
these nodes become high impedance and may be driven
through separate, external reference sources.

Clock Input (CLK)

The MAX1185’s CLK input accepts CMOS-compatible
clock signals. Since the interstage conversion of the
device depends on the repeatability of the rising and
falling edges of the external clock, use a clock with low jit­ter and fast rise and fall times (< 2ns). In particular, sam­pling occurs on the rising edge of the clock signal,
requiring this edge to provide lowest possible jitter. Any
significant aperture jitter would limit the SNR performance
of the on-chip ADCs as follows:

SNRdB= 20 x log10(1/[2π x fINx tAJ])

where fINrepresents the analog input frequency and t

AJ

is the time of the aperture jitter.

Clock jitter is especially critical for undersampling appli­cations. The clock input should always be considered as
an analog input and routed away from any analog input
or other digital signal lines.

The MAX1185 clock input operates with a voltage thresh­old set to V

DD

/2. Clock inputs with a duty cycle other
than 50%, must meet the specifications for high and low
periods as stated in the

Electrical Characteristics

.

System Timing Requirements

Figure 3 shows the relationship between clock and
analog input, A/B indicator, and the resulting CHA/CHB
data output. CHA and CHB data are sampled on the
rising edge of the clock signal. Following the rising
edge of the 5th clock cycles, the digitized value of the
original CHA sample is presented at the output, fol­lowed one half-clock cycle later by the digitized value
of the original CHB sample.

A channel selection signal (A/B indicator) allows the user
to determine which output data represents which input
channel. With A/B = 1, digitized data from CHA is present
at the output and with A/B = 0 digitized data from CHB is
present.

Digital Output Data, Output Data Format

Selection (T/B), Output Enable (

OE

), Channel

Selection (A/B)

All digital outputs, D0A/B–D9A/B (CHA or CHB data) and
A/B are TTL/CMOS logic-compatible. The output coding
can be chosen to be either offset binary or two’s comple­ment (Table 1) controlled by a single pin (T/B). Pull T/B
low to select offset binary and high to activate two’s com­plement output coding. The capacitive load on the digital
outputs D0A/B–D9A/B should be kept as low as possible
(< 15pF), to avoid large digital currents that could feed
back into the analog portion of the MAX1185, thereby
degrading its dynamic performance. Using buffers on
the digital outputs of the ADCs can further isolate the
digital outputs from heavy capacitive loads. To further
improve the dynamic performance of the MAX1185,
small-series resistors (e.g., 100Ω) may be added to the
digital output paths close to the MAX1185.

Figure 4 displays the timing relationship between output
enable and data output valid as well as power­down/wake-up and data output valid.

Power-Down (PD) and Sleep

(SLEEP) Modes

The MAX1185 offers two power-save modes—sleep
and full power-down mode. In sleep mode (SLEEP = 1),
only the reference bias circuit is active (both ADCs are
disabled), and current consumption is reduced to

2.8mA.
To enter full power-down mode, pull PD high. With OE

simultaneously low, all outputs are latched at the last
value prior to the power-down. Pulling OE high forces
the digital outputs into a high-impedance state.

MAX1185

Dual 10-Bit, 20Msps, 3V, Low-Power ADC with

Internal Reference and Multiplexed Parallel Outputs

______________________________________________________________________________________ 13

Applications Information

Figure 5 depicts a typical application circuit containing
two single-ended to differential converters. The internal
reference provides a V

DDS

/2 output voltage for level
shifting purposes. The input is buffered and then split
to a voltage follower and inverter. One lowpass filter per
ADC suppresses some of the wideband noise associat­ed with high-speed operational amplifiers that follows

the amplifiers. The user may select the R

ISO

and C

IN

values to optimize the filter performance, to suit a par­ticular application. For the application in Figure 5, a
R

ISO

of 50Ω is placed before the capacitive load to
prevent ringing and oscillation. The 22pF CINcapacitor
acts as a small bypassing capacitor.

Using Transformer Coupling

An RF transformer (Figure 6) provides an excellent
solution to convert a single-ended source signal to a
fully differential signal, required by the MAX1185 for
optimum performance. Connecting the center tap of the
transformer to COM provides a V

DDS

/2 DC level shift to
the input. Although a 1:1 transformer is shown, a step­up transformer may be selected to reduce the drive
requirements. A reduced signal swing from the input
driver, such as an op amp, may also improve the over­all distortion.

In general, the MAX1185 provides better SFDR and
THD with fully differential input signals than single­ended drive, especially for very high input frequencies.
In differential input mode, even-order harmonics are
lower as both inputs (INA+, INA- and/or INB+, INB-) are
balanced, and each of the ADC inputs only requires
half the signal swing compared to single-ended mode.

Figure 3. Timing Diagram for Multiplexed Outputs

Figure 4. Output Timing Diagram

5 CLOCK-CYCLE LATENCY (CHA), 5.5 CLOCK-CYCLE LATENCY (CHB)

CHA

CHB

t

CLK

CLK

t

t

CL

CH

t

DOB

A/B CHB

t

DA/B

D0A/B-D9A/B D0B

CHA

D1A

t

DOA

CHB

D1B

CHA

D2A

CHB

D2B

CHA

D3A

OE

t

DISABLE

VALID DATA

HIGH
IMPEDANCEHIGH IMPEDANCE

OUTPUT

D0A/B–D9A/B

t

ENABLE

CHB

D3B

CHA

D4A

CHB

D4B

CHA

D5A

CHB

D5B

CHA

D6A

CHB

D6B

MAX1185

Dual 10-Bit, 20Msps, 3V, Low-Power ADC with
Internal Reference and Multiplexed Parallel Outputs

14 ______________________________________________________________________________________

Table 1. MAX1185 Output Codes For Differential Inputs

*

V

REF

= V

REFP

- V

REFN

Single-Ended AC-Coupled Input Signal

Figure 7 shows an AC-coupled, single-ended applica­tion. Amplifiers like the MAX4108 provide high speed,
high bandwidth, low noise, and low distortion to maintain
the integrity of the input signal.

Typical QAM Demodulation Application

The most frequently used modulation technique for digital
communications applications is probably the Quadrature
Amplitude Modulation (QAM). Typically found in spread­spectrum based systems, a QAM signal represents a
carrier frequency modulated in both amplitude and
phase. At the transmitter, modulating the baseband sig­nal with quadrature outputs, a local oscillator followed by
subsequent up-conversion can generate the QAM signal.
The result is an in-phase (I) and a quadrature (Q) carrier
component, where the Q component is 90 degree phase­shifted with respect to the in-phase component. At the
receiver, the QAM signal is divided down into it’s I and Q
components, essentially representing the modulation
process reversed. Figure 8 displays the demodulation
process performed in the analog domain, using the dual
matched 3.3V, 10-bit ADC MAX1185 and the MAX2451
quadrature demodulator to recover and digitize the I and
Q baseband signals. Before being digitized by the
MAX1185, the mixed down-signal components may be fil­tered by matched analog filters, such as Nyquist or
Pulse-Shaping filters. These remove any unwanted
images from the mixing process, thereby enhancing the
overall signal-to-noise (SNR) performance and minimizing
intersymbol interference.

Grounding, Bypassing, and

Board Layout

The MAX1185 requires high-speed board layout design
techniques. Locate all bypass capacitors as close as
possible to the device, preferably on the same side as
the ADC, using surface-mount devices for minimum
inductance. Bypass VDD, REFP, REFN, and COM with
two parallel 0.1µF ceramic capacitors and a 2.2µF
bipolar capacitor to GND. Follow the same rules to
bypass the digital supply (OVDD) to OGND. Multilayer
boards with separated ground and power planes pro­duce the highest level of signal integrity. Consider the
use of a split ground plane arranged to match the
physical location of the analog ground (GND) and the
digital output driver ground (OGND) on the ADC’s
package. The two ground planes should be joined at a
single point such that the noisy digital ground currents
do not interfere with the analog ground plane. The ideal
location of this connection can be determined experi­mentally at a point along the gap between the two
ground planes, which produces optimum results. Make
this connection with a low-value, surface-mount resistor
(1Ω to 5Ω), a ferrite bead, or a direct short. Alternatively,
all ground pins could share the same ground plane, if
the ground plane is sufficiently isolated from any noisy
digital systems ground plane (e.g., downstream output
buffer or DSP ground plane). Route high-speed digital
signal traces away from the sensitive analog traces of
either channel. Make sure to isolate the analog input
lines to each respective converter to minimize channel­to-channel crosstalk. Keep all signal lines short and
free of 90 degree turns.

DIFFERENTIAL INPUT

VOLTAGE*

V

x 511/512 +FULL SCALE - 1LSB 11 1111 1111 01 1111 1111

REF

V

x 1/512 + 1 LSB 10 0000 0001 00 0000 0001

REF

0 Bipolar Zero 10 0000 0000 00 0000 0000

- V

x 1/512 - 1 LSB 01 1111 1111 11 1111 1111

REF

-V

x 511/512 - FULL SCALE + 1 LSB 00 0000 0001 10 0000 0001

REF

-V

x 512/512 - FULL SCALE 00 0000 0000 10 0000 0000

REF

DIFFERENTIAL

INPUT

STRAIGHT OFFSET

BINARY

T/B = 0

TWO’S COMPLEMENT

T/B = 1

MAX1185

Dual 10-Bit, 20Msps, 3V, Low-Power ADC with

Internal Reference and Multiplexed Parallel Outputs

______________________________________________________________________________________ 15

Figure 5. Typical Application for Single-Ended-to-Differential Conversion

+5V

INPUT

MAX4108

300Ω

+5V

-5V

300Ω

0.1μF

0.1μF

300Ω

300Ω

300Ω

300Ω

300Ω

300Ω

600Ω

600Ω

0.1μF

0.1μF

0.1μF

MAX4108

-5V

+5V

MAX4108

-5V

+5V

MAX4108

-5V

600Ω

0.1μF

0.1μF

600Ω

0.1μF

0.1μF

0.1μF

0.1μF

LOWPASS FILTER

R

IS0

50Ω

LOWPASS FILTER

R

IS0

50Ω

LOWPASS FILTER

R

IS0

50Ω

C
22pF

C
22pF

C
22pF

INA+

IN

COM

INA-

IN

MAX1185

INB+

IN

+5V

MAX4108

-5V

600Ω

0.1μF

0.1μF

600Ω

INPUT

MAX4108

300Ω

+5V

-5V

300Ω

0.1μF

0.1μF

300Ω

600Ω

0.1μF

600Ω

300Ω

300Ω

LOWPASS FILTER

R

IS0

50Ω

C
22pF

INB-

IN

MAX1185

Dual 10-Bit, 20Msps, 3V, Low-Power ADC with
Internal Reference and Multiplexed Parallel Outputs

16 ______________________________________________________________________________________

Figure 6. Transformer-Coupled Input Drive

Static Parameter Definitions

Integral Nonlinearity (INL)

Integral nonlinearity is the deviation of the values on an
actual transfer function from a straight line. This straight
line can be either a best straight-line fit or a line drawn
between the endpoints of the transfer function, once
offset and gain errors have been nullified. The static lin­earity parameters for the MAX1185 are measured using
the best straight-line fit method.

Differential Nonlinearity (DNL)

Differential nonlinearity is the difference between an
actual step width and the ideal value of 1 LSB. A DNL
error specification of less than 1 LSB guarantees no
missing codes and a monotonic transfer function.

Dynamic Parameter

Definitions

Aperture Jitter

Figure 9 depicts the aperture jitter (tAJ), which is the
sample-to-sample variation in the aperture delay.

Aperture Delay

Aperture delay (tAD) is the time defined between the
falling edge of the sampling clock and the instant when
an actual sample is taken (Figure 9).

Signal-to-Noise Ratio (SNR)

For a waveform perfectly reconstructed from digital
samples, the theoretical maximum SNR is the ratio of
the full-scale analog input (RMS value) to the RMS

25Ω

INA+

22pF

0.1μF

V

IN

N.C.

MINICIRCUITS

0.1μF

V

IN

N.C.

MINICIRCUITS

1

2

1

2

3

T1

TT1–6

T1

TT1–6

6

5

2.2μF

43

6

5

2.2μF

4

0.1μF

25Ω

22pF

25Ω

22pF

0.1μF

25Ω

22pF

COM

INA-

MAX1185

INB+

INB-

quantization error (residual error). The ideal, theoretical
minimum analog-to-digital noise is caused by quantiza­tion error only and results directly from the ADC’s reso­lution (N-Bits):

SNR

dB[max]

= 6.02 x N + 1.76

In reality, there are other noise sources besides quanti­zation noise: thermal noise, reference noise, clock jitter,
etc. SNR is computed by taking the ratio of the RMS

signal to the RMS noise, which includes all spectral
components minus the fundamental, the first five har­monics, and the DC offset.

Signal-to-Noise Plus Distortion (SINAD)

SINAD is computed by taking the ratio of the RMS sig­nal to all spectral components minus the fundamental
and the DC offset.

MAX1185

Dual 10-Bit, 20Msps, 3V, Low-Power ADC with

Internal Reference and Multiplexed Parallel Outputs

______________________________________________________________________________________ 17______________________________________________________________________________________ 17

MAX1185

0.1μF

1kΩ

1kΩ

100Ω

100Ω

C

IN

22pF

C

IN

22pF

INB+

INB-

COM

INA+

INA-

0.1μF

R

ISO

50Ω

R

ISO

50Ω

REFP

REFN

V

IN

MAX4108

0.1μF

1kΩ

1kΩ

100Ω

100Ω

C

IN

22pF

C

IN

22pF

0.1μF

R

ISO

50Ω

R

ISO

50Ω

REFP

REFN

V

IN

MAX4108

Figure 7. Using an Op Amp for Single-Ended, AC-Coupled Input Drive

MAX1185

Total Harmonic Distortion (THD)

THD is typically the ratio of the RMS sum of the first four
harmonics of the input signal to the fundamental itself.
This is expressed as:

where V1is the fundamental amplitude, and V2through
V5are the amplitudes of the 2nd- through 5th-order
harmonics.

Spurious-Free Dynamic Range (SFDR)

SFDR is the ratio expressed in decibels of the RMS
amplitude of the fundamental (maximum signal compo­nent) to the RMS value of the next largest spurious
component, excluding DC offset.

Intermodulation Distortion (IMD)

The two-tone IMD is the ratio expressed in decibels of
either input tone to the worst 3rd-order (or higher) inter­modulation products. The individual input tone levels
are backed off by 6.5dB from full scale.

Dual 10-Bit, 20Msps, 3V, Low-Power ADC with
Internal Reference and Multiplexed Parallel Outputs

18 ______________________________________________________________________________________

Figure 8. Typical QAM Application, Using the MAX1185

Figure 9. T/H Aperture Timing

0°

90°

÷

8

DOWNCONVERTER

MAX2451

INA+

A/B

CHA AND CHB DATA
ALTERNATINGLY
AVAILABLE ON 10-BIT,
MULTIPLEXED
OUTPUT BUS

MAX1185

INA-

INB+
INB-

DSP

POST

PROCESSING

CLK

ANALOG

INPUT

SAMPLED

DATA (T/H)

t

AD

t

AJ

⎛

2

2

2

2

5

THD

=×

20

log

VVVV

+++

2

10

⎜
⎜
⎝

3

V

1

4

⎞
⎟

⎟
⎠

TRACK TRACK

T/H

HOLD

MAX1185

Dual 10-Bit, 20Msps, 3V, Low-Power ADC with

Internal Reference and Multiplexed Parallel Outputs

______________________________________________________________________________________ 19

Functional Diagram

Pin-Compatible Versions

V

GND

INA+

INA-

CLK

INB+

INB-

DD

T/H

T/H

PIPELINE

ADC

CONTROL

PIPELINE

ADC

REFERENCE

DEC

DEC

MUX

10

OUTPUT

DRIVERS

MAX1185

OGND
OV

DD

A/B

10

D0A/B–D9A/B

OE

T/B
PD
SLEEP

REFOUT

REFN

COM

REFP

REFIN

PART

RESOLUTION

(Bits)

MAX1190 10 120 Full duplex

MAX1180 10 105 Full duplex

MAX1181 10 80 Full duplex

MAX1182 10 65 Full duplex

MAX1183 10 40 Full duplex

MAX1186 10 40 Half duplex

MAX1184 10 20 Full duplex

MAX1185 10 20 Half duplex

MAX1198 8 100 Full duplex

MAX1197 8 60 Full duplex

MAX1196 8 40 Half duplex

MAX1195 8 40 Full duplex

SPEED GRADE

(Msps)

OUTPUT BUS

MAX1185

Dual 10-Bit, 20Msps, 3V, Low-Power ADC with
Internal Reference and Multiplexed Parallel Outputs

20 ______________________________________________________________________________________

PACKAGE TYPE PACKAGE CODE OUTLINE NO. LAND PATTERN NO.

48 TQFP-EP C48E+7

21-0065 90-0137

Package Information

For the latest package outline information and land patterns (footprints), go to www.maxim-ic.com/packages. Note that a “+”, “#”, or
“-” in the package code indicates RoHS status only. Package drawings may show a different suffix character, but the drawing per­tains to the package regardless of RoHS status.

Dual 10-Bit, 20Msps, 3V, Low-Power ADC with

Internal Reference and Multiplexed Parallel Outputs

MAX1185

Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are
implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.

Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 ____________________

21

© 2011 Maxim Integrated Products Maxim is a registered trademark of Maxim Integrated Products, Inc.

Revision History

REVISION

NUMBER

2 4/10 Added automotive qualified part to Ordering Information 1

3 5/11 Corrected pin 13 label in Pin Configuration 1

REVISION

DATE

DESCRIPTION

PAGES

CHANGED