Page 1
19-1109; Rev 0; 7/96
_______________General Description
The MAX101A ECL-compatible, 500Msps, 8-bit analogto-digital converter (ADC) allows accurate digitizing of
analog signals from DC to 250MHz (Nyquist frequency). Dual monolithic converters, driven by the track/hold
(T/H), operate on opposite clock edges (time interleaved). Designed with Maxim’s proprietary advanced
bipolar processes, the MAX101A contains a high-performance T/H amplifier and two quantizers in an 84-pin
ceramic flat pack.
The innovative design of the internal T/H ensures an
exceptionally wide 1.2GHz input bandwidth and aperture delay uncertainty of less than 2ps, resulting in a
high 7.0 effective bits at the Nyquist frequency. Special
comparator output design and decoding circuitry
reduce out-of-sequence code errors. The probability of
erroneous codes due to metastable states is reduced to
less than 1 error per 1015clock cycles. And, unlike other
ADCs that can have errors resulting in false full-scale or
zero-scale outputs, the MAX101A keeps the error magnitude to less than 1LSB.
The analog input is designed for either differential or
single-ended use with a ±250mV range. Sense pins for
the reference input allow full-scale calibration of the
input range or facilitate ratiometric use.
Phase adjustment is available to adjust the relative
sampling of the converter halves for optimizing converter performance. Input clock phasing is also available
for interleaving several MAX101As for higher effective
sampling rates.
____________________________Features
♦ 500Msps Conversion Rate
♦ 7.0 Effective Bits Typical at 250MHz
♦ 1.2GHz Analog Input Bandwidth
♦ Less than ±1/2LSB INL
♦ 50Ω Differential or Single-Ended Inputs
♦ ±250mV Input Signal Range
♦ Ratiometric Reference Inputs
♦ Dual Latched Output Data Paths
♦ Low Error Rate, Less than 10
-15
Metastable States
♦ 84-Pin Ceramic Flat Pack
________________________Applications
High-Speed Digital Instrumentation
High-Speed Signal Processing
Medical Systems
Radar/Signal Processing
High-Energy Physics
Communications
______________Ordering Information
MAX101A
500Msps, 8-Bit ADC with Track/Hold
________________________________________________________________
Maxim Integrated Products
1
DCLK
DCLK
PH
ADJ
TRK1
TRK1
BDATA
ADATA
AIN+
AIN-
CLK
CLK
VA
RTVARTS VA
RB
VA
RBS
VB
RT
VB
RTS
VB
RB
VB
RBS
L
A
T
C
H
E
S
L
A
T
C
H
E
S
STROBESTROBE
TRACK
AND
HOLD
FLASH CONVERTER
(8 -BIT)
FLASH CONVERTER
(8 -BIT)
8 8
8 8
MAX101A
B
U
F
F
E
R
_________________________________________________________Functional Diagram
For the latest literature: http://www.maxim-ic.com, or phone 1-800-998-8800
PART
MAX101ACFR* 0°C to +70°C
TEMP. RANGE PIN-PACKAGE
84 Ceramic Flat Pack
(with heatsink)
EVALUATION KIT MANUAL
AVAILABLE
*Contact factory for 84-pin ceramic flat pack without heatsink.
Page 2
MAX101A
500Msps, 8-Bit ADC with Track/Hold
2 _______________________________________________________________________________________
ABSOLUTE MAXIMUM RATINGS
ELECTRICAL CHARACTERISTICS
(VEE= -5.2V, VCC= +5V, RL= 100Ω to -2V, VART, VBRT= 0.95V, VARB, VBRB= -0.95V, TA= +25°C, unless otherwise noted.
T
MIN
to T
MAX
= 0°C to +70°C.) (Note 3)
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
Supply Voltages (Note 1)
V
CC
...........................................................................0V to +7V
V
EE
.............................................................................-7V to 0V
V
CC
- VEE.........................................................................+12V
Analog Input Voltage.............................................................±2V
Reference Voltage (VA
RT
, VBRT)...........................-0.3V to +1.5V
Reference Voltage (VA
RB
, VBRB)..........................-1.5V to +0.3V
Clock Input Voltage (V
IH
, VIL).....................................-2.3V to 0V
DIV10 Input Voltage (VIH, VIL).......................................VEEto 0V
Output Current, (I
OUT(max)
)
T
J
<100°C.......................................................................14mA
100°C < T
J
<120°C.........................................................12mA
Operating Temperature Range...............................0°C to +70°C
Operating Junction Temperature (Note 2)............0°C to +120°C
Storage Temperature Range.............................-65°C to +150°C
Lead Temperature (soldering, 10sec).............................+250°C
Full scale
AData, BData,
no missing codes
f
CLK
= 500MHz,
VIN= 95% full scale
(Note 5)
Bits7.1
f
AIN
= 10MHz
f
AIN
= 125MHz
Zero scale
7.6
f
AIN
= 250MHz
AData, BData
6.7 7.0
ENOBEffective Bits
CONDITIONS
Figure 4
Figure 4
(Note 7)
f
AIN
= 125MHz, f
CLK
= 500MHz,
VIN= 95% full scale (Note 6)
ps2t
AJ
ps270t
AW
Aperture Width
Aperture Jitter
205 290
Msps500f
CLK
Maximum Conversion Rate
dB44.5SNRSignal-to-Noise Ratio
GHz1.2BW
3dB
Analog Input Bandwidth
AIN+ to AIN-, Table 2,
TA= T
MIN
to T
MAX
mV
-290 -205
V
IN
Input Voltage Range
AIN+, AIN-, to GND
TA= T
MIN
to T
MAX
±0.75
±0.50TA= +25°C
TA= T
MIN
to T
MAX
Bits8Resolution
AIN+, AIN-, TA= T
MIN
to T
MAX
Ω/°C0.008
Input Resistance
Temperature Coefficient
LSB
±0.75
INLIntegral Nonlinearity (Note 4)
Ω49 51R
I
Input Resistance
mV1.65 2.35LSB
mV-23 23V
IO
Input Offset Voltage
UNITSMIN TYP MAXSYMBOLPARAMETER
Least Significant Bit Size
TA= +25°C
TA= T
MIN
to T
MAX
LSB
±0.85
DNLDifferential Nonlinearity
Note 1: The digital control inputs are diode protected. However, limited protection is provided on other pins. Permanent damage
may occur on unconnected units under high-energy electrostatic fields. Keep unused units in supplied conductive carrier or
shunt the terminals together.
Note 2: Typical thermal resistance, junction-to-case R
θJC
= 5°C/W and thermal resistance, junction to ambient (MAX101ACFR)
R
θJA
=12°C/W, if 200 lineal ft/min airflow is provided. See
Package Information.
Figure 4 ns1t
AD
Aperture Delay
ACCURACY
DYNAMIC SPECIFICATIONS
ANALOG INPUT
Page 3
VCC(nom) = ±0.25V
MAX101A
500Msps, 8-Bit ADC with Track/Hold
_______________________________________________________________________________________ 3
40
-1.02 -0.70
VARTto VA
RB
1.1 3.1
-50 50
TA= +25°C
-1.95 -1.60TA= +25°C
TA= T
MIN
to T
MAX
CONDITIONS
VEE= -5.2V
TA= +25°C
VCC= 5.0V
mA
-935
TA= +25°C
I
VEE
AData, BData
Negative Supply Current
TA= T
MIN
to T
MAX
-895 -500
V
INCM
= ±0.5V TA= T
MIN
to T
MAX
mA
910
I
VCC
Positive Supply Current
dBCMRRCommon-Mode Rejection Ratio 35
TA= T
MIN
to T
MAX
V
-1.95 -1.50
V
OL
Digital Output Low Voltage
dB
415 855
40VCC(nom) = ±0.25V
Power-Supply Rejection Ratio PSRR
V-1.50V
IL
Digital Input Low Voltage
Ω100 190R
REF
Reference String Resistance
Ω/°C0.02
Reference String Resistance
Temperature Coefficient
UNITSMIN TYP MAXSYMBOLPARAMETER
CLK, CLK, TA= T
MIN
to T
MAX
VV
IH
Digital Input High Voltage
CLK, CLK = -0.8V (no termination),
TA= T
MIN
to T
MAX
mA
-40 40
I
IH
TA= T
MIN
to T
MAX
AData, BData,
DCLK, DCLK
PH
ADJ
= 0V, TA= T
MIN
to T
MAX
V
-1.10 -0.60
V
OH
Digital Output High Voltage
Digital Input High Current
Input Bias Current I
B
µA
DIV10 = 0V, TA= T
MIN
to T
MAX
Clock Input Bias Current I
CLK
µA
-1.3 -1.00TA= +25°C
TA= T
MIN
to T
MAX
DCLK, DCLK
-1.4 -0.9
DCLK, DCLK, TA= T
MIN
to T
MAX
mV275 445V
OH
- V
OL
Digital Output Voltage
REFERENCE INPUT
LOGIC INPUTS
LOGIC OUTPUTS (Note 8)
POWER REQUIREMENTS
ELECTRICAL CHARACTERISTICS (continued)
(VEE= -5.2V, VCC= +5V, RL= 100Ω to -2V, VART, VBRT= 0.95V, VARB, VBRB= -0.95V, TA= +25°C, unless otherwise noted.
T
MIN
to T
MAX
= 0°C to +70°C.) (Note 3)
TA= T
MIN
to T
MAX
CLK, CLK, TA= T
MIN
to T
MAX
-1.1
VEE(nom) = ±0.25V
Page 4
Divide-by-1 mode See
Figures 2, 3
MAX101A
500Msps, 8-Bit ADC with Track/Hold
4 _______________________________________________________________________________________
DIV10 = 0, Figures 1 and 2
DIV10 = 0, Figures 1 and 2
ns
CLK, CLK
CLK, CLK
0.7 1.3 1.8t
PD2
DCLK to A/BData
Propagation Delay
DCLK
DATA
DCLK
DATA
20% to 80% ps
800
t
F
ns1.2 2.3 3.4t
PD1
CLK to DCLK
Propagation Delay
CONDITIONS
20% to 80%
300
Clock
Cycles
t
NPD
Divide-by-1 mode, Figures 2 and 3, Table 1Pipeline Delay (Latency) 15 15
ps
500
t
R
Fall Time
300
Rise Time
ns0.9 2.5t
PWH
ns0.9 2.5t
PWL
Clock Pulse Width Low
Clock Pulse Width High
UNITSMIN TYP MAXSYMBOLPARAMETER
TIMING CHARACTERISTICS
(VEE= -5.2V, VCC= +5V, RL= 100Ω to -2V, VART, VBRT= 0.95V, VARB, VBRB= -0.95V, TA= +25°C, unless otherwise noted.)
Note 3: All devices are 100% production tested at +25°C and are guaranteed by design for T
A
= T
MIN
to T
MAX
as specified.
Note 4: Deviation from best-fit straight line. See
Integral Nonlinearity
section.
Note 5: See the
Signal-to-Noise Ratio and Effective Bits
section in the
Detailed Description of Specifications
.
Note 6: SNR calculated from effective bits performance using the following equation: SNR(dB) = 1.76 + 6.02 x effective bits.
Note 7: Clock pulse width minimum requirements t
PWL
and t
PWH
must be observed to achieve stated performance.
Note 8: Outputs terminated through 100Ω to -2.0V.
INTEGRAL NONLINEARITY
vs. OUTPUT CODE
-0.75
0.75
0 256
-0.50
0.50
MAX101 TOC1
OUTPUT CODE
INL (LSBs)
64 192128
0
-0.25
0.25
DIFFERENTIAL NONLINEARITY
vs. OUTPUT CODE
-0.75
0.75
0 256
-0.50
0.50
MAX101 TOC2
OUTPUT CODE
DNL (LSBs)
64 192128
0
-0.25
0.25
__________________________________________Typical Operating Characteristics
(VEE= -5.2V, VCC= +5V, RL= 100Ω to -2V, VART, VBRT= 0.95V, VARB, VBRB= -0.95V, TA= +25°C, unless otherwise noted.)
Page 5
MAX101A
500Msps, 8-Bit ADC with Track/Hold
_______________________________________________________________________________________
5
____________________________Typical Operating Characteristics (continued)
(VEE= -5.2V, VCC= +5V, RL= 100Ω to -2V, VART, VBRT= 0.95V, VARB, VBRB= -0.95V, TA= +25°C, unless otherwise noted.)
FFT PLOT
(f
AIN
= 251.4462MHz)
-100
-40
-30
-20
-10
0
0 50 75 100 125
-90
-50
MAX101 TOC3
(MHz)
(dB)
25
-70
-80
-60
f
CLK
= 500MHz
SER = -44.5dB
NOISE FLOOR = -67.3dB
SPURIOUS = -58.2dB
FFT PLOT
(f
AIN
= 10.4462MHz)
-100
-40
-30
-20
-10
0
0 25 37.5 50 62.5
-90
-50
MAX101 TOC4
(MHz)
(dB)
12.5
-70
-80
-60
f
CLK
= 250MHz
SER = -47.2dB
NOISE FLOOR = -70.5dB
SPURIOUS = -61.8dB
EFFECTIVE BITS vs. ANALOG INPUT
FREQUENCY (f
AIN
)
(f
CLK
= 500MHz, VIN = 95% FS)
MAX110 TOC5
6
500
7
8
f
AIN
(MHz)
100 150 200 250 300
EFFECTIVE BITS
RECORD LENGTH = 512
EFFECTIVE BITS vs. CLOCK
FREQUENCY (f
CLK
)
(f
AIN
= 10.4462, VIN = 95% FS)
MAX110 TOC6
6
1000
7
8
f
CLK
(MHz)
200 300 400 500 600
EFFECTIVE BITS
Page 6
MAX101A
500Msps, 8-Bit ADC with Track/Hold
6 _______________________________________________________________________________________
____________________________Typical Operating Characteristics (continued)
(VEE= -5.2V, VCC= +5V, RL= 100Ω to -2V, VART, VBRT= 0.95V, VARB, VBRB= -0.95V, TA= +25°C, unless otherwise noted.)
100mV/div
-1.55V
-4.18ns 5.2ns
DATA CLOCK (DCLK) FALL TIME
(315ps), DIV10 = OPEN
MAX101 TOC8
-550mV
100mV/div
-1.55V
-4.18ns 5.2ns
DATA CLOCK (DCLK)
RISE TIME (360ps), DIV10 = OPEN
MAX101 TOC7
-550mV
100mV/div
-1.825V
-4.98ns 5.02ns
BDATA RISE TIME (504ps),
DIV10 = OPEN
MAX101 TOC9
-825mV
100mV/div
-1.825V
-4.98ns 5.02ns
BDATA FALL TIME (827ps),
DIV10 = OPEN
MAX101 TOC10
-825mV
Page 7
MAX101A
500Msps, 8-Bit ADC with Track/Hold
_______________________________________________________________________________________ 7
______________________________________________________________Pin Description
32, 69, 80 V
EE
31 DCLK
Complementary Differential Clock Outputs. Used to synchronize following circuitry: Outputs A0–A7
are valid after DCLK’s rising edge. B0–B7 output data are valid after DCLK’s falling edge (see Figure 1
for output timing information).
Negative Power Supply, -5.2V ±5% nominal
16, 48, 63 N.C.
35
10 VB
RBS
“B” side negative reference voltage sense (Note 9)
DIV10 Divide by 10 mode. Leave open for normal operation. Selects test mode when grounded.
36, 38, 39,
41, 42, 44,
45, 47
A7–A0
29 SUB
No Connect—no internal connection to these pins.
12 TP3
5, 59 TRK1
Phasing inputs (normally left open). See
Applications Information
section.
8, 21, 43,
56, 81
V
CC
Positive Power Supply, +5V ±5% nominal
11 TP4 Internal connection, leave pin open.
13 VB
RTS
“B” side positive reference voltage sense (Note 9)
9 VB
RB
“B” side negative reference voltage input (Note 9)
3, 61 CLK
Complementary Differential Clock Inputs. Can be driven from standard 10KH ECL with the following
considerations: Internally, pins 2, 62 and 3, 61 are the ends of a 50Ω transmission line. Either end
can be driven with the other end terminated with 50Ω to -2V. See
Typical Operating Circuit
.
4, 7, 15, 18,
24, 27, 30,
34, 37, 40,
46, 49, 57,
60, 64, 67,
68, 70, 71,
74, 77, 78,
79, 82, 84
GND Power-Supply Ground
2, 62 CLK
NAME FUNCTION
1 PAD Internal connection, leave open.
PIN
14 VB
RT
“B” side positive reference voltage input (Note 9)
Internal connection, leave pin open.
Circuit Substrate contact. This pin must be connected to VEE.
33 DCLK
28, 26, 25,
23, 22, 20,
19, 17
B7–B0
AData and BData Outputs. A0 and B0 are the LSBs, and A7 and B7 are the MSBs. AData and BData
outputs conform to ECL logic swings and drive 100Ω transmission lines. Terminate with 100Ω to -2V
(120Ω for Tj > +100°C). See Figures 1–3.
6, 58 TRK1
Page 8
MAX101A
500Msps, 8-Bit ADC with Track/Hold
8 _______________________________________________________________________________________
72, 73 AIN+
75, 76 AIN-
Analog Inputs, internally terminated with 50Ω to ground. Full-scale linear input range is approximately
±250mV. Drive AIN+ and AIN- differentially for best high-frequency performance.
52 TP1 Internal connection, leave pin open.
53 TP2 Internal connection, leave pin open.
54 VA
RBS
“A” side negative reference voltage sense (Note 9)
55 VA
RB
“A” side negative reference voltage input (Note 9)
65 TP5 Internal connection, leave pin open.
50 VA
RT
“A” side positive reference voltage input (Note 9)
51 VA
RTS
“A” side positive reference voltage sense (Note 9)
NAME FUNCTIONPIN
_________________________________________________Pin Description (continued)
83 PH
ADJ
Phase adjustment for T/H. Normally connected to ground. A phase adjustment of approximately ±18ps
can be made by varying this pin’s bias point to optimize interleaving between sides A and B (Note 10).
66 TP6 Internal connection, leave pin open.
Note 9: VART, VARB, VBRT, and VBRBshould be adjusted separately from a well bypassed reference circuit to ensure proper
amplitude and offset matching. The sense connections to each of these terminals allows precision setting of the reference
voltage. The reference ladder is similar for both converter halves (check electrical section for values). Any noise on these
terminals will severely reduce overall performance.
Note 10: Good results are obtained by connecting the PH
ADJ
input to ground. Improve performance by applying a voltage between
±1.25V to this input. The time that the “A” T/H bridge samples relative to the time that the “B” T/H bridge samples can be
varied through a ±18ps range.
CLK
ADATA
BDATA
CLK
DCLK
DCLK
t
PD1
t
PD2
t
PD2
t
PWH
t
PWL
Figure 1. Output Timing, Normal Mode (DIV10 = OPEN)
Page 9
MAX101A
500Msps, 8-Bit ADC with Track/Hold
_______________________________________________________________________________________ 9
ADATA
BDATA
CLK
DCLK
t
PD2
t
PD2
N-1 N+3
N-2 N N+2
N–1
N
N+1
N+2 +14 +15 +16 +17
01 7 8
N+1
NOTE: DATA ARBITRARY ON START-UP FOR SIDE A OR B, SEE
INPUT CLOCK PHASING
SECTION.
Figure 2. Output Timing, Clock to Data, Normal Mode (DIV10 = OPEN)
N+5
ADATA
BDATA
CLK
DCLK
NOTE: DATA ARBITRARY ON START-UP FOR SIDE A OR B, SEE
INPUT CLOCK PHASING
SECTION.
N
N
N+1
N+2 N+3 +15 +16 +17
Figure 3. Output Timing, Test Mode (DIV10 = GND)
Page 10
MAX101A
500Msps, 8-Bit ADC with Track/Hold
10 ______________________________________________________________________________________
______Definitions of Specifications
Signal-to Noise Ratio and Effective Bits
Signal-to-noise ratio (SNR) is the ratio between the RMS
amplitude of the fundamental input frequency to the
RMS amplitude of all other analog-to-digital (A/D) output signals. The theoretical minimum A/D noise is
caused by quantization error and is a direct result of
the ADC’s resolution: SNR = (6.02N + 1.76)dB, where N
is the number of effective bits of resolution. Therefore, a
perfect 8-bit ADC can do no better than 50dB. The FFT
plots in the
Typical Operating Characteristics
show the
output level in various spectral bands.
Effective bits is calculated from a digital record taken
from the ADC under test. The quantization error of the
ideal converter equals the total error of the device. In
addition to ideal quantization error, other sources of
error include all DC and AC nonlinearities, clock and
aperture jitter, missing output codes, and noise. Noise
on references and supplies also degrades effective bits
performance.
The ADC’s input is sine-wave filtered with an anti-aliasing filter to remove any harmonic content. The digital
record taken from this signal is compared against a
mathematically generated sine wave. DC offsets,
phase, and amplitudes of the mathematical model are
adjusted until a best-fit sine wave is found. After subtracting this sine wave from the digital record, the residual error remains. The RMS value of the error is applied
in the following equation to yield the ADC’s effective
bits.
measured RMS error
Effective bits = N - log2—————————-
ideal RMS error
where N is the resolution of the converter. In this case,
N = 8.
The worst-case error for any device will be at the converter’s maximum clock rate with the analog input near
the Nyquist rate (one-half the input clock rate).
Aperture Width and Jitter
Aperture width is the time the T/H circuit takes to disconnect the hold capacitor from the input circuit (i.e., to
turn off the sampling bridge and put the T/H in hold
mode). Aperture jitter is the sample-to-sample variation
in aperture delay (Figure 4).
Error Rates
Errors resulting from metastable states may occur when
the analog input voltage, at the time the sample is
taken, falls close to the decision point for any one of the
input comparators. The resulting output code for many
typical converters can be incorrect, including false full- or
zero-scale output. The MAX101A’s unique design
reduces the magnitude of this type of error to 1LSB, and
reduces the probability of the error occurring to less than
one in every 10
15
clock cycles. If the MAX101A were
operated at 500MHz, 24 hours a day, this would translate
to less than one metastable state error every 46 days.
Integral Nonlinearity
Integral nonlinearity is the deviation of the transfer function from a reference line measured in fractions of 1LSB
using a “best straight line” determined by a least
square curve fit.
Differential Nonlinearity
Differential nonlinearity (DNL) is the difference between
the measured LSB step and an ideal LSB step size
between adjacent code transitions. DNL is expressed
in LSBs and is calculated using the following equation:
[V
MEAS
- (V
MEAS - 1
)] - LSB
DNL(LSB) = ——————————————-
LSB
where V
MEAS - 1
is the measured value of the previous
code.
A DNL specification of less than 1LSB guarantees no
missing codes and a monotonic transfer function.
SAMPLED
DATA (T/H)
T/H
CLK
CLK
ANALOG
INPUT
t
AD
TRACK
t
AJ
t
AW
TRACKHOLD
APERTURE DELAY (t
AD)
APERTURE WIDTH (tAW)
APERTURE JITTER (tAJ)
Figure 4. T/H Aperture Timing
Page 11
_______________Detailed Description
Converter Operation
The parallel or “flash” architecture used by the MAX101A
provides the fastest multibit conversion of all common
integrated ADC designs. The basic element of a flash, as
with all other ADC architectures, is the comparator, which
has a positive input, a negative input, and an output. If
the voltage at the positive input is higher than the negative input (connected to a reference), the output will be
high. If the positive input voltage is lower than the reference, the output will be low. A typical n-bit flash consists
of 2n- 1 comparators with negative inputs evenly spaced
at 1LSB increments from the bottom to the top of the reference ladder. For n = 8, there are 255 comparators.
For any input voltage, all the comparators with negative
inputs connected to the reference ladder below the
input voltage will have outputs of 1 and all comparators
with negative inputs above the input voltage will have
outputs of 0. Decode logic is provided to convert this
information into a parallel n-bit digital word (the output)
corresponding to the number of LSBs (minus 1) that the
input voltage is above the bottom of the ladder.
The comparators contain latch circuitry and are
clocked. This allows the comparators to function as
described previously when, for example, clock is low.
When clock goes high (samples) the comparator will
latch and hold its state until the clock goes low again.
The MAX101A uses a monolithic, dual-interleaved parallel quantizer chip with two separate 8-bit converters.
These converters deliver results to the A and B output
latches on alternate negative edges of the input clock.
Track/Hold
As with all ADCs, if the input waveform is changing
rapidly during the conversion, the effective bits and
SNR will decrease. The MAX101A has an internal
track/hold (T/H) that increases attainable effective-bits
performance and allows more accurate capture of analog data at high conversion rates.
The internal T/H circuit provides two important circuit
functions for the MAX101A:
1) Its nominal voltage gain of 4 reduces the input driving signal to ±250mV differential (assuming a
±0.95V reference).
2) It provides a differential 50Ω input that allows easy
interface to the MAX101A.
Data Flow
The MAX101A’s internal T/H amplifier samples the analog input voltage for the ADC to convert. The T/H is split
into two sections that operate on alternate negative
clock edges. The input clock, CLK, is conditioned by
the T/H and fed to the A/D section. The output clock,
DCLK, used for output data timing, will be divided by 2
or 10 from the input clock (Table 1). This results in an
output data rate of 250Mbps on each output port in normal mode and 50Mbps in test mode. The differential
inputs, AIN+ and AIN-, are tracked continuously
between data samples. When a negative strobe edge is
sensed, one-half of the T/H goes into hold mode (Figure
4). When the strobe is low, the just-acquired sample is
presented to the ADC’s input comparators. Internal processing of the sampled data takes an additional 15
clock cycles before it is available at the outputs, AData
and BData. See Figures 1–3 for timing.
__________Applications Information
Analog Input Ranges
Although the normal operating range is ±250mV, the
MAX101A can be operated with up to ±500mV on each
input with respect to ground. This extended input level
includes the analog signal and any DC common-mode
voltage.
To obtain full-scale digital output with differential
input drive, a nominal +250mV must be applied
between AIN+ and AIN-. That is, AIN+ = +125mV and
AIN- = -125mV (with no DC offset). Mid-scale digital
output code occurs when there is no voltage difference
across the analog inputs. Zero-scale digital output
code, with differential -250mV drive, occurs when AIN+
= -125mV and AIN- = +125mV. Table 2 shows how the
output of the converter stays at all ones (full scale)
when over-ranged or all zeros (zero scale) when underranged.
Table 1. Output Mode Control
* Input clocks (CLK, CLK) = 500MHz for all above combinations. In
all modes, the output clock DCLK will be a 50% duty-cycle signal.
MAX101A
500Msps, 8-Bit ADC with Track/Hold
______________________________________________________________________________________ 11
DIV10
DCLK*
(MHz)
DESCRIPTION
OPEN 250
AData and BData valid on opposite DCLK edges (AData on rise,
BData on fall).
GND 50
AData and BData valid on opposite DCLK edges (AData on rise,
BData on fall). Data sampled at
input CLK rate but 4 out of every
5 samples discarded.
MODE
Normal
Divide
by 2
Test
Divide
by 10
Page 12
MAX101A
500Msps, 8-Bit ADC with Track/Hold
12 ______________________________________________________________________________________
For single-ended operation:
1) Apply a DC offset to one of the analog inputs, or
leave one input open. (Both AIN+ and AIN- are terminated internally with 50Ω to analog ground.)
2) Drive the other input with a ±250mV + offset to
obtain either full- or zero-scale digital output. If a DC
common-mode offset is used, the total voltage swing
allowed is ±500mV (analog signal plus offset with
respect to ground).
Reference
The ADC’s reference resistor is a Kelvin-sensed, resistor string that sets the ADC’s LSB size and dynamic
operating range. Normally, the top and bottom of this
string are driven with an external buffer amplifier. It will
need to supply approximately 19mA due to the 100Ω
minimum resistor string impedance. A ±0.95V reference voltage is normally applied to inputs VART, VBRT,
VARB, and VBRB. The reference inputs VA
RTS
, VA
RBS
,
VB
RTS
, and VB
RBS
allow Kelvin sensing of the applied
voltages to increase precision.
An RC network at the ADC’s reference terminals is
needed for best performance. This network consists of
a 33Ω resistor connected in series with the buffer output that drives the reference. A 0.47µF capacitor must
be connected near the resistor at the buffer’s output
(see
Typical Operating Circuit
). This resistor and
capacitor combination should be located within 0.5
inches of the MAX101A package. Any noise on these
pins will directly affect the code uncertainty and
degrade the ADC’s effective-bits performance.
R
R
R
PARASITIC
RESISTANCE
TO
COMPARATORS
POSITIVE
REFERENCE
NEGATIVE
REFERENCE
R
R
VA
RBS
VA
RB
VA
RT
VA
RTS
PARASITIC
RESISTANCE
Figure 5. Reference Ladder
Table 2. Input Voltage Range
* An offset VIO, as specified in the DC electrical parameters, will
be present at the input. Compensate for this offset by adjusting
the reference voltage. Offsets may be different between side A
and side B.
INPUT
AIN+
(mV)
AIN-
(mV)
OUTPUT
CODE
MSB to
LSB
+125 -125 1 1 1 1 1 1 1 1 full scale
Differential 0 0 1 0 0 0 0 0 0 0 mid scale
-125 +125 0 0 0 0 0 0 0 0 zero scale
+250 0 1 1 1 1 1 1 1 1 full scale
0 0 1 0 0 0 0 0 0 0 mid scale
-250 0 0 0 0 0 0 0 0 0 zero scale
Single
Ended
Page 13
MAX101A
500Msps, 8-Bit ADC with Track/Hold
______________________________________________________________________________________ 13
CLK and DCLK
All input and output clock signals are differential. The
input clocks, CLK and CLK, are the primary timing signals for the MAX101A. CLK (pins 2, 62) and CLK (pins
3, 61) are fed to the internal circuitry through an internal
50Ω transmission line. One set of CLK, CLK inputs
should be driven and the other pair terminated by 50Ω
to -2V. Either set of inputs can be used as the driven
inputs (input lines are balanced) for easy circuit connection. A minimum pulse width (t
PWL
) is required for
CLK and CLK (Figures 1–3).
For best performance and consistent results, use a low-
phase-jitter clock source for CLK and CLK. Phase jitter
larger than 2ps from the input clock source reduces the
converter’s effective bits performance and causes
inconsistent results. The clock supplied to the
MAX101A is internally divided by two, reshaped, and
buffered. This divided clock becomes the internal signal used as strobes for the converters.
DCLK and DCLK are output clock signals derived from
the input clocks and are used for external timing of the
AData and BData outputs. (AData is valid after the rising edge of DCLK, and BData is valid after the falling
edge.) They are fixed at one-half the rate of the input
clocks in normal mode (Table 1). The MAX101A is
characterized to work with 500MHz maximum input
clock frequencies. See
Typical Operating Circuit
.
Output Mode Control (DIV10)
When DIV10 is grounded, it enables the test mode,
where the input incoming clock is divided by ten. This
reduces the output data and clock rates by a factor of
5, allowing the output clock duty cycle to remain at
50%. The clock to output phasing remains the same
and four out of every five sampled input values are discarded.
When left open, this input (DIV10) is pulled low by internal circuitry and the converter functions in its normal
mode.
Layout, Grounding, and Power Supplies
A +5V ±5% supply as well as a -5.2V ±5% supply is
needed for proper operation. Bypass the VEEand V
CC
supply pins to GND with high-quality 0.1µF and 0.001µF
ceramic capacitors located as close to the package as
possible. Connect all ground pins to a ground plane to
optimize noise immunity and device accuracy. Turn on
the fan before connecting the power supplies. See
Package Information
for the required airflow.
Phase Adjust
This control pin affects the point in time that one-half of
the converter samples the input signal relative to the
other half. PH
ADJ
is normally connected to ground (0V),
but can be adjusted over a ±1.25V range that typically
provides a ±18ps adjustment between the “A” side T/H
bridge strobe and the “B” side T/H bridge strobe.
Interleaving (Input Clock Phasing)
To interleave two MAX101As it is necessary to know on
which positive edge of the input clock data will change.
At power-up, the clock edge from which AData and
BData are synchronized is undetermined. The converter can work from a specific input clock edge, as
described in the following paragraph.
TRK1 and TRK1 are differential inputs that are used in
addition to the normal input clock (CLK) to set data
phasing. A signal at one-half the input clock rate with
the proper setup and hold times (setup and hold typically 300ps) is applied to these inputs. Choose AData
by applying a logic “1” to TRK1 (“0” to TRK1) before
CLK’s negative transition. Choose BData by applying a
logic “0” to TRK1 before CLK’s negative edge (“1” to
TRK1). Voltages at the TRK1 input between ±50mV are
interpreted as logic “1” and voltages between -350mV
and -500mV are interpreted as logic “0”.
Page 14
MAX101A
500Msps, 8-Bit ADC with Track/Hold
14 ______________________________________________________________________________________
____________________________________________________________Pin Configuration
GND
CLK
CLK
N.C.
63
62
61
60
59
58
57
56
55
54
53
52
50
49
48
47
46
45
44
43
51
TOP VIEW
MAX101A
V
CC
GND
TRK1
TRK1
VA
RBS
VA
RB
VA
RT
VA
RTS
TP1
TP2
GND
A0
N.C.
GND
A2
A1
V
CC
GND
CLK
CLK
PAD
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
V
CC
GND
TRK1
TRK1
VB
RBS
VB
RB
VB
RT
VB
RTS
TP3
TP4
GND
B0
N.C.
GND
B2
B1
V
CC
84838281807978
77
VCCGND
PH
ADJ
GND
GND
GND
GND
V
EE
AIN-
AIN-
74
75
76
69
70
71
72
73
686766
65
GND
AIN+
AIN+
GND
GND
GND
V
EE
GND
TP5
TP6
64
GND
2425262728
29
B5
GND
B4
B3
SUB
B7
GND
B6
DCLK
GND
34
35
33
32
31
30
39
38
37
36
DIV10
GND
DCLK
V
EE
A5
A6
GND
A7
A4
GND
22
23
42
41
40
A3
Ceramic Flat Pack
Page 15
MAX101A
500Msps, 8-Bit ADC with Track/Hold
______________________________________________________________________________________ 15
1
/2 MAX412
8
8
+1.25V
83
-1.25V
33
31
DCLK
DCLK
ADATA
BDATA
PH
ADJ
+5V
0.1µF
0.001µF
50
8, 21, 43, 56, 81
51
54
AIN+
AIN-
GND
SUB VEE
29 32, 69, 80
4, 7, 15, 18, 24, 27, 30, 34,
37, 40, 46, 49, 57, 60, 64, 67, 68,
70, 71, 74, 77, 78, 79, 82, 84
PHASE
-5.2V
0.001µF
0.1µF
VA
RT
V
CC
VA
RTS
1.2k
500Ω
0.01µF
+5V
0.01µF
2.5V
MX580LH
1
3
2
+VS
VOUT
GND
50Ω
20k
20k
50Ω
33Ω20Ω
0.47µF
MC100E151
33Ω20Ω
1
/2 MAX412
55
VA
RBS
VA
RB
0.47µF
0.01µF
0.01µF
14
75, 76
72, 73
13
10
VB
RT
VB
RTS
9
VB
RBS
VB
RB
CLK
CLK
50Ω
2
61
-2V
-2V
62
50Ω
3
D>Q
Q
D>Q
Q
MC100E151
D>Q
Q
D>Q
Q
MAX101A
10k
2k
1.2k
500Ω
2k
CMPSH-3
CMPSH-3
1
/2 MAX412
1.2k
500Ω
50Ω
20k
20k
50Ω
33Ω20Ω
0.47µF
33Ω20Ω
1
/2 MAX412
0.47µF
0.01µF
0.01µF
10k
2k
1.2k
500Ω
2k
CMPSH-3
CMPSH-3
MC100E116
WATKINS-JOHNSON
SMRA 89-1 (2x)
___________________________________________________Typical Operating Circuit
Page 16
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are
implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
16
__________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 (408) 737-7600
© 1996 Maxim Integrated Products Printed USA is a registered trademark of Maxim Integrated Products.
MAX101A
500Msps, 8-Bit ADC with Track/Hold
________________________________________________________Package Information
0.060±.005(7x)
D3
0.075±.020(6x)
EQUAL SPACES
D2
D
D1
C
PIN #1
e
S
E2
E
E1
b
A2 A1
A
0.060±.005
E3
5°–6°
84-PIN CERAMIC FLAT
PACK WITH HEAT SINK
MILLIMETERS INCHES
A
A1
A2
b
C
D
D1
D2
D3
e
E
E1
E2
E3
S
DIM
MIN MAX MIN MAX
17.272
1.041
3.048
0.406
0.228
29.184
44.196
25.298
28.448
29.184
44.196
25.298
28.194
1.930
18.288
1.270
3.302
0.508
0.279
29.794
44.704
25.502
28.829
29.794
44.704
25.502
28.702
2.184
0.680
0.041
0.120
0.016
0.009
1.149
1.740
0.996
1.120
1.149
1.740
0.996
1.110
0.076
0.720
0.050
0.130
0.020
0.011
1.173
1.760
1.004
1.135
1.173
1.760
1.004
1.130
0.086
1.270 BSC 0.050 BSC
0 100 200 300 400 500
7
MAX100-insertB
VELOCITY (ft /min)
θ
JA
(°C/W)
9
11
13
15
17
19
21
23
PIN FIN HEATSINK
FORCED CONVECTION PARAMETERS
45° Angle*
*DIRECTION OF AIRFLOW ACROSS HEATSINK
0° Angle*
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