FEATURES
Low V
Low TCV
High h
Excellent h
Low Noise Voltage: 0.23 V p-p—0.1 Hz to 10 Hz
High Breakdown: 45 V min
Available in Die Form
PRODUCT DESCRIPTION
The MAT01 is a monolithic dual NPN transistor. An exclusive
Silicon Nitride “Triple-Passivation” process provides excellent
stability of critical parameters over both temperature and time.
Matching characteristics include offset voltage of 40 µV, tem-
perature drift of 0.15 µV/°C, and h
high h
including an exceptional h
10 nA. The high gain at low collector current makes the
MAT01 ideal for use in low power, low level input stages.
(VBE Match): 40 V typ, 100 V max
OS
: 0.5 V/ⴗC max
OS
: 500 min
FE
Linearity from 10 nA to 10 mA
FE
matching of 0.7%. Very
is provided over a six decade range of collector current,
FE
FE
FE
of 590 at a collector current of only
Dual Transistor
MAT01
PIN CONNECTION
TO-78
(H Suffix)
NOTE: Substrate is connected to case.
BURN-IN CIRCUIT
REV. A
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.
Exclude first hour of operation to allow for stabilization.
2
Parameter describes long-term average drift after first month of operation.
3
Sample tested.
4
The collector-base (I
reduced by a factor of two to ten times by connecting the substrate (package) to
a potential which is lower than either collector voltage.
5
ICC and I
6
Guaranteed by VOS test (TCV
7
Guaranteed by IOS test limits over temperature.
Specifications subject to change without notice.
are guaranteed by measurement of I
CES
) and collector-emitter (I
CBO
V
OS
≅
OS
for V
T
) leakage currents may be
CES
.
CBO
Ⰶ VBE) T = 298°K for T
OS
= 25°C.
A
WAFER TEST LIMITS
(@ VCB = 15 V, IC = 10 A, TA = +25ⴗC, unless otherwise noted.)
MAT01N
ParameterSymbolConditionsLimitsUnits
Breakdown VoltageBV
Offset VoltageV
Offset CurrentI
Bias CurrentI
Current Gainh
Current Gain Match∆h
Offset Voltage Change∆V
Offset Current Change∆V
Collector Saturation VoltageV
NOTE
Electrical tests are performed at wafer probe to the limits shown. Due to variations in assembly methods and normal yield loss, yield after packaging is not
guaranteed for standard product dice. Consult factory to negotiate specifications based on dice lot qualification through sample lot assembly and testing.
CEO
OS
OS
B
FE
FE
/∆V
OS
/∆V
OS
CE (SAT)
CB
CB
I
= 100 µA45 V min
C
0.5mV max
3.2nA max
40nA max
250min
8.0% max
0 ≤ VCB ≤ 30 V8.0µV/V max
0 ≤ VCB ≤ 30 V70pA/V max
Lead Temperature (Soldering, 60 sec) . . . . . . . . . . . .+300°C
DICE Junction Temperature . . . . . . . . . . . . –65°C to +150°C
NOTES
1
Absolute maximum ratings apply to both DICE and packaged devices.
2
Application of reverse bias voltages in excess of rating shown can result in
degradation of hFE and hFE matching characteristics. Do not attempt to measure
BV
greater than the 5 V rating shown.
EBO
3
Rating applies to applications using heat sinking to control case temperature.
Derate linearity at 16.4 mW/°C for case temperatures above 40°C.
4
Rating applies to applications not using heat sinking; device in free air only. Derate
linearity at 6.3 mW/°C for ambient temperatures above 70°C.
1
DICE CHARACTERISTICS
1. COLLECTOR (1)
2. BASE (1)
3. EMITTER (1)
5. EMITTER (2)
6. BASE (2)
7. COLLECTOR (2)
DIE SIZE 0.035 × 0.025 inch, 875 sq. mils
(0.89
×
0.64 mm, 0.58 sq. mm)
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection.
Although the MAT01 features proprietary ESD protection circuitry, permanent damage may
occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD
precautions are recommended to avoid performance degradation or loss of functionality.
–4–
REV. A
Page 5
MAT01
Figure 1. Offset Voltage
vs. Temperature
Figure 2. Current Gain
vs. Collector Current
Figure 4. Offset Voltage vs. Time
Figure 5. Current Gain
vs. Temperature
Figure 7. Base-Emitter Voltage
vs. Collector Current
Figure 8. Saturation Voltage
vs. Collector Current
Figure 3. Noise Voltage
REV. A
Figure 6. Noise Current Density
–5–
Figure 9. Gain-Bandwidth
vs. Collector Current
Page 6
MAT01
MAT01 TEST CIRCUITS
Figure 10. MAT01 Matching Measurement Circuit
Figure 11. MAT01 Noise Measurement Circuit
–6–
REV. A
Page 7
APPLICATION NOTES
Application of reverse bias voltages to the emitter-base junctions
in excess of ratings (5 V) may result in degradation of h
h
matching characteristics. Circuit designs should be checked
FE
FE
and
to ensure that reverse bias voltages above 5 V cannot be applied
during such transient conditions as at circuit turn-on and
turn-off.
Stray thermoelectric voltages generated by dissimilar metals at
the contacts to the input terminals can prevent realization of the
predicted drift performance. Both input terminals should be
maintained at the same temperature, preferably close to the temperature of the device’s package.
TYPICAL APPLICATIONS
MAT01
Figure 12. Precision Reference
Figure 13. Basic Digital Thermometer Readout in
°
Degrees Kelvin (
K)
REV. A
Figure 14. Precision Operational Amplifiers
Figure 15. Digital Thermometer with Readout in °C
–7–
Page 8
MAT01
0.185 (4.70)
0.165 (4.19)
0.370 (9.40)
0.335 (8.51)
0.335 (8.51)
0.305 (7.75)
0.040 (1.02) MAX
0.045 (1.14)
0.010 (0.25)
OUTLINE DIMENSIONS
Dimensions shown in inches and (mm).
H-06A
6-Lead Metal Can (TO-78)
REFERENCE PLANE
0.750 (19.05)
0.500 (12.70)
0.250 (6. 35) MIN
0.050 (1.27) MAX
0.019 (0.48)
0.016 (0.41)
0.021 (0.53)
0.016 (0.41)
BASE & SEATING PLANE
0.200
(5.08)
BSC
0.100
(2.54)
BSC
0.100 (2.54) BSC
4
3
2
1
0.034 (0.86)
0.027 (0.69)
0.160 (4.06)
0.110 (2.79)
5
6
45° BSC
0.045 (1.14)
0.027 (0.69)
3127–0–6/97
–8–
PRINTED IN U.S.A.
REV. A
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