Datasheet MACH445-20YC, MACH445-15YC Datasheet (Lattice Semiconductor Corporation)

FINAL

COM’L: -12/15/20

MACH445-12/15/20

High-Density EE CMOS Programmable Logic

DISTINCTIVE CHARACTERISTICS

■ 100-pin version of the MACH435 in PQFP

■ 5 V, in-circuit programmable

■ JTAG, IEEE 1149.1 JTAG testing capability

■ 128 macrocells

■ 12 ns t

■ 83 MHz f

■ 70 inputs with pull-up resistors

■ 64 outputs

■ 192 flip-flops

— 128 macrocell flip-flops
— 64 input flip-flops

PD

CNT

GENERAL DESCRIPTION

The MACH445 is a member of the high-performance
EE CMOS MACH 4 family. This device has approxi­mately twelve times the macrocell capability of the
popular PAL22V10, with significant density and func­tional features that the PAL22V10 does not provide. It is
architecturally identical to the MACH435, with the
addition of JTAG and 5-V programming features.

The MACH445 consists of eight PAL blocks intercon­nected by a programmable central switch matrix. The
central switch matrix connects the PAL blocks to each
other and to all input pins, providing a high degree of
connectivity between the fully-connected PAL blocks.
This allows designs to be placed and routed efficiently.
Routability is further enhanced by an input switch matrix
and an output switch matrix. The input switch matrix
provides input signals with alternative paths into the
central switch matrix; the output switch matrix provides
flexibility in assigning macrocells to I/O pins.

The MACH445 has macrocells that can be configured
as synchronous or asynchronous. This allows
designers to implement both synchronous and

■ Up to 20 product terms per function, with XOR

■ Flexible clocking

— Four global clock pins with selectable edges
— Asynchronous mode available for each

■ 8 “PAL33V16” blocks

■ Input and output switch matrices for high

routability

■ Fixed, predictable, deterministic delays

■ JEDEC-file compatible with MACH435

■ Zero-hold-time input register option

asynchronous logic together on the same device. The
two types of design can be mixed in any proportion,
since the selection on each macrocell affects only that
macrocell.

Up to 20 product terms per function can be assigned. It
is possible to allocate some product terms away from a
macrocell without losing the use of that macrocell for
logic generation.

The MACH445 macrocell provides either registered or
combinatorial outputs with programmable polarity. If a
registered configuration is chosen, the register can be
configured as D-type, T-type, J-K, or S-R to help reduce
the number of product terms used. The flip-flop can also
be configured as a latch. The register type decision can
be made by the designer or by the software.

All macrocells can be connected to an I/O cell through
the output switch matrix. The output switch matrix
makes it possible to make significant design changes
while minimizing the risk of pinout changes.

Lattice Semiconductor

macrocell

Publication# 17468 Rev. E Amendment/0
Issue Date: May 1995

BLOCK DIAGRAM

I2, I5

2

8

8

I/O Cells

I/O Cells

16

Matrix

8

Output Switch

8

4

Clock Generator

16

Matrix

8

Output Switch

8

4

Clock Generator

16

16

16

4

16

16

4

16

Input Switch

16

Macrocells

OE

Input Switch

16

Macrocells

OE

Input Switch

Matrix

66 X 90

AND Logic Array

and Logic Allocator

4

Matrix

66 X 90

AND Logic Array

and Logic Allocator

4

Matrix

24

33

24

33

24

33

33

Central Switch Matrix

Input Switch

Matrix

24

66 X 90

Input Switch

Matrix

24

66 X 90

Input Switch

Matrix

24

16

AND Logic Array

and Logic Allocator

OE

4

16

AND Logic Array

and Logic Allocator

OE

4

16

16

16

Macrocells

8

4

Clock Generator

16

16

16

Macrocells

8

4

Clock Generator

16

16

Matrix

8

Output Switch

4

Matrix

8

Output Switch

4

8

I/O Cells

8

I/O Cells

I/O32–I/O39I/O40–I/O47I/O48–I/O55I/O56–I/O63

Block A Block B Block C Block D

I/O0–I/O7 I/O8–I/O15 I/O16–I/O23 I/O24–I/031

8

8

8

I/O Cells

4

Clock Generator

8

I/O Cells

4

Clock Generator

Matrix

16

Output Switch

8

4

16

16

Matrix

16

Output Switch

8

4

16

Macrocells

OE

Input Switch

16

Macrocells

OE

66 X 90

AND Logic Array

and Logic Allocator

4

Matrix

66 X 90

AND Logic Array

and Logic Allocator

4

33

24

33

4

4

CLK0/I0, CLK1/I1, 

CLK2/I3, CLK3/I4

33

Input Switch

24

33

66 X 90

AND Logic Array

and Logic Allocator

OE

4

Matrix

66 X 90

AND Logic Array

and Logic Allocator

OE

4

16

16

16

Macrocells

4

Clock Generator

16

16

16

Macrocells

4

Clock Generator

Matrix

8

Output Switch

8

4

Matrix

8

Output Switch

8

4

8

I/O Cells

8

I/O Cells

17468E-1

Block H Block G Block F Block E

2 MACH445-12/15/20

CONNECTION DIAGRAM MACH445 (MACH435)
Top View

PQFP

BLOCK A

I/O7

I/O6

I/O5

I/O4

I/O3

I/O2

I/O1

I/O0

VCC

GND

GND

99

98

97969594939291908988878685

100

GND
GND

TDI

I/O8
I/O9

I/O10

BLOCK B

I/O11
I/O12
I/O13
I/O14
I/O15

I0/CLK0

VCC
VCC

GND
GND

I1/CLK1

I/O16
I/O17
I/O18
I/O19
I/O20
I/O21

BLOCK C

I/O22
I/O23

TMS

TCK
GND
GND

I5

1

(9)

(8)

(7)

(6)

(5)

(4)

(10)

2

(3)

3

(83)

4

(12)

5

(13)

6

(14)

7

(15)

8

(16)

9

(17)

10

(18)

11

(19)

12

(20)

13
14

15
16

17

(23)

18

(24)

19

(25)

20

(26)

21

(27)

22

(28)

23

(29)

24

(30)

25

(31)

26
27
28
29
30

(33)

(34)

(35)

(36)

(37)

(38)

(39)

(40)

31323334353637383940414243444546474849

VCC

(82)

(45)

I/O63

BLOCK H

I/O62

I/O61

I/O60

I/O59

84

(81)

(80)

(79)

(78)

(46)

(47)

(48)

(49)

I/O58

I/O57

828183

(77)

(76)

(73)
(72)
(71)
(70)
(69)

(68)
(67)
(66)
(65)

(62)
(61)
(60)
(59)

(58)
(57)
(56)
(55)
(54)

(41)

(50)

(51)

I/O56

80

(75)

79
78
77
76

75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60

59
58
57
56
55
54
53
52
51

(52)

50

GND
GND
TD0
TRST*
I/O55
I/O54
I/O53
I/O52
I/O51
I/O50
I/O49
I/O48
I4/CLK3
GND
GND

VCC
VCC

I3/CLK2
I/O47
I/O46
I/O45

I/O44
I/O43
I/O42
I/O41
I/O40
I2
ENABLE*
GND
GND

BLOCK G

BLOCK F

PIN DESIGNATIONS

CLK/I = Clock or Input
GND = Ground
I = Input
I/O = Input/Output
VCC = Supply Voltage

I/O24

I/O25

I/O26

BLOCK D

I/O28

I/O27

I/O29

I/O30

VCC

I/O31

GND

GND

VCC

I/O32

I/O33

I/O34

I/O35

I/O36

BLOCK E

I/O37

I/O38

I/O39

17468E-2

3MACH445-12/15/20

ORDERING INFORMATION
Commercial Products

Programmable logic products for commercial applications are available with several ordering options. The order number
(Valid Combination) is formed by a combination of:

MACH 445 -12 Y C

FAMILY TYPE

MACH = Macro Array CMOS High-Speed

DEVICE NUMBER

445 = 2nd Generation, 128 Macrocells, 100 Pins

SPEED

-12 = 12 ns t

-15 = 15 ns t

-20 = 20 ns t

PD
PD
PD

Valid Combinations

MACH445-12
MACH445-15
MACH445-20

YC

OPTIONAL PROCESSING

Blank = Shipped in Trays

OPERATING CONDITIONS

C = Commercial (0

PACKAGE TYPE

Y = 100-Pin Plastic Quad Flat Pack

(PQR100)

Valid Combinations

The Valid Combinations table lists configurations
planned to be supported in volume for this device. Con­sult your local sales office to confirm availability of
specific valid combinations and to check on newly re­leased combinations.

°C to +70°C)

4 MACH445-12/15/20

FUNCTIONAL DESCRIPTION

The MACH445 consists of eight PAL blocks connected
by a central switch matrix. There are 64 I/O pins and 6
dedicated input pins feeding the central switch matrix.
These signals are distributed to the eight PAL blocks for
efficient design implementation. There are 4 global
clock pins that can also be used as dedicated inputs.

All inputs and I/O pins have built-in pull-up resistors.
While it is always good design practice to tie unused
pins high, the pull-up resistors provide design security
and stability in the event that unused pins are left
disconnected.

The PAL Blocks

Each PAL block in the MACH445 (Figure 1) contains a
clock generator, a 90-product-term logic array, a logic
allocator, 16 macrocells, an output switch matrix, 8 I/O
cells, and an input switch matrix. The central switch
matrix feeds each PAL block with 33 inputs. This makes
the PAL block look effectively like an independent
“PAL33V16” with 8 to 16 buried macrocells.

In addition to the logic product terms, individual output
enable product terms and two PAL block initialization
product terms are provided. Each I/O pin can be
individually enabled. All flip-flops that are in the
synchronous mode within a PAL block are initialized
together by either of the PAL block nitialization
product terms.

The Central Switch Matrix and Input
Switch Matrix

The MACH445 central switch matrix is fed by the input
switch matrices in each PAL block. Each PAL block
provides 16 internal feedback signals, 8 registered input
signals, and 8 I/O pin signals to the input switch matrix.
Of these 32 signals, 24 decoded signals are provided to
the central switch matrix by the input switch matrix. The
central switch matrix distributes these signals back to
the PAL blocks in a very efficient manner that provides
for high performance. The design software automati­cally configures the input and central switch matrices
when fitting a design into the device.

The Clock Generator

Each PAL block has a clock generator that can generate
four clock signals for use throughout the PAL block.
These four signals are available to all macrocells and
I/O cells in the PAL block, whether in synchronous or
asynchronous mode. The clock generator chooses the
four signals from the eight possible signals given by the
true and complement versions of the four global clock
pin signals.

The Product-Term Array

The MACH445 product-term array consists of 80
product terms for logic use, eight product terms for
output enable use, and two product terms for global PAL
block initialization. Each macrocell has a nominal
allocation of 5 product terms for logic, although the logic
allocator allows for logic redistribution. Each I/O pin has
its own individual output enable term. The initialization
product terms provide asynchronous reset or preset to
synchronous-mode macrocells in the PAL block.

The Logic Allocator

The logic allocator in the MACH445 takes the 80 logic
product terms and allocates them to the 16 macrocells
as needed. Each macrocell can be driven by up to 20
product terms in synchronous mode, or 18 product
terms in asynchronous mode. When product terms are
routed away from a macrocell, all 5 product terms may
be redirected, which precludes the use of the macrocell
for logic generation. It is possible to redirect only 4
product terms, leaving one for simple function genera­tion. The design software automatically configures the
logic allocator when fitting the design into the device.

The logic allocator also provides an exclusive-OR gate.
This gate allows generation of combinatorial exclusive­OR logic, such as comparison or addition. It allows
registered exclusive-OR functions, such as CRC gen­eration, to be implemented more efficiently. Emulating
all flip-flop types with a D-type flip-flop is also made
possible. Register type emulation is automatically
handled by the design software.

Table 1 illustrates which product term clusters are
available to each macrocell within a PAL block. Refer to
Figure 1 for cluster and macrocell numbers.

5MACH445-12/15/20

Table 9. Logic Allocation

Macrocell Available Clusters

M0 C0, C1, C2
M1 C0, C1, C2, C3
M2 C1, C2, C3, C4
M3 C2, C3, C4, C5
M4 C3, C4, C5, C6
M5 C4, C5, C6, C7
M6 C5, C6, C7, C8
M7 C6, C7, C8, C9
M8 C7, C8, C9, C10
M9 C8, C9, C10, C11
M10 C9, C10, C11, C12
M11 C10, C11, C12, C13
M12 C11, C12, C13, C14
M13 C12, C13, C14, C15
M14 C13, C14, C15
M15 C14, C15

The Macrocell and Output Switch Matrix

The MACH445 has 16 macrocells, half of which can
drive I/O pins; this selection is made by the output switch
matrix. Each macrocell can drive one of four I/O cells.
The allowed combinations are shown in Table 2. Please
refer to Figure 1 for macrocell and I/O pin
numbers.

Table 2. Output Switch Matrix Combinations

Macrocell Routable to I/O Pins

M0, M1 I/O5, I/O6, I/O7, I/O0
M2, M3 I/O6, I/O7, I/O0, I/O1
M4, M5 I/O7, I/O0, I/O1, I/O2
M6, M7 I/O0, I/O1, I/O2, I/O3
M8, M9 I/O1, I/O2, I/O3, I/O4
M10, M11 I/O2, I/O3, I/O4, I/O5
M12, M13 I/O3, I/O4, I/O5, I/O6
M14, M15 I/O4, I/O5, I/O6, I/O7

I/O Pin Available Macrocells

I/O0 M0, M1, M2, M3, M4, M5, M6, M7

I/O1 M2, M3, M4, M5, M6, M7, M8, M9
I/O2 M4, M5, M6, M7, M8, M9, M10, M11
I/O3 M6, M7, M8, M9, M10, M11, M12, M13
I/O4 M8, M9, M10, M11, M12, M13, M14, M15
I/O5 M10, M11, M12, M13, M14, M15, M0, M1
I/O6 M12, M13, M14, M15, M0, M1, M2, M3
I/O7 M14, M15, M0, M1, M2, M3, M4, M5

The macrocells can be configured as registered,
latched, or combinatorial. In combination with the logic
allocator, the registered configuration can be any of the
standard flip-flop types. The macrocell provides internal
feedback whether configured with or without the flip­flop, and whether or not the macrocell drives an I/O cell.

The flip-flop clock depends on the mode selected for
the macrocell. In synchronous mode, any of the PAL
block clocks generated by the Clock Generator can be
used. In asynchronous mode, the additional choice of
either edge of an individual product-term clock is
available.

Initialization can be handled as part of a bank of
macrocells via the PAL block initialization terms if in
synchronous mode, or individually if in asynchronous
mode. In synchronous mode, one of the PAL block
product terms is available each for preset and reset. The
swap function determines which product term drives
which function. This allows initialization polarity com­patibility with the MACH 1 and 2 series. In asynchronous
mode, one product term can be used either to drive reset
or preset.

The I/O Cell

The I/O cell in the MACH445 consists of a three-state
buffer and an input flip-flop. The I/O cell is driven by one
of the macrocells, as selected by the output switch
matrix. Each I/O cell can take its input from one of eight
macrocells. The three-state buffer is controlled by an
individual product term. The input flip-flop can be
configured as a register or latch. Both the direct I/O
signal and the registered/latched signal are available to
the input switch matrix, and can be used simultaneously
if desired.

JTAG Testing

JTAG is the commonly used acronym for the IEEE
Standard 1149.1–1990. The JTAG standard defines
input and output pins, logic control functions, and
instructions. Lattice/Vantis has incorporated this stan­dard into the MACH445device.

The JTAG standard was developed as a means of
providing both board-level and device-level testing.

6 MACH445-12/15/20

Five-Volt Programming

Another benefit from the JTAG circuitry that we have
derived is the ability to use the JTAG port for five-volt
programming. This allows the device to be soldered to
the board before programming. Once the device is
attached, the delicate Plastic Quad Flat Pack, or PQFP,
leads are protected from programming and testing
operations that could potentially damage them. Pro­gramming and verification of the device is done serially
which is ideal for on-board programming since it only
requires the use of the Test Access Port. Use of the
programming Enable Pin (ENABLE*) is optional.

Zero-Hold-Time Input Register

The MACH445 device has a zero-hold time (ZHT) fuse.
This fuse controls the time delay associated with loading
data into all I/O cell registers and latches in the
MACH445 device.

When programmed, the ZHT fuse increases the data
path setup delays to input storage elements, matching
equivalent delays in the clock path. When the fuse is
erased, the setup time to the input storage element is
minimized and the device timing is compatible with the
MACH435 device.

This feature facilitates doing worst-case designs for
which data is loaded from sources which have low (or
zero) minimum output propagation delays from clock
edges.

7MACH445-12/15/20

16

CLK0/I0

CLK1/I1

Clock

Generator

4

CLK2/I3

CLK3/I4

Central Switch Matrix

C0

M0

C1

M1

C2

M2

C3

M3

C4

M4

C5

M5

C6

M6

C7

M7

C8

M8

Logic Allocator

C9

M9

Macrocell

Macrocell

Macrocell

Macrocell

Macrocell

Macrocell

Macrocell

Macrocell

Macrocell

Macrocell

M0

M1

M2

M3

M4

M5

M6

M7

M8

Output Switch Matrix

M9

I/O

O0

Cell

I/O

O1

Cell

I/O

O2

Cell

I/O

O3

Cell

I/O

O4

Cell

I/O0

I/O1

I/O2

I/O3

I/O4

17

24

Input

Switch

Matrix

C10

M10

C11

M11

C12

M12

C13

M13

C14

M14

C15

M15

16

16

Figure 1. MACH445 PAL Block

Macrocell

Macrocell

Macrocell

Macrocell

Macrocell

Macrocell

M10

M11

M12

M13

M14

M15

I/O

O5

Cell

I/O

O6

Cell

I/O

O7

Cell

I/O5

I/O6

I/O7

17468E-3

8 MACH445-12/15/20

ABSOLUTE MAXIMUM RATINGS

Storage Temperature –65°C to +150°C. . . . . . . . . . .

Ambient Temperature

with Power Applied –55°C to +125°C. . . . . . . . . . . . .

Supply Voltage with

Respect to Ground –0.5 V to +7.0 V. . . . . . . . . . . . .

DC Input Voltage –0.5 V to V
DC Output or

CC

+0.5 V. . . . . . . . . . . .

OPERATING RANGES

Commercial (C) Devices

Temperature (T

in Free Air 0°C to +70°C. . . . . . . . . . . . . . . . . . . . . . .

Supply Voltage (V

Respect to Ground +4.75 V to +5.25 V. . . . . . . . . . . .

Operating ranges define those limits between which the
functionality of the device is guaranteed.

) Operating

A

) with

CC

I/O Pin Voltage –0.5 V to VCC +0.5 V. . . . . . . . . . . . .

Static Discharge Voltage 2001 V. . . . . . . . . . . . . . . . .

Latchup Current
(T

= 0°C to +70°C) 200 mA. . . . . . . . . . . . . . . . . . . .

A

Stresses above those listed under Absolute Maximum
Ratings may cause permanent device failure. Functionality at
or above these limits is not implied. Exposure to Absolute
Maximum Ratings for extended periods may affect device
reliability. Programming conditions may differ.

DC CHARACTERISTICS over COMMERCIAL operating ranges unless otherwise specified

Parameter

Symbol Parameter Description Test Conditions Min Typ Max Unit

V

OH Output HIGH Voltage IOH = –3.2 mA, VCC = Min 2.4 V

IN = VIH or VIL

V

V

V

V

I

I

I
I

OL

I

IH

I

IL

OZH

OZL

SC

CC

IH

IL

Output LOW Voltage IOL = 24 mA, VCC = Min 0.5 V

V

= VIH or V

IN

(Note 1)

IL

Input HIGH Voltage Guaranteed Input Logical HIGH 2.0 V

Voltage for all Inputs (Note 2)

Input LOW Voltage Guaranteed Input Logical LOW 0.8 V

Voltage for all Inputs (Note 2)
Input HIGH Leakage Current VIN = 5.25 V, VCC = Max (Note 3) 10 µA
Input LOW Leakage Current VIN = 0 V, V
Off-State Output Leakage V

= 5.25 V, VCC = Max

OUT

Current HIGH VIN = V
Off-State Output Leakage V

Current LOW V
Output Short-Circuit Current V
Supply Current V

= 0 V, VCC = Max

OUT

= V

IN

= 0.5 V, VCC = Max (Note 4) –30 –160 mA

OUT

= 0 V, Outputs Open (I

IN

V

= 5.0 V, f =25 MHz, TA = 25°C (Note 5)

CC

= Max (Note 3) –100 µA

CC

or VIL (Note 3)

IH

or VIL (Note 3)

IH

= 0 mA) 255 mA

OUT

10

–100

µA

µA

CAPACITANCE (Note 6)

Parameter
Symbol Parameter Description Test Conditions Typ Unit

C

IN

C

OUT

Input Capacitance V
Output Capacitance V

Notes:

1. Total I

for one PAL block should not exceed 128 mA.

OL

2. These are absolute values with respect to device ground and all overshoots due to system or tester noise are included.

3. I/O pin leakage is the worst case of I

and I

IL

(or IIH and I

OZL

4. Not more than one output should be shorted at a time and duration of the short-circuit should not exceed one second.
= 0.5 V has been chosen to avoid test problems caused by tester ground degradation.

V

OUT

5. Measured with a 16-bit up/down counter pattern. This pattern is programmed in each PAL block and capable of being loaded,

enabled, and reset.

6. These parameters are not 100% tested, but are evaluated at initial characterization and at any time the design is modified

where capacitance may be affected.

= 2.0 V VCC = 5.0 V, TA = 25°C, 6 pF

IN

= 2.0 V f = 1 MHz 8 pF

OUT

).

OZH

9MACH445-12 (Com’l)

SWITCHING CHARACTERISTICS over COMMERCIAL operating ranges (Note 1)

Parameter

-12

Symbol Parameter Description Min Max Unit

t

PD

Input, I/O, or Feedback to 3 12 ns
Combinatorial Output

t

t

t

COA

t

WLA

t

WHA

f

MAXA

t

t

t

COS

t

WLS

t

WHS

f

MAXS

t

SA

HA

SS

HS

SLA

Setup Time from Input, I/O, or D-type 5 ns
Feedback to Product Term Clock

T-type 6 ns
Register Data Hold Time Using Product Term Clock 5 ns
Product Term Clock to Output 4 14 ns

Product Term, Clock Width

Maximum

External Feedback
Frequency
Using Product

D-type 58.8 MHz
Term Clock

Internal Feedback (f

CNTA

)

(Note 2)

No Feedback (Note 3)

Setup Time from Input, I/O, or Feedback
to Global Clock

LOW 8 ns
HIGH 8 ns
D-type 52.6 MHz
T-type 50.0 MHz

T-type 55.6 MHz

62.5 MHz
D-type 7 ns
T-type 8 ns

Register Data Hold Time Using Global Clock 0 ns
Global Clock to Output 2 8 ns

Global Clock Width

LOW 6 ns
HIGH 6 ns

D-type 66.7 MHz
Maximum
Frequency
Using Global

D-type 83.3 MHz
Clock (Note 2)

83.3 MHz

External Feedback

Internal Feedback (f

No Feedback (Note 3)

CNTS

T-type 62.5 MHz

)

T-type 76.9 MHz

Setup Time from Input, I/O, or Feedback to 5 ns
Product Term Clock

t

HLA

t

GOA

t

GWA

Latch Data Hold Time Using Product Term Clock 5 ns
Product Term Gate to Output 16 ns
Product Term Gate Width LOW (for LOW transparent) 6 ns

or HIGH (for HIGH transparent)
t
t

HLS

t

GOS

t

GWS

SLS

Setup Time from Input, I/O, or Feedback to Global Gate 8 ns

Latch Data Hold Time Using Global Gate 0 ns

Gate to Output 10 ns

Global Gate Width LOW (for LOW transparent) 6 ns

or HIGH (for HIGH transparent)
t

ICO

Input Register Clock to Combinatorial Output 18 ns

10 MACH445-12 (Com’l)

SWITCHING CHARACTERISTICS over COMMERCIAL operating ranges (Note 1)

(continued)

Parameter

Symbol Parameter Description Min Max Unit

t

ICS

Input Register Clock to Output Register Setup D-type 9 ns

T-type 10 ns

t

WICL

t

WICH

f

MAXIR

t

IGO

t

IGOL

Input Register Clock Width

Maximum Input Register Frequency 1/(t

WICL

+ t

) 83.3 MHz

WICH

Input Latch Gate to Combinatorial Output 16 ns
Input Latch Gate to Output Through Transparent 18 ns

LOW 6 ns
HIGH 6 ns

Output Latch

t

IGSA

Input Latch Gate to Output Latch Setup Using 4 ns
Product Term Output Latch Gate

t

IGSS

Input Latch Gate to Output Latch Setup Using Global 9 ns
Output Latch Gate

t

WIGL

t

t

ARW

t

ARR

t

t

APW

t

APR

t

t

AR

AP

EA

ER

Input Latch Gate Width LOW 6 ns
Asynchronous Reset to Registered or Latched Output 16 ns
Asynchronous Reset Width (Note 2) 12 ns
Asynchronous Reset Recovery Time (Note 2) 10 ns
Asynchronous Preset to Registered or Latched Output 16 ns
Asynchronous Preset Width (Note 2) 12 ns
Asynchronous Preset Recovery Time (Note 2) 8 ns
Input, I/O, or Feedback to Output Enable 2 12 ns
Input, I/O, or Feedback to Output Disable 2 12 ns

Input Register with Standard-Hold-Time Option

t

PDL

Input, I/O, or Feedback to Output Through 14 ns

Transparent Input Latch
t
t

t
t

t

SLLA

SIR

HIR

SIL

HIL

Input Register Setup Time 2 ns

Input Register Hold Time 3 ns

Input Latch Setup Time 2 ns

Input Latch Hold Time 3 ns

Setup Time from Input, I/O, or Feedback Through 4 ns

Transparent Input Latch to Product Term Output Gate

t

SLLS

Setup Time from Input, I/O, or Feedback Through 9 ns

Transparent Input Latch to Output Gate

t

PDLL

Input, I/O, or Feedback to Output Through Transparent 16 ns

Input and Output Latches

-12

11MACH445-12 (Com’l)

SWITCHING CHARACTERISTICS over COMMERCIAL operating ranges (Note 1)

(continued)

Parameter

-12

Symbol Parameter Description Min Max Unit

Input Register with Zero-Hold-Time Option

❙

t

PDL

Input, I/O, or Feedback to Output Through 20 ns

Transparent Input Latch

t

SIR

t

HIR

t

SIL

t

HIL

t

SLLA

❙

❙

❙

❙

❙

Input Register Setup Time 6 ns

Input Register Hold Time 0 ns

Input Latch Setup Time 6 ns

Input Latch Hold Time 0 ns

Setup Time from Input, I/O, or Feedback Through 16 ns

Transparent Input Latch to Product Term Output Gate

t

SLLS

❙

Setup Time from Input, I/O, or Feedback Through 18 ns

Transparent Input Latch to Output Gate

❙

t

PDLL

Input, I/O, or Feedback to Output Through Transparent 22 ns

Input and Output Latches

Notes:

1. See Switching Test Circuit at the end of this Data Book for test conditions.

2. These parameters are not 100% tested, but are evaluated at initial characterization and at any time the design is modified
where frequency may be affected.

3. This parameter does not apply to flip-flops in the emulated mode since the feedback path is required for emulation.

12 MACH445-12 (Com’l)

ABSOLUTE MAXIMUM RATINGS

Storage Temperature –65°C to +150°C. . . . . . . . . . .

Ambient Temperature

with Power Applied –55°C to +125°C. . . . . . . . . . . . .

Supply Voltage with

Respect to Ground –0.5 V to +7.0 V. . . . . . . . . . . . .

DC Input Voltage –0.5 V to V
DC Output or

I/O Pin Voltage –0.5 V to V

Static Discharge Voltage 2001 V. . . . . . . . . . . . . . . . .

Latchup Current

= 0°C to +70°C) 200 mA. . . . . . . . . . . . . . . . . . . .

(T

A

CC

CC

+0.5 V. . . . . . . . . . .

+0.5 V. . . . . . . . . . . .

OPERATING RANGES

Commercial (C) Devices

Temperature (T

in Free Air 0°C to +70°C. . . . . . . . . . . . . . . . . . . . . . .

Supply Voltage (V

Respect to Ground +4.75 V to +5.25 V. . . . . . . . . . . .

Operating ranges define those limits between which the
functionality of the device is guaranteed.

Stresses above those listed under Absolute Maximum
Ratings may cause permanent device failure. Functionality at
or above these limits is not implied. Exposure to Absolute
Maximum Ratings for extended periods may affect device

) Operating

A

) with

CC

reliability. Programming conditions may differ.

DC CHARACTERISTICS over COMMERCIAL operating ranges unless otherwise specified

Parameter

Symbol Parameter Description Test Conditions Min Typ Max Unit

V

V

V

V

I

I

I
I

OH

OL

I

IH

I

IL

OZH

OZL

SC

CC

IH

IL

Output HIGH Voltage IOH = –3.2 mA, VCC = Min 2.4 V

V

= VIH or V

IN

IL

Output LOW Voltage IOL = 24 mA, VCC = Min 0.5 V

VIN = VIH or V

(Note 1)

IL

Input HIGH Voltage Guaranteed Input Logical HIGH 2.0 V

Voltage for all Inputs (Note 2)

Input LOW Voltage Guaranteed Input Logical LOW 0.8 V

Voltage for all Inputs (Note 2)
Input HIGH Leakage Current VIN = 5.25 V, VCC = Max (Note 3) 10 µA
Input LOW Leakage Current VIN = 0 V, V
Off-State Output Leakage V

Current HIGH V
Off-State Output Leakage V

Current LOW V
Output Short-Circuit Current V
Supply Current V

= 5.25 V, V

OUT

= V

IN

= 0 V, VCC = Max

OUT

= V

IN

= 0.5 V, VCC = Max (Note 4) –30 –160 mA

OUT

= 0 V, Outputs Open 255 mA

IN

(I

= 0 mA), V

OUT

f =25 MHz T

= Max (Note 3) –100 µA

CC

= Max 10 µA

CC

or VIL (Note 3)

IH

or VIL (Note 3)

IH

= 5.0 V,

CC

= 25°C (Note 5)

A

–100

µA

CAPACITANCE (Note 6)

Parameter
Symbol Parameter Description Test Conditions Typ Unit

C

IN

C

OUT

Input Capacitance V
Output Capacitance V

Notes:

1. Total I

for one PAL block should not exceed 128 mA.

OL

2. These are absolute values with respect to device ground and all overshoots due to system or tester noise are included.

3. I/O pin leakage is the worst case of I

and I

IL

(or IIH and I

OZL

4. Not more than one output should be shorted at a time and duration of the short-circuit should not exceed one second.
= 0.5 V has been chosen to avoid test problems caused by tester ground degradation.

V

OUT

5. Measured with a 16-bit up/down counter pattern. This pattern is programmed in each PAL block and capable of being loaded,

enabled, and reset. An actual I

value can be calculated by using the “Typical Dynamic I

CC

end of this data sheet.

6. These parameters are not 100% tested, but are evaluated at initial characterization and at any time the design is modified

where capacitance may be affected.

= 2.0 V VCC = 5.0 V, TA = 25°C, 6 pF

IN

= 2.0 V f = 1 MHz 8 pF

OUT

).

OZH

Characteristics” Chart towards the

CC

13MACH445-15/20 (Com’l)

SWITCHING CHARACTERISTICS over COMMERCIAL operating ranges (Note 1)

Parameter

-15 -20

Symbol Parameter Description Min Max Min Max Unit

t

PD

Input, I/O, or Feedback to Combinatorial Output 3 15 3 20 ns

(Note 2)

D-type 8 10 ns
T-type 9 11 ns

LOW 9 12 ns
HIGH 9 12 ns

t
t
t

t

WHA

t

SA

HA

COA

WLA

Setup Time from Input, I/O, or
Feedback to Product Term Clock

Register Data Hold Time Using Product Term Clock 8 10 ns
Product Term Clock to Output (Note 2) 4 18 4 22 ns

Product Term, Clock Width

D-type 38.5 31.2 MHz

f

MAXA

External Feedback 1/(t

Maximum
Frequency

D-type 47.6 37 MHz

Using Product

Internal Feedback (f

Term Clock
(Note 3)

No Feedback 1/(t

CNTA

SA

)

WLA

+ t

+ t

)

COA

T-type 37 30.3 MHz

T-type 45.4 35.7 MHz

)

WHA

55.6 41.7 MHz

(Note 4)

t
t
t

t

WHS

t

SS

HS

COS

WLS

Setup Time from Input, I/O, or Feedback
to Global Clock

Register Data Hold Time Using Global Clock 0 0 ns
Global Clock to Output (Note 2) 2 10 2 12 ns

Global Clock Width

D-type 10 13 ns
T-type 11 14 ns

LOW 6 8 ns
HIGH 6 8 ns

D-type 50 40 MHz

f

MAXS

External Feedback 1/(t

Maximum

D-type 66.6 50 MHz

Frequency
Using Global

Internal Feedback (f

Clock (Note 3)

83.3 62.5 MHz

No Feedback 1/(t
(Note 4)

CNTS

SS

)

WLS

+ t

+ t

)

COS

T-type 47.6 38.5 MHz

T-type 62.5 47.6 MHz

)

WHS

t

SLA

Setup Time from Input, I/O, or Feedback to 8 10 ns
Product Term Clock

t

HLA

t

GOA

t

GWA

Latch Data Hold Time Using Product Term Clock 8 10 ns
Product Term Gate to Output (Note 2) 19 22 ns
Product Term Gate Width LOW (for LOW transparent) 9 12 ns

or HIGH (for HIGH transparent)
t
t

HLS

t

GOS

t

GWS

SLS

Setup Time from Input, I/O, or Feedback to Global Gate 10 13 ns

Latch Data Hold Time Using Global Gate 0 0 ns

Gate to Output (Note 2) 11 12 ns

Global Gate Width LOW (for LOW transparent) 6 8 ns

or HIGH (for HIGH transparent)
t

ICO

Input Register Clock to Combinatorial Output 20 25 ns

14 MACH445-15/20 (Com’l)

SWITCHING CHARACTERISTICS over COMMERCIAL operating ranges (Note 1)

(continued)

Parameter

-15 -20

Symbol Parameter Description Min Max Min Max Unit

t

ICS

Input Register Clock to Output Register Setup D-type 15 20 ns

T-type 16 21 ns

t

WICL

t

WICH

f

MAXIR

t

IGO

t

IGOL

Input Register Clock Width

Maximum Input Register Frequency 1/(t

WICL

Input Latch Gate to Combinatorial Output 20 25 ns
Input Latch Gate to Output Through Transparent 22 27 ns

LOW 6 8 ns
HIGH 6 8 ns

+ t

) 83.3 62.5 MHz

WICH

Output Latch

t

IGSA

Input Latch Gate to Output Latch Setup Using 14 19 ns
Product Term Output Latch Gate

t

IGSS

Input Latch Gate to Output Latch Setup Using Global 16 21 ns
Output Latch Gate

t

WIGL

t

t

ARW

t

ARR

t

t

APW

t

APR

t

t

AR

AP

EA

ER

Input Latch Gate Width LOW 6 8 ns
Asynchronous Reset to Registered or Latched Output 20 25 ns
Asynchronous Reset Width (Note 3) 15 20 ns
Asynchronous Reset Recovery Time (Note 3) 15 20 ns
Asynchronous Preset to Registered or Latched Output 20 25 ns
Asynchronous Preset Width (Note 3) 15 20 ns
Asynchronous Preset Recovery Time (Note 3) 15 20 ns
Input, I/O, or Feedback to Output Enable (Note 2) 2 15 2 20 ns
Input, I/O, or Feedback to Output Disable (Note 2) 2 15 2 20 ns

Input Register with Standard-Hold-Time Option

t

PDL

Input, I/O, or Feedback to Output Through 17 22 ns

Transparent Input Latch
t
t

t
t

t

SLLA

SIR

HIR

SIL

HIL

Input Register Setup Time 2 2 ns

Input Register Hold Time 4 5 ns

Input Latch Setup Time 2 2 ns

Input Latch Hold Time 4 5 ns

Setup Time from Input, I/O, or Feedback Through 10 12 ns

Transparent Input Latch to Product Term Output Gate

t

SLLS

Setup Time from Input, I/O, or Feedback Through 12 16 ns

Transparent Input Latch to Output Gate

t

PDLL

Input, I/O, or Feedback to Output Through Transparent 19 24 ns

Input and Output Latches

15MACH445-15/20 (Com’l)

SWITCHING CHARACTERISTICS over COMMERCIAL operating ranges (Note 1)

(continued)

Parameter

-15 -20

Symbol Parameter Description Min Max Min Max Unit

Input Register with Zero-Hold-Time Option

❙

t

PDL

Input, I/O, or Feedback to Output Through 23 30 ns

Transparent Input Latch

❙

t
t

t

t

t

SLLA

SIR

HIR

SIL

HIL

Input Register Setup Time 6 8 ns

❙

Input Register Hold Time 0 0 ns

❙

Input Latch Setup Time 6 8 ns

❙

Input Latch Hold Time 0 0 ns

❙

Setup Time from Input, I/O, or Feedback Through 16 20 ns

Transparent Input Latch to Product Term Output Gate

❙

t

SLLS

Setup Time from Input, I/O, or Feedback Through 18 24 ns

Transparent Input Latch to Output Gate

❙

t

PDLL

Input, I/O, or Feedback to Output Through Transparent 25 32 ns

Input and Output Latches

Notes:

1. See Switching Test Circuit at the end of this Data Book for test conditions.

2. Parameters measured with 32 outputs switching.

3. These parameters are not 100% tested, but are evaluated at initial characterization and at any time the design is modified
where frequency may be affected.

4. This parameter does not apply to flip-flops in the emulated mode since the feedback path is required for emulation.

16 MACH445-15/20 (Com’l)

TYPICAL CURRENT VS. VOLTAGE (I-V) CHARACTERISTICS

V

= 5.0 V, TA = 25°C

CC

(mA)

I

OL

80
60

40
20

–0.8 –0.6 –0.4 .2–0.2–1.0

–20

–40
–60

–80

.4 .6 1.0.8

V

(V)

OL

–3 –2 –1

Output, LOW

I

(mA)

OH

25

123

–25
–50

–75

–100
–125

–150

Output, HIGH

I

(mA)

I

20

45

17468E-4

V

(V)

OH

17468E-5

–2 –1

–20
–40

–60
–80

–100

Input

123

45

V

(V)

I

17468E-6

17MACH445-12/15/20

TYPICAL ICC CHARACTERISTICS

= 5 V, TA = 25°C

V

CC

325

ICC (mA)

300

275

250

225

200

175

150

125

100

75

MACH445

50

25

0

0 10203040506070

Frequency (MHz)

The selected “typical” pattern is a 16-bit up/down counter. This pattern is programmed in each PAL block and is
capable of being loaded, enabled, and reset.

Maximum frequency shown uses internal feedback and a D-type register.

17468E-7

18 MACH445-12/15/20

TYPICAL THERMAL CHARACTERISTICS

Measured at 25°C ambient. These parameters are not tested.

Parameter
Symbol Parameter Description PQFP Unit

θ

jc

θ

ja

θ

jma

Thermal impedance, junction to case 5 °C/W
Thermal impedance, junction to ambient 38 °C/W
Thermal impedance, junction to 200 lfpm air 32 °C/W

ambient with air flow

400 lfpm air 28 °C/W
600 lfpm air 26 °C/W
800 lfpm air 24 °C/W

Typ

Plastic θjc Considerations

The data listed for plastic θjc are for reference only and are not recommended for use in calculating junction temperatures. The

θ

heat-flow paths in plastic-encapsulated devices are complex, making the
package surface. Tests indicate this measurement reference point is directly below the die-attach area on the bottom center of the
package. Furthermore,

θ

jc tests on packages are performed in a constant-temperature bath, keeping the package surface at a

constant temperature. Therefore, the measurements can only be used in a similar environment.

jc measurement relative to a specific location on the

19MACH445-12/15/20

SWITCHING WAVEFORMS

Input, I/O,

or Feed-

back

Clock

Registered

Output

Input, I/O, or

Feedback

Combinatorial

Output

t

S

V

Registered Output

V

T

t

PD

V

T

17468E-8

Combinatorial Output

T

Input, I/O, or

Feedback

Gate

Latched

Out

t

PDL

V

T

t

H

T

t

CO

V

17468E-9

V

T

t

t

HL

SL

V

T

t

GO

V

T

17468E-10

Latched Output (MACH 2, 3, and 4)

t

WH

Clock

Clock Width

Registered

Input

t

SIR

Input

Register

Clock

Combinatorial

Output

Registered Input (MACH 2 and 4)

Notes:

= 1.5 V.

1. V

T

2. Input pulse amplitude 0 V to 3.0 V.

3. Input rise and fall times 2 ns–4 ns typical.

t

WL

V

T

t

ICO

17468E-11

Gate

t

GWS

V

T

17468E-12

Gate Width (MACH 2, 3, and 4)

V

t

T

HIR

Registered

Input

V

T

Input

Register

V

T

Clock

t

V

T

Output

Register

17468E-13 17468E-14

Clock

ICS

V

T

Input Register to Output Register Setup

(MACH 2 and 4)

20 MACH445-12/15/20

SWITCHING WAVEFORMS

Latched

Combinatorial

In

Latched

Gate

Output

V

t

HIL

T

V

T

t

IGO

V

T

17468E-15

In

t

SIL

Latched Input (MACH 2 and 4)

t

PDLL

V

T

Latched

Out

t

Input

IGOL

Latch Gate

t

IGS

Output

Latch Gate

Notes:

1. VT = 1.5 V.

2. Input pulse amplitude 0 V to 3.0 V.

3. Input rise and fall times 2 ns–4 ns typical.

Latched Input and Output

(MACH 2, 3, and 4)

V

T

t

SLL

V

T

17468E-16

21MACH445-12/15/20

SWITCHING WAVEFORMS

t

WICH

Clock

Input Register Clock Width

(MACH 2 and 4)

t

WICL

V

T

17468E-17

Input

Latch

Gate

t

WIGL

Input Latch Gate Width

(MACH 2 and 4)

V

T

17468E-18

Input, I/O, or

Feedback

Registered

Output

Clock

t

ARW

t

AR

V

T

Asynchronous Reset

Input, I/O, or

Feedback

Outputs

V

T

t

ARR

V

T

17468E-19

t

ER

Input, I/O,

or Feedback

Registered

Output

Clock

V

- 0.5V

OH

+ 0.5V

V

OL

t

APW

V

T

t

AP

V

T

t

APR

V

T

17468E-20

Asynchronous Preset

V

T

t

EA

V

T

Output Disable/Enable

Notes:

= 1.5 V.

1. V

T

2. Input pulse amplitude 0 V to 3.0 V.

3. Input rise and fall times 2 ns–4 ns typical.

22 MACH445-12/15/20

17468E-21

KEY TO SWITCHING WAVEFORMS

WAVEFORM INPUTS OUTPUTS

SWITCHING TEST CIRCUIT

Must be
Steady

May
Change
from H to L

May
Change
from L to H

Don’t Care,
Any Change
Permitted

Does Not
Apply

5 V

Will be
Steady

Will be
Changing
from H to L

Will be
Changing
from L to H

Changing,
State
Unknown

Center
Line is High­Impedance
“Off” State

KS000010-PAL

S

1

R

1

Specification S

, t

t

PD

CO

t

EA

Output

R

2

Commercial

1

C

L

R

1

Closed 1.5 V
Z → H: Open 35 pF 1.5 V

C

L

Test Point

R

2

17468E-22

Measured

Output Value

Z → L: Closed 300 Ω 390 Ω

t

ER

H →Z: Open 5 pF H →Z: VOH – 0.5 V
L →Z: Closed L →Z: V

*Switching several outputs simultaneously should be avoided for accurate measurement.

+ 0.5 V

OL

23MACH445-12/15/20

f

PARAMETERS

MAX

The parameter f

is the maximum clock rate at which

MAX

the device is guaranteed to operate. Because the flexi­bility inherent in programmable logic devices offers a
choice of clocked flip-flop designs, f

is specified for

MAX

three types of synchronous designs.
The first type of design is a state machine with feedback

signals sent off-chip. This external feedback could go
back to the device inputs, or to a second device in a
multi-chip state machine. The slowest path defining the
period is the sum of the clock-to-output time and the in­put setup time for the external signals (t
ciprocal, f

, is the maximum frequency with external

MAX

+ tCO). The re-

S

feedback or in conjunction with an equivalent speed de­vice. This f

is designated “f

MAX

external.”

MAX

The second type of design is a single-chip state ma­chine with internal feedback only. In this case, flip-flop
inputs are defined by the device inputs and flip-flop out­puts. Under these conditions, the period is limited by the
internal delay from the flip-flop outputs through the inter­nal feedback and logic to the flip-flop inputs. This f
designated “f

internal”. A simple internal counter is a

MAX

MAX

is

good example of this type of design; therefore, this pa­rameter is sometimes called “f

CNT.

”

The third type of design is a simple data path applica­tion. In this case, input data is presented to the flip-flop
and clocked through; no feedback is employed. Under
these conditions, the period is limited by the sum of the
data setup time and the data hold time (t
a lower limit for the period of each f
mum clock period (t

+ tWL). Usually, this minimum

WH

clock period determines the period for the third f
ignated “f

no feedback.”

MAX

For devices with input registers, one additional f
rameter is specified: f

. Because this involves no

MAXIR

feedback, it is calculated the same way as f

+ tH). However,

S

type is the mini-

MAX

MAX

no feed-

MAX

, des-

MAX

pa-

back. The minimum period will be limited either by the

+ t

sum of the setup and hold times (t
the clock widths (t

WICL

+ t

WICH

SIR

). The clock widths are nor­mally the limiting parameters, so that f
as 1/(t

WICL

+ t

). Note that if both input and output reg-

WICH

) or the sum of

HIR

is specified

MAXIR

isters are use in the same path, the overall frequency will
be limited by t

All frequencies except f
other measured AC parameters. f

ICS

.

internal are calculated from

MAX

internal is meas-

MAX

ured directly.

CLK

(SECOND

CHIP)

LOGIC REGISTER

tt

SCO

f

External; 1/(tS + tCO)

MAX

t

S

CLK

LOGIC REGISTER

CLK

LOGIC REGISTER

f

Internal (f

MAX

CNT

)

CLK

REGISTER

LOGIC

t

S

f

No Feedback; 1/(tS + tH) or 1/(tWH + tWL)

MAX

24 MACH445-12/15/20

t

SIR

f

MAXIR

t

HIR

; 1/(t

SIR

+ t

HIR

) or 1/(t

WICL

+ t

WICH

17468E-23

)

ENDURANCE CHARACTERISTICS

The MACH families are manufactured using our
advanced Electrically Erasable process. This technol­ogy uses an EE cell to replace the fuse link used in

bipolar parts. As a result, the device can be erased and
reprogrammed, a feature which allows 100% testing at
the factory.

Endurance Characteristics

Parameter

Symbol Parameter Description Min Units Test Conditions

10 Years Max Storage

Temperature

t

DR

N Max Reprogramming Cycles 100 Cycles Normal Programming

Min Pattern Data Retention Time

20 Years Max Operating

Temperature

Conditions

25MACH445-12/15/20

INPUT/OUTPUT EQUIVALENT SCHEMATICS

1 kΩ

ESD

Protection

Input

V

CC

100 kΩ

V

CC

V

CC

Preload

Circuitry

100 kΩ

Feedback

Input

I/O

V

CC

1 kΩ

17468E-24

26 MACH445-12/15/20

POWER-UP RESET

The MACH devices have been designed with the capa­bility to reset during system power-up. Following power­up, all flip-flops will be reset to LOW. The output state

wide range of ways V
conditions are required to insure a valid power-up reset.
These conditions are:

will depend on the logic polarity. This feature provides
extra flexibility to the designer and is especially valuable
in simplifying state machine initialization. A timing dia­gram and parameter table are shown below. Due to the
synchronous operation of the power-up reset and the

Parameter
Symbol Parameter Descriptions Max Unit

1. The V

2. Following reset, the clock input must not be driven

from LOW to HIGH until all applicable input and
feedback setup times are met.

rise must be monotonic.

CC

can rise to its steady state, two

CC

t

PR

t

S

t

WL

Registered

Power

Output

Clock

Power-Up Reset Time 10 µs
Input or Feedback Setup Time
Clock Width LOW

4 V

t

PR

t

S

t

WL

See
Switching
Characteristics

V

CC

17468E-25

Power-Up Reset Waveform

27MACH445-12/15/20

USING PRELOAD AND OBSERVABILITY

In order to be testable, a circuit must be both controllable
and observable. To achieve this, the MACH devices
incorporate register preload and observability.

In preload mode, each flip-flop in the MACH device can
be loaded from the I/O pins, in order to perform
functional testing of complex state machines. Register
preload makes it possible to run a series of tests from a
known starting state, or to load illegal states and test for
proper recovery. This ability to control the MACH
device’s internal state can shorten test sequences,
since it is easier to reach the state of interest.

The observability function makes it possible to see the
internal state of the buried registers during test by
overriding each register’s output enable and activating
the output buffer. The values stored in output and buried
registers can then be observed on the I/O pins. Without
this feature, a thorough functional test would be
impossible for any designs with buried registers.

While the implementation of the testability features is
fairly straightforward, care must be taken in certain
instances to insure valid testing.

Preloaded

HIGH

DQQ

1

AR

Preloaded

HIGH

Q

D

2

Q

AR

One case involves asynchronous reset and preset. If the
MACH registers drive asynchronous reset or preset
lines and are preloaded in such a way that reset or
preset are asserted, the reset or preset may remove the
preloaded data. This is illustrated in Figure 2. Care
should be taken when planning functional tests, so that
states that will cause unexpected resets and presets are
not preloaded.

Another case to be aware of arises in testing combinato­rial logic. When an output is configured as combinato­rial, the observability feature forces the output into
registered mode. When this happens, all product terms
are forced to zero, which eliminates all combinatorial
data. For a straight combinatorial output, the correct
value will be restored after the preload or observe
function, and there will be no problem. If the function
implements a combinatorial latch, however, it relies on
feedback to hold the correct value, as shown in Figure 3.
As this value may change during the preload or observe
operation, you cannot count on the data being correct
after the operation. To insure valid testing in these
cases, outputs that are combinatorial latches should not
be tested immediately following a preload or observe
sequence, but should first be restored to a known state.

Preload

Mode

Q

1

AR

Q

2

Set

On

Off

Figure 2. Preload/Reset Conflict

17468E-26

All MACH 2 devices support both preload and
observability.

Contact individual programming vendors in order to

Reset

verify programmer support.

28 MACH445-12/15/20

Figure 3. Combinatorial Latch

17468E-27