Datasheet M95640, M95640-W, M95640-R, M95640-DR Datasheet (ST)

M95640 M95640-W M95640-R

UFDFPN8 (MB or MC)

2 x 3 mm

TSSOP8 (DW)

169 mil width

SO8 (MN)

150 mil width

Features

■ Compatible with the Serial Peripheral Interface

(SPI) bus

■ Memory array

– 64 Kb (8 Kbytes) of EEPROM
– Page size: 32 bytes

■ Additional Write lockable Page (Identification

page)

■ Write (self timed cycle)

– Byte Write within 5 ms
– Page Write within 5 ms

■ Write Protect: quarter, half or whole memory

array

■ High speed clock frequency (20 MHz)

■ Single supply voltage: 1.8 V to 5.5 V

■ More than 1 million Write cycles

■ More than 40-year data retention

■ Enhanced ESD Protection

■ Packages

–ECOPACK2

Halogen-free)

®

(RoHS-compliant and

M95640-DR

64 Kbit serial SPI bus EEPROMs

with high-speed clock

April 2011 Doc ID 16877 Rev 15 1/48

www.st.com

1

Contents M95640, M95640-W, M95640-R, M95640-DR

Contents

1 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

2 Signal description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

2.1 Serial Data output (Q) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

2.2 Serial Data input (D) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

2.3 Serial Clock (C) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

2.4 Chip Select (S

2.5 Hold (HOLD

2.6 Write Protect (W

2.7 V

2.8 V

ground . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

SS

supply voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

CC

) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

3 Connecting to the SPI bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

3.1 SPI modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

4 Operating features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

4.1 Supply voltage (VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

4.1.1 Operating supply voltage V

4.1.2 Device reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

4.1.3 Power-up conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

4.1.4 Power-down . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

4.2 Active Power and Standby Power modes . . . . . . . . . . . . . . . . . . . . . . . . . 13

4.2.1 Hold condition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

CC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

4.3 Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

4.4 Data protection and protocol control . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

5 Memory organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

6 Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

6.1 Write Enable (WREN) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

6.2 Write Disable (WRDI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

6.3 Read Status Register (RDSR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

6.3.1 WIP bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

2/48 Doc ID 16877 Rev 15

M95640, M95640-W, M95640-R, M95640-DR Contents

6.3.2 WEL bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

6.3.3 BP1, BP0 bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

6.3.4 SRWD bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

6.4 Write Status Register (WRSR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

6.5 Read from Memory Array (READ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

6.6 Write to Memory Array (WRITE) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

6.7 Read Identification Page . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

6.8 Write Identification Page . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

6.9 Read Lock Status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

6.10 Lock ID . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

7 Power-up and delivery state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

7.1 Power-up state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

7.2 Initial delivery state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

8 Maximum rating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

9 DC and AC parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

10 Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40

11 Part numbering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43

12 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44

Doc ID 16877 Rev 15 3/48

List of tables M95640, M95640-W, M95640-R, M95640-DR

List of tables

Table 1. Signal names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

Table 2. Write-protected block size . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

Table 3. M95640-x Instruction set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

Table 4. M95640-DR instruction set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

Table 5. Status Register format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

Table 6. Protection modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

Table 7. Address range bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

Table 8. Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

Table 9. Operating conditions (M95640 device grade 3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

Table 10. Operating conditions (M95640-W) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

Table 11. Operating conditions (M95640-R device grade 6) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

Table 12. AC measurement conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

Table 13. Capacitance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

Table 14. DC characteristics (M95640, device grade 3). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

Table 15. DC characteristics (M95640-W, device grade 6) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

Table 16. DC characteristics (M95640-W, device grade 3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

Table 17. DC characteristics (M95640-R, M95640-DR, device grade 6) . . . . . . . . . . . . . . . . . . . . . . 33

Table 18. AC characteristics (M95640, device grade 3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

Table 19. AC characteristics (M95640-W products, device grade 6) . . . . . . . . . . . . . . . . . . . . . . . . . 35

Table 20. AC characteristics (M95640-W products, device grade 3) . . . . . . . . . . . . . . . . . . . . . . . . . 36

Table 21. AC characteristics (M95640-R, M95640-DR devices, grade 6) . . . . . . . . . . . . . . . . . . . . . 37

Table 22. SO8N – 8-lead plastic small outline, 150 mils body width, package mechanical data . . . . 40

Table 23. TSSOP8 – 8-lead thin shrink small outline, package mechanical data. . . . . . . . . . . . . . . . 41

Table 24. UFDFPN8 (MLP8) 8-lead ultra thin fine pitch dual flat package no lead

2 x 3 mm, data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42

Table 25. Ordering information scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43

Table 26. Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44

4/48 Doc ID 16877 Rev 15

M95640, M95640-W, M95640-R, M95640-DR List of figures

List of figures

Figure 1. Logic diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

Figure 2. 8-pin package connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

Figure 3. Bus master and memory devices on the SPI bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

Figure 4. SPI modes supported . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

Figure 5. Hold condition activation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

Figure 6. Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

Figure 7. Write Enable (WREN) sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

Figure 8. Write Disable (WRDI) sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

Figure 9. Read Status Register (RDSR) sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

Figure 10. Write Status Register (WRSR) sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

Figure 11. Read from Memory Array (READ) sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

Figure 12. Byte Write (WRITE) sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

Figure 13. Page Write (WRITE) sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

Figure 14. Read Identification Page sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

Figure 15. Write Identification Page sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

Figure 16. Read Lock Status sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

Figure 17. Lock ID sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

Figure 18. AC measurement I/O waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

Figure 19. Serial input timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38

Figure 20. Hold timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38

Figure 21. Serial output timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39

Figure 22. SO8N – 8-lead plastic small outline, 150 mils body width, package outline . . . . . . . . . . . . 40

Figure 23. TSSOP8 – 8-lead thin shrink small outline, package outline . . . . . . . . . . . . . . . . . . . . . . . 41

Figure 24. UFDFPN8 (MLP8) - 8-lead ultra thin fine pitch dual flat no lead, package

outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42

Doc ID 16877 Rev 15 5/48

Description M95640, M95640-W, M95640-R, M95640-DR

AI01789C

S

V

CC

M95xxx

HOLD

V

SS

W

Q

C

D

DV

SS

C

HOLDQ

SV

CC

W

AI01790D

M95xxx

1
2
3
4

8

7

6

5

1 Description

The M95640, M95640-W and M95640-R are electrically erasable programmable memory

(EEPROM) devices. They are accessed by a high-speed SPI-compatible bus. The devices

are 64 Kbit devices organized as 8192 × 8 bits.

The M95640-D also offers an additional page, named the Identification Page (32 bytes)

which can be written and (later) permanently locked in Read-only mode. This Identification

Page offers flexibility in the application board production line, as it can be used to store

unique identification parameters and/or parameters specific to the production line.

The device is accessed by a simple serial interface that is SPI-compatible. The bus signals

are C, D and Q, as shown in Ta bl e 1 and Figure 1.

The device is selected when Chip Select (S

can be interrupted using Hold (HOLD

).

Figure 1. Logic diagram

Figure 2. 8-pin package connections

) is taken low. Communications with the device

1. See Package mechanical data section for package dimensions and how to identify pin-1.

6/48 Doc ID 16877 Rev 15

M95640, M95640-W, M95640-R, M95640-DR Description

Table 1. Signal names

Signal name Description

C Serial Clock

D Serial data input

Q Serial data output

S Chip Select

W

HOLD

Write Protect

Hold

V

CC

V

SS

Supply voltage

Ground

Doc ID 16877 Rev 15 7/48

Signal description M95640, M95640-W, M95640-R, M95640-DR

2 Signal description

During all operations, VCC must be held stable and within the specified valid range:

V

(min) to VCC(max).

CC

All of the input and output signals must be held high or low (according to voltages of V

V

, VIL or VOL, as specified in Ta bl e 1 4 ). These signals are described next.

OH

2.1 Serial Data output (Q)

This output signal is used to transfer data serially out of the device. Data is shifted out on the

falling edge of Serial Clock (C).

2.2 Serial Data input (D)

This input signal is used to transfer data serially into the device. It receives instructions,

addresses, and the data to be written. Values are latched on the rising edge of Serial Clock

(C).

,

IH

2.3 Serial Clock (C)

This input signal provides the timing of the serial interface. Instructions, addresses, or data

present at Serial Data Input (D) are latched on the rising edge of Serial Clock (C). Data on

Serial Data Output (Q) changes after the falling edge of Serial Clock (C).

2.4 Chip Select (S)

When this input signal is high, the device is deselected and Serial Data output (Q) is at high

impedance. Unless an internal Write cycle is in progress, the device will be in the Standby

Power mode. Driving Chip Select (S

mode.

After Power-up, a falling edge on Chip Select (S

instruction.

2.5 Hold (HOLD)

The Hold (HOLD) signal is used to pause any serial communications with the device without

deselecting the device.

During the Hold condition, the Serial Data output (Q) is high impedance, and Serial Data

input (D) and Serial Clock (C) are Don’t Care.

To start the Hold condition, the device must be selected, with Chip Select (S

) low selects the device, placing it in the Active Power

) is required prior to the start of any

) driven low.

8/48 Doc ID 16877 Rev 15

M95640, M95640-W, M95640-R, M95640-DR Signal description

2.6 Write Protect (W)

The main purpose of this input signal is to freeze the size of the area of memory that is

protected against Write instructions (as specified by the values in the BP1 and BP0 bits of

the Status Register).

This pin must be driven either high or low, and must be stable during all write operations.

2.7 VSS ground

VSS is the reference for the VCC supply voltage.

2.8 VCC supply voltage

Refer to Section 4.1: Supply voltage (VCC) on page 12.

Doc ID 16877 Rev 15 9/48

Connecting to the SPI bus M95640, M95640-W, M95640-R, M95640-DR

AI12836b

SPI bus master

SPI memory

device

SDO

SDI

SCK

CQD

S

SPI memory

device

CQD

S

SPI memory

device

CQD

S

CS3 CS2 CS1

SPI interface with

(CPOL, CPHA) =

(0, 0) or (1, 1)

W

HOLD

W

HOLD

W

HOLD

RRR

V

CC

V

CC

V

CC

V

CC

V

SS

V

SS

V

SS

V

SS

R

3 Connecting to the SPI bus

These devices are fully compatible with the SPI protocol.

All instructions, addresses and input data bytes are shifted in to the device, most significant

bit first. The Serial Data input (D) is sampled on the first rising edge of the Serial Clock (C)

after Chip Select (S

All output data bytes are shifted out of the device, most significant bit first. The Serial Data

output (Q) is latched on the first falling edge of the Serial Clock (C) after the instruction (such

as the Read from Memory Array and Read Status Register instructions) have been clocked

into the device.

Figure 3 shows three devices, connected to an MCU, on a SPI bus. Only one device is

selected at a time, so only one device drives the Serial Data output (Q) line at a time, all the

others being high impedance.

Figure 3. Bus master and memory devices on the SPI bus

) goes low.

1. The Write Protect (W) and Hold (HOLD) signals should be driven, high or low as appropriate.

A pull-up resistor connected on each /S input (represented in Figure 3) ensures that each

device is not selected if the bus master leaves the /S line in the high impedance state.

In applications where the bus master might enter a state where all inputs/outputs SPI bus

10/48 Doc ID 16877 Rev 15

would be in high impedance at the same time (for example, if the bus master is reset during

the transmission of an instruction), the clock line (C) must be connected to an external pull-

down resistor so that, if all inputs/outputs become high impedance, the C line is pulled low

(while the S

same time, and so, that the t

line is pulled high): this will ensure that S and C do not become high at the

requirement is met. The typical value of R is 100 kΩ.

SHCH

M95640, M95640-W, M95640-R, M95640-DR Connecting to the SPI bus

AI01438B

C

MSB

CPHA

D

0

1

CPOL

0

1

Q

C

MSB

3.1 SPI modes

These devices can be driven by a microcontroller with its SPI peripheral running in either of

the two following modes:

● CPOL=0, CPHA=0

● CPOL=1, CPHA=1

For these two modes, input data is latched in on the rising edge of Serial Clock (C), and

output data is available from the falling edge of Serial Clock (C).

The difference between the two modes, as shown in Figure 4, is the clock polarity when the

bus master is in Stand-by mode and not transferring data:

● C remains at 0 for (CPOL=0, CPHA=0)

● C remains at 1 for (CPOL=1, CPHA=1)

Figure 4. SPI modes supported

Doc ID 16877 Rev 15 11/48

Operating features M95640, M95640-W, M95640-R, M95640-DR

4 Operating features

4.1 Supply voltage (VCC)

4.1.1 Operating supply voltage V

Prior to selecting the memory and issuing instructions to it, a valid and stable VCC voltage

within the specified [V

(min), VCC(max)] range must be applied (see Ta bl e 9 andTa bl e 1 0).

CC

This voltage must remain stable and valid until the end of the transmission of the instruction

and, for a Write instruction, until the completion of the internal write cycle (t

secure a stable DC supply voltage, it is recommended to decouple the V

suitable capacitor (usually of the order of 10 nF to 100 nF) close to the V

pins.

4.1.2 Device reset

In order to prevent inadvertent write operations during power-up, a power-on-reset (POR)

circuit is included. At power-up, the device does not respond to any instruction until V

reaches the internal threshold voltage (this threshold is defined in DC characteristics tables

14, 15 and16 as V

When V

● in the Standby Power mode

● deselected (note that, to be executed, an instruction must be preceded by a falling

passes over the POR threshold, the device is reset and in the following state:

CC

edge on Chip Select (S

● Status register values:

– the Write Enable Latch (WEL) bit is reset to 0
– the Write In Progress (WIP) bit is reset to 0
– the SRWD, BP1 and BP0 bits remain unchanged (non-volatile bits).

RES

).

))

CC

). In order to

W

line with a

CC

CC/VSS

package

CC

When V

passes over the POR threshold, the device is reset and enters the Standby

CC

Power mode. The device must not be accessed until V

voltage within the specified [V

(min), VCC(max)] range defined in Ta b le 9 andTa bl e 1 0.

CC

4.1.3 Power-up conditions

When the power supply is turned on, VCC continuously rises from VSS to VCC. During this

time, the Chip Select (S

therefore recommended to connect the S

Figure 3).

In addition, the Chip Select (S

sensitive as well as level-sensitive: after power-up, the device does not become selected

until a falling edge has first been detected on Chip Select (S

(S

) must have been high, prior to going low to start the first operation.

The V

voltage has to rise continuously from 0 V up to the minimum VCC operating voltage

CC

defined in Ta bl e 9 and Ta bl e 1 0 and the rise time must not vary faster than 1 V/µs.

12/48 Doc ID 16877 Rev 15

) line is not allowed to float but should follow the VCC voltage. It is

line to VCC via a suitable pull-up resistor (see

) input offers a built-in safety feature, as the S input is edge-

reaches a valid and stable VCC

CC

). This ensures that Chip Select

M95640, M95640-W, M95640-R, M95640-DR Operating features

AI02029D

HOLD

C

Hold

Condition

Hold

Condition

4.1.4 Power-down

During power-down (continuous decrease in the VCC supply voltage below the minimum

V

operating voltage defined in Ta bl e 9 and Ta bl e 1 0 ), the device must be:

CC

● deselected (Chip Select S should be allowed to follow the voltage applied on V

● in Standby Power mode (there should not be any internal write cycle in progress).

CC

)

4.2 Active Power and Standby Power modes

When Chip Select (S) is low, the device is selected, and in the Active Power mode. The

device consumes I

When Chip Select (S

progress, the device then goes in to the Standby Power mode, and the device consumption

drops to I

CC1

.

4.2.1 Hold condition

The Hold (HOLD) signal is used to pause any serial communications with the device without

resetting the clocking sequence.

During the Hold condition, the Serial Data output (Q) is high impedance, and Serial Data

input (D) and Serial Clock (C) are Don’t Care.

, as specified in Ta bl e 1 4 to Ta bl e 1 8 .

CC

) is high, the device is deselected. If a Write cycle is not currently in

To enter the Hold condition, the device must be selected, with Chip Select (S

) low.

Normally, the device is kept selected, for the whole duration of the Hold condition.

Deselecting the device while it is in the Hold condition, has the effect of resetting the state of

the device, and this mechanism can be used if it is required to reset any processes that had

been in progress.

The Hold condition starts when the Hold (HOLD

) signal is driven low at the same time as

Serial Clock (C) already being low (as shown in Figure 5).

The Hold condition ends when the Hold (HOLD

) signal is driven high at the same time as

Serial Clock (C) already being low.

Figure 5 also shows what happens if the rising and falling edges are not timed to coincide

with Serial Clock (C) being low.

Figure 5. Hold condition activation

Doc ID 16877 Rev 15 13/48

Operating features M95640, M95640-W, M95640-R, M95640-DR

4.3 Status Register

Figure 6 shows the position of the Status Register in the control logic of the device. The

Status Register contains a number of status and control bits that can be read or set (as

appropriate) by specific instructions. See Section 6.3: Read Status Register (RDSR) for a

detailed description of the Status Register bits.

4.4 Data protection and protocol control

Non-volatile memory devices can be used in environments that are particularly noisy, and

within applications that could experience problems if memory bytes are corrupted.

Consequently, the device features the following data protection mechanisms:

● Write and Write Status Register instructions are checked that they consist of a number

of clock pulses that is a multiple of eight, before they are accepted for execution.

● All instructions that modify data must be preceded by a Write Enable (WREN)

instruction to set the Write Enable Latch (WEL) bit. This bit is returned to its reset state
by the following events:

–Power-up
– Write Disable (WRDI) instruction completion
– Write Status Register (WRSR) instruction completion
– Write (WRITE) instruction completion

● The Block Protect (BP1, BP0) bits in the Status Register allow part of the memory to be

configured as read-only.

● The Write Protect (W) signal is used to protect the Block Protect (BP1, BP0) bits of the

Status Register.

For any instruction to be accepted, and executed, Chip Select (S

) must be driven high after
the rising edge of Serial Clock (C) for the last bit of the instruction, and before the next rising
edge of Serial Clock (C).

Two points need to be noted in the previous sentence:

● The ‘last bit of the instruction’ can be the eighth bit of the instruction code, or the eighth

bit of a data byte, depending on the instruction (except for Read Status Register
(RDSR) and Read (READ) instructions).

● The ‘next rising edge of Serial Clock (C)’ might (or might not) be the next bus

transaction for some other device on the SPI bus.

Table 2. Write-protected block size

Status Register bits

Protected block

BP1 BP0 64 Kbit devices

0 0 none none

0 1 Upper quarter 1800h - 1FFFh

1 0 Upper half 1000h - 1FFFh

1 1 Whole memory 0000h - 1FFFh

Array addresses protected

14/48 Doc ID 16877 Rev 15

M95640, M95640-W, M95640-R, M95640-DR Memory organization

AI01272C

HOLD

S

W

Control Logic

High Voltage

Generator

I/O Shift Register

Address Register

and Counter

Data

Register

1 Page

X Decoder

Y Decoder

C

D

Q

Size of the
Read only
EEPROM
area

Status

Register

5 Memory organization

The memory is organized as shown in Figure 6.

Figure 6. Block diagram

Doc ID 16877 Rev 15 15/48

Instructions M95640, M95640-W, M95640-R, M95640-DR

6 Instructions

Each instruction starts with a single-byte code, as summarized in Ta b le 3 .

If an invalid instruction is sent (one not contained in Ta bl e 3 ), the device automatically
deselects itself.

Table 3. M95640-x Instruction set

Instruction Description Instruction format

WREN Write Enable 0000 0110

WRDI Write Disable 0000 0100

RDSR Read Status Register 0000 0101

WRSR Write Status Register 0000 0001

READ Read from Memory Array 0000 0011

WRITE Write to Memory Array 0000 0010

Table 4. M95640-DR instruction set

Instruction Description

WREN Write Enable 0000 0110

WRDI Write Disable 0000 0100

RDSR Read Status Register 0000 0101

WRSR Write Status Register 0000 0001

READ Read from Memory Array 0000 0011

WRITE Write to Memory Array 0000 0010

Read Identification
Page

Write Identification
Page

Read Lock Status Reads the lock status of the Identification Page. 1000 0011

Lock ID Locks the Identification page in read-only mode. 1000 0010

Reads the page dedicated to identification. 1000 0011

Writes the page dedicated to identification. 1000 0010

6.1 Write Enable (WREN)

The Write Enable Latch (WEL) bit must be set prior to each WRITE and WRSR instruction.
The only way to do this is to send a Write Enable instruction to the device.

Instruction

format

As shown in Figure 7, to send this instruction to the device, Chip Select (S
and the bits of the instruction byte are shifted in, on Serial Data Input (D). The device then
enters a wait state. It waits for a the device to be deselected, by Chip Select (S
high.

16/48 Doc ID 16877 Rev 15

) is driven low,

) being driven

M95640, M95640-W, M95640-R, M95640-DR Instructions

C

D

AI02281E

S

Q

21 34567

High Impedance

0

Instruction

Figure 7. Write Enable (WREN) sequence

Doc ID 16877 Rev 15 17/48

Instructions M95640, M95640-W, M95640-R, M95640-DR

C

D

AI03750D

S

Q

21 34567

High Impedance

0

Instruction

6.2 Write Disable (WRDI)

One way of resetting the Write Enable Latch (WEL) bit is to send a Write Disable instruction
to the device.

As shown in Figure 8, to send this instruction to the device, Chip Select (S

) is driven low,

and the bits of the instruction byte are shifted in, on Serial Data Input (D).

The device then enters a wait state. It waits for a the device to be deselected, by Chip Select
(S

) being driven high.

The Write Enable Latch (WEL) bit, in fact, becomes reset by any of the following events:

● Power-up

● WRDI instruction execution

● WRSR instruction completion

● WRITE instruction completion.

Figure 8. Write Disable (WRDI) sequence

18/48 Doc ID 16877 Rev 15

M95640, M95640-W, M95640-R, M95640-DR Instructions

6.3 Read Status Register (RDSR)

The Read Status Register (RDSR) instruction allows the Status Register to be read. The
Status Register may be read at any time, even while a Write or Write Status Register cycle
is in progress. When one of these cycles is in progress, it is recommended to check the
Write In Progress (WIP) bit before sending a new instruction to the device. It is also possible
to read the Status Register continuously, as shown in Figure 9.

The Status Register format is shown in Ta b le 5 and the status and control bits of the Status
Register are as follows:

6.3.1 WIP bit

The Write In Progress (WIP) bit indicates whether the memory is busy with a Write or Write
Status Register cycle. When set to 1, such a cycle is in progress, when reset to 0 no such
cycle is in progress.

6.3.2 WEL bit

The Write Enable Latch (WEL) bit indicates the status of the internal Write Enable Latch.
When set to 1 the internal Write Enable Latch is set, when set to 0 the internal Write Enable
Latch is reset and no Write or Write Status Register instruction is accepted.

6.3.3 BP1, BP0 bits

The Block Protect (BP1, BP0) bits are non-volatile. They define the size of the area to be
software protected against Write instructions. These bits are written with the Write Status
Register (WRSR) instruction. When one or both of the Block Protect (BP1, BP0) bits is set to
1, the relevant memory area (as defined in Ta bl e 5 ) becomes protected against Write
(WRITE) instructions. The Block Protect (BP1, BP0) bits can be written provided that the
Hardware Protected mode has not been set.

6.3.4 SRWD bit

The Status Register Write Disable (SRWD) bit is operated in conjunction with the Write
Protect (W
signal allow the device to be put in the Hardware Protected mode (when the Status Register
Write Disable (SRWD) bit is set to 1, and Write Protect (W
non-volatile bits of the Status Register (SRWD, BP1, BP0) become read-only bits and the
Write Status Register (WRSR) instruction is no longer accepted for execution.

Table 5. Status Register format

Status Register Write Protect

) signal. The Status Register Write Disable (SRWD) bit and Write Protect (W)

b7 b0

SRWD 0 0 0 BP1 BP0 WEL WIP

) is driven low). In this mode, the

Block Protect bits

Write Enable Latch bit

Write In Progress bit

Doc ID 16877 Rev 15 19/48

Instructions M95640, M95640-W, M95640-R, M95640-DR

C

D

S

21 3456789101112131415

Instruction

0

AI02031E

Q

7 6543210

Status Register Out

High Impedance

MSB

7 6543210

Status Register Out

MSB

7

Figure 9. Read Status Register (RDSR) sequence

6.4 Write Status Register (WRSR)

The Write Status Register (WRSR) instruction allows new values to be written to the Status
Register. Before it can be accepted, a Write Enable (WREN) instruction must previously
have been executed.

The Write Status Register (WRSR) instruction is entered by driving Chip Select (S

) low,
sending the instruction code followed by the data byte on Serial Data input (D), and driving
the Chip Select (S

) signal high. Chip Select (S) must be driven high after the rising edge of
Serial Clock (C) that latches in the eighth bit of the data byte, and before the next rising edge
of Serial Clock (C). Otherwise, the Write Status Register (WRSR) instruction is not properly
executed.

Driving the Chip Select (S
timed write cycle that takes t

) signal high at a byte boundary of the input data triggers the self-

to complete (as specified in Ta bl e 1 8, Ta bl e 1 9 , Tab le 2 0 and

W

Ta bl e 2 1 ). The instruction sequence is shown in Figure 10.

While the Write Status Register cycle is in progress, the Status Register may still be read to
check the value of the Write in progress (WIP) bit: the WIP bit is 1 during the self-timed write
cycle t
reset at the end of the write cycle t

, and is 0 when the write cycle is complete. The WEL bit (Write enable latch) is also

W

.

W

The Write Status Register (WRSR) instruction allows the user to change the values of the
BP1, BP0 bits and the SRWD bit:

● The Block protect (BP1, BP0) bits define the size of the area that is to be treated as

read only, as defined in Tab l e 2 .

● The SRWD bit (Status register write disable bit), in accordance with the signal read on

the Write protect pin (W

), allows the user to set or reset the write protection mode of the
Status Register itself, as shown in Ta bl e 6 . When in the Write-protected mode, the
Write Status Register (WRSR) instruction is not executed.

The contents of the SRWD and BP1, BP0 bits are updated after the completion of the
WRSR instruction, including the t

write cycle.

W

The Write Status Register (WRSR) instruction has no effect on the b6, b5, b4, b1 and b0
bits in the Status Register. Bits b6, b5, b4 are always read as 0.

20/48 Doc ID 16877 Rev 15

M95640, M95640-W, M95640-R, M95640-DR Instructions

Table 6. Protection modes

W

signal

10

00

11

01

1. As defined by the values in the Block Protect (BP1, BP0) bits of the Status Register, as shown in Table 2.

SRWD

bit

Mode Write protection of the Status Register

Software

protected

(SPM)

Hardware

protected

(HPM)

Status Register is Writable (if the WREN
instruction has set the WEL bit)
The values in the BP1 and BP0 bits can be
changed

Status Register is Hardware write protected
The values in the BP1 and BP0 bits cannot
be changed

Memory content

Protected area

Write Protected

Write Protected

(1)

Unprotected area

Ready to accept
Write instructions

Ready to accept
Write instructions

The protection features of the device are summarized in Tab l e 6 .

When the Status Register Write Disable (SRWD) bit of the Status Register is 0 (its initial
delivery state), it is possible to write to the Status Register provided that the Write Enable
Latch (WEL) bit has previously been set by a Write Enable (WREN) instruction, regardless
of whether Write Protect (W

) is driven high or low.

When the Status Register Write Disable (SRWD) bit of the Status Register is set to 1, two
cases need to be considered, depending on the state of Write Protect (W

● If Write Protect (W) is driven high, it is possible to write to the Status Register provided

that the Write enable latch (WEL) bit has previously been set by a Write Enable
(WREN) instruction.

● If Write Protect (W) is driven low, it is not possible to write to the Status Register even if

the Write Enable latch (WEL) bit has previously been set by a Write Enable (WREN)
instruction. (Attempts to write to the Status Register are rejected, and are not accepted
for execution). As a consequence, all the data bytes in the memory area that are
software-protected (SPM) by the Block protect (BP1, BP0) bits in the Status Register,
are also hardware-protected against data modification.

(1)

):

Regardless of the order of the two events, the Hardware-protected mode (HPM) can be
entered:

● by setting the Status register write disable (SRWD) bit after driving Write Protect (W)

low

● or by driving Write Protect (W) low after setting the Status register write disable

(SRWD) bit.

The only way to exit the Hardware-protected mode (HPM) once entered is to pull Write
Protect (W

If Write Protect (W

) high.

) is permanently tied high, the Hardware-protected mode (HPM) can
never be activated, and only the Software-protected mode (SPM), using the Block protect
(BP1, BP0) bits in the Status Register, can be used.

Table 7. Address range bits

Device 64 Kbit devices

Address bits A12-A0

1. b15 to b13 are Don’t Care.

(1)

Doc ID 16877 Rev 15 21/48

Instructions M95640, M95640-W, M95640-R, M95640-DR

C

D

AI02282D

S

Q

21 3456789101112131415

High Impedance

Instruction Status

Register In

0

765432 0

1

MSB

C

D

AI01793D

S

Q

15

21 345678910 2021222324252627

1413 3210

28 29 30

76543 1 7

0

High Impedance

Data Out 1

Instruction 16-Bit Address

0

MSB

MSB

2

31

Data Out 2

Figure 10. Write Status Register (WRSR) sequence

6.5 Read from Memory Array (READ)

As shown in Figure 11, to send this instruction to the device, Chip Select (S) is first driven
low. The bits of the instruction byte and address bytes are then shifted in, on Serial Data
Input (D). The address is loaded into an internal address register, and the byte of data at
that address is shifted out, on Serial Data Output (Q).

If Chip Select (S

) continues to be driven low, the internal address register is automatically

incremented, and the byte of data at the new address is shifted out.

When the highest address is reached, the address counter rolls over to zero, allowing the
Read cycle to be continued indefinitely. The whole memory can, therefore, be read with a
single READ instruction.

The Read cycle is terminated by driving Chip Select (S
Select (S

) signal can occur at any time during the cycle.

) high. The rising edge of the Chip

The first byte addressed can be any byte within any page.

The instruction is not accepted, and is not executed, if a Write cycle is currently in progress.

Figure 11. Read from Memory Array (READ) sequence

1. Depending on the memory size, as shown in Table 7, the most significant address bits are Don’t Care.

22/48 Doc ID 16877 Rev 15

M95640, M95640-W, M95640-R, M95640-DR Instructions

C

D

AI01795D

S

Q

15

21 345678910 2021222324252627

1413 3210

28 29 30

High Impedance

Instruction 16-Bit Address

0

765432 0

1

Data Byte

31

6.6 Write to Memory Array (WRITE)

As shown in Figure 12, to send this instruction to the device, Chip Select (S) is first driven
low. The bits of the instruction byte, address byte, and at least one data byte are then shifted
in, on Serial Data Input (D).

The instruction is terminated by driving Chip Select (S

) high at a byte boundary of the input
data. In the case of Figure 12, this occurs after the eighth bit of the data byte has been
latched in, indicating that the instruction is being used to write a single byte. The self-timed
Write cycle starts from the rising edge of Chip Select (S

), and continues for a period tWC (as
specified in Ta bl e 1 9 to Ta bl e 2 1), at the end of which the Write in Progress (WIP) bit is reset
to 0.

If, though, Chip Select (S

) continues to be driven low, as shown in Figure 13, the next byte of
input data is shifted in, so that more than a single byte, starting from the given address
towards the end of the same page, can be written in a single internal Write cycle.

Each time a new data byte is shifted in, the least significant bits of the internal address
counter are incremented. If the number of data bytes sent to the device exceeds the page
boundary, the internal address counter rolls over to the beginning of the page, and the
previous data there are overwritten with the incoming data. (The page size of these devices
is 32 bytes).

The instruction is not accepted, and is not executed, under the following conditions:

● if the Write Enable Latch (WEL) bit has not been set to 1 (by executing a Write Enable

instruction just before)

● if a write cycle is already in progress

● if the device has not been deselected, by Chip Select (S) being driven high, at a byte

boundary (after the eighth bit, b0, of the last data byte that has been latched in)

● if the addressed page is in the region protected by the Block Protect (BP1 and BP0)

bits.

Note: The self-timed write cycle t

is internally executed as a sequence of two consecutive

W

events: [Erase addressed byte(s)], followed by [Program addressed byte(s)]. An erased bit is
read as “0” and a programmed bit is read as “1”.

Figure 12. Byte Write (WRITE) sequence

1. Depending on the memory size, as shown in Table 7, the most significant address bits are Don’t Care.

Doc ID 16877 Rev 15 23/48

Instructions M95640, M95640-W, M95640-R, M95640-DR

C

D

AI01796D

S

3433 35 36 37 38 39 40 41 42 44 45 46 4732

C

D

S

15

21 345678910 2021222324252627

1413 3210

28 29 30

Instruction 16-Bit Address

0

765432 0

1

Data Byte 1

31

43

765432 0

1

Data Byte 2

765432 0

1

Data Byte 3

65432 0

1

Data Byte N

Figure 13. Page Write (WRITE) sequence

1. Depending on the memory size, as shown in Table 7, the most significant address bits are Don’t Care.

ECC (error correction code) and Write cycling

The M95640-x and M95640-Dx devices identified with the process letter K offer an ECC
(error correction code) logic which compares each 4-byte word with its associated 6
EEPROM bits of ECC. As a result, if a single bit out of 4 bytes of data happens to be
erroneous during a Read operation, the ECC detects it and replaces it with the correct
value. The read reliability is therefore much improved by the use of this feature.

Note however that even if a single byte has to be written, 4 bytes are internally modified
(plus the ECC bits), that is, the addressed byte is cycled together with the three other bytes
making up the word. It is therefore recommended to write data by word (4 Bytes) at address
4*N (where N is an integer) in order to benefit from the larger amount of Write cycles.

The M95640-x and M95640-Dx devices are qualified at 1 million (1 000 000) Write cycles,

6.7 Read Identification Page

using a cycling routine that writes to the device in multiples of 4-byte words.

The Identification Page (32 bytes) is an additional page which can be written and (later)
permanently locked in Read-only mode.

Reading this page is achieved with the Read Identification Page instruction (see Ta bl e 4 ).

The Chip Select signal (S) is first driven low, the bits of the instruction byte and address
bytes are then shifted in, on Serial Data input (D). Address bit A10 must be 0, address bits
[A15:A11] and [A9:A5] are Don't Care, and the data byte pointed to by [A4:A0] is shifted out
on Serial Data output (Q).

24/48 Doc ID 16877 Rev 15

M95640, M95640-W, M95640-R, M95640-DR Instructions

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If Chip Select (S) continues to be driven low, the internal address register is automatically
incremented and the byte of data at the new address is shifted out. The number of bytes to
read in the ID page must not exceed the page boundary (e.g.: when reading the ID page
from location 10d, the number of bytes should be less than or equal to 22d, as the ID page
boundary is 32 bytes).

The read cycle is terminated by driving Chip Select (S) high. The rising edge of the Chip
Select (S) signal can occur at any time during the cycle. The first byte addressed can be any
byte within any page.

The instruction is not accepted, and is not executed, if a write cycle is currently in progress.

Figure 14. Read Identification Page sequence

Doc ID 16877 Rev 15 25/48

Instructions M95640, M95640-W, M95640-R, M95640-DR

6.8 Write Identification Page

The Identification Page (32 bytes) is an additional page which can be written and (later)
permanently locked in Read-only mode. Writing this page is achieved with the Write
Identification Page instruction (see Ta bl e 4 ), the Chip Select signal (S) is first driven low. The
bits of the instruction byte, address byte, and at least one data byte are then shifted in on
Serial Data input (D). Address bit A10 must be 0, address bits [A15:A11] and [A9:A5] are
Don't Care, the [A4:A0] address bits define the byte address inside the identification page.

Figure 15. Write Identification Page sequence

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6.9 Read Lock Status

The Read Lock Status instruction is used to read the lock status. To send this instruction to
the device, Chip Select (S) first has to be driven low. The bits of the instruction byte and
address bytes are then shifted in on Serial Data input (D). Address bit A10 must be 1, all
other address bits are Don't Care. The Lock bit is the LSB (least significant bit) of the byte
read on Serial Data output (Q). It is at ‘1’ when the lock is active and at ‘0’ when the lock is
not active. If Chip Select (S) continues to be driven low, the same data byte is shifted out.

The read cycle is terminated by driving Chip Select (S) high. The instruction sequence is
shown in Figure 16.

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26/48 Doc ID 16877 Rev 15

M95640, M95640-W, M95640-R, M95640-DR Instructions

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Figure 16. Read Lock Status sequence

6.10 Lock ID

The Lock ID instruction permanently locks the Identification Page in read-only mode. Before
this instruction can be accepted, a Write Enable (WREN) instruction must have been
executed. The Lock ID instruction is issued by driving Chip Select (S) low, sending the
instruction code, the address and a data byte on Serial Data input (D), and driving Chip
Select (S) high. In the address sent, A10 must be equal to 1, all other address bits are Don't
Care. The data byte sent must be equal to the binary value xxxx xx1x, where x = Don't Care.

Chip Select (S) must be driven high after the rising edge of Serial Clock (C) that latches in
he eighth bit of the data byte, and before the next rising edge of Serial Clock (C). Otherwise,
the Lock ID instruction is not executed.

Driving Chip Select (S) high at a byte boundary of the input data triggers the self-timed write
cycle which duration is t

(specified in Ta bl e 1 8, Ta b le 1 9 , Ta bl e 2 0 and Tab le 2 1 ). The

W

instruction sequence is shown in Figure 17.

Figure 17. Lock ID sequence

3

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Doc ID 16877 Rev 15 27/48

Power-up and delivery state M95640, M95640-W, M95640-R, M95640-DR

7 Power-up and delivery state

7.1 Power-up state

After Power-up, the device is in the following state:

● Standby Power mode

● deselected (after power-up, a falling edge is required on Chip Select (S) before any

instructions can be started).

● not in the Hold condition

● the Write Enable Latch (WEL) is reset to 0

● Write In Progress (WIP) is reset to 0

The SRWD, BP1 and BP0 bits of the Status Register are unchanged from the previous
power-down (they are non-volatile bits).

7.2 Initial delivery state

The device is delivered with the memory array set to all 1s (each byte = FFh). The Status
register write disable (SRWD) and Block protect (BP1 and BP0) bits are initialized to 0.

28/48 Doc ID 16877 Rev 15

M95640, M95640-W, M95640-R, M95640-DR Maximum rating

8 Maximum rating

Stressing the device outside the ratings listed in Ta bl e 8 may cause permanent damage to
the device. These are stress ratings only, and operation of the device at these, or any other
conditions outside those indicated in the operating sections of this specification, is not
implied. Exposure to absolute maximum rating conditions for extended periods may affect
device reliability. Refer also to the STMicroelectronics SURE Program and other relevant
quality documents.

Table 8. Absolute maximum ratings

Symbol Parameter Min. Max. Unit

T

STG

Storage temperature –65 150 °C

Ambient operating temperature –40 130 °C

T

LEAD

V

O

V

I

OL

I

OH

V

CC

V

ESD

1. Compliant with JEDEC Std J-STD-020 (for small body, Sn-Pb or Pb assembly), the ST ECOPACK®

7191395 specification, and the European directive on Restrictions on Hazardous Substances (RoHS)
2002/95/EU

2. AEC-Q100-002 (compliant with JEDEC Std JESD22-A114, C1 = 100 pF, R1 = 1500 Ω, R2 = 500 Ω)

Lead temperature during soldering See note

Output voltage –0.50 VCC+0.6 V

Input voltage –0.50 6.5 V

I

DC output current (Q = 0) 5 mA

DC output current (Q = 1) –5 mA

Supply voltage –0.50 6.5 V

Electrostatic discharge voltage (human body

(2)

model)

(1)

4000 V

°C

Doc ID 16877 Rev 15 29/48

DC and AC parameters M95640, M95640-W, M95640-R, M95640-DR

AI00825B

0.8V

CC

0.2V

CC

0.7V

CC

0.3V

CC

Input and Output

Timing Reference Levels

Input Levels

9 DC and AC parameters

This section summarizes the operating and measurement conditions, and the DC and AC
characteristics of the device. The parameters in the DC and AC characteristic tables that
follow are derived from tests performed under the measurement conditions summarized in
the relevant tables. Designers should check that the operating conditions in their circuit
match the measurement conditions when relying on the quoted parameters.

Table 9. Operating conditions (M95640 device grade 3)

Symbol Parameter Min. Max. Unit

V

T

Table 10. Operating conditions (M95640-W)

Supply voltage 4.5 5.5 V

CC

Ambient operating temperature (device grade 3) –40 125 °C

A

Symbol Parameter Min. Max. Unit

V

CC

Supply voltage 2.5 5.5 V

Ambient operating temperature (device grade 6) –40 85 °C

T

A

Ambient operating temperature (device grade 3) –40 125 °C

Table 11. Operating conditions (M95640-R device grade 6)

Symbol Parameter Min. Max.

V

CC

T

A

Table 12. AC measurement conditions

Supply voltage 1.8 5.5 V

Ambient operating temperature –40 85 °C

(1)

Symbol Parameter Min. Max. Unit

C

Load capacitance 30 pF

L

Input rise and fall times 25 ns

Input pulse voltages 0.2V

Input and output timing reference voltages 0.3V

1. Output Hi-Z is defined as the point where data out is no longer driven.

to 0.8V

CC

to 0.7V

CC

CC

CC

Unit

V

V

Figure 18. AC measurement I/O waveform

30/48 Doc ID 16877 Rev 15

M95640, M95640-W, M95640-R, M95640-DR DC and AC parameters

Table 13. Capacitance

(1)

Symbol Parameter Test condition Max. Unit

C

OUT

C

1. Sampled only, not 100% tested.

Table 14. DC characteristics (M95640, device grade 3)

Output capacitance (Q) V

Input capacitance (D) VIN = 0 V 8 pF

IN

Input capacitance (other pins) V

= 0 V 8 pF

OUT

= 0 V 6 pF

IN

Symbol Parameter Test condition Min. Max. Unit

Input leakage current V

I

LI

I

Output leakage current S = VCC, V

LO

I

Supply current

CC

I

V

V

OH

V

RES

1. For all 5 V range devices, the device meets the output requirements for both TTL and CMOS standards.

2. Characterized only, not 100% tested.

Supply current

CC1

(Standby Power mode)

V

Input low voltage –0.45 0.3 V

IL

Input high voltage 0.7 V

V

IH

(1)

Output low voltage IOL = 2 mA, VCC = 5 V 0.4 V

OL

(1)

Output high voltage IOH = –2 mA, VCC = 5 V 0.8 V

Internal reset threshold

(2)

voltage

= VSS or V

IN

C=0.1V

CC

= VSS or V

OUT

/0.9VCC at 5 MHz,

CC

VCC= 5V, Q = open

C=0.1V
V

CC

S = VCC, V

= VSS or V

V

IN

/0.9VCC at 10 MHz,

CC

= 5V, Q = open

= 5 V,

CC

CC

CC

± 2 µA

± 2 µA

4mA

8mA

5µA

CC

CCVCC

CC

+1 V

2.5 4.0 V

V

V

Doc ID 16877 Rev 15 31/48

DC and AC parameters M95640, M95640-W, M95640-R, M95640-DR

Table 15. DC characteristics (M95640-W, device grade 6)

Symbol Parameter Test condition Min. Max. Unit

I

V

I

LO

I

CC

I

CC0

I

CC1

V

V

V

OL

V

OH

RES

Input leakage current V

LI

Output leakage current S = VCC, V

Supply current (Read)

Supply current (Write)

Supply current
(Standby Power mode)

Input low voltage –0.45 0.3V

IL

Input high voltage 0.7VCCVCC+1 V

IH

Output low voltage

Output high voltage

Internal reset threshold

(3)

voltage

= VSS or V

IN

CC

OUT

= VSS or V

CC

VCC= 2.5 V, C = 0.1VCC/0.9V
fC = 5 MHz, Q = open

V

= 2.5 V, C = 0.1VCC/0.9V

CC

fC = 10 MHz, Q = open

VCC= 5.5 V, C = 0.1VCC/0.9V
fC = 20 MHz, Q = open

2.5 V < V
S = V

S

= VCC, VCC = 5.5 V

= VSS or V

V

IN

S = VCC, V
V

= VSS or V

IN

S = VCC, V

= VSS or V

V

IN

V

= 2.5 V and IOL = 1.5 mA, or

CC

< 5.5 V, during tW,

CC

CC

CC

= 5.0 V

CC

CC

= 2.5 V

CC

CC

VCC = 5 V and IOL = 2 mA

= 2.5 V and IOH = 0.4 mA, or

V

CC

= 5 V and IOH = 2 mA

V

CC

CC,

CC,

CC,

0.8V

1.0

CC

(4)

± 2 µA

± 2 µA

3

(1)

2

5

mA

(1)

5mA

(1)

3

CC

µA

V

2

(2)

1

0.4 V

V

(5)

1.65

V

1. Only for the device identified with process letter K.

2. 2 µA with the device identified with process letter K.

3. Characterized only, not 100% tested.

4. 0.7 V with the device identified with process letter K.

5. 1.3 V with the device identified with process letter K.

32/48 Doc ID 16877 Rev 15

M95640, M95640-W, M95640-R, M95640-DR DC and AC parameters

Table 16. DC characteristics (M95640-W, device grade 3)

Symbol Parameter Test condition Min. Max. Unit

I

Input leakage current V

LI

Output leakage current S = VCC, V

I

LO

I

Supply current (Read)

CC

= VSS or V

IN

f

= 5 MHz, VCC=2.5V,

C

C = 0.1V

= 10 MHz, VCC=2.5V,

f

C

CC

= VSS or V

OUT

/0.9VCC, Q = open

CC

CC

C = 0.1VCC/0.9VCC, Q = open

± 2 µA

± 2 µA

3

mA

6

I

I

V

V

RES

1. Characterized only, not 100% tested.

Table 17. DC characteristics (M95640-R, M95640-DR, device grade 6)

Supply current (Write) 2.5 V < VCC < 5.5 V, during tW, S = V

CC0

= VCC, V

Supply current (Standby

CC1

Power mode)

V

Input low voltage –0.45 0.3V

IL

Input high voltage 0.7VCCVCC+1 V

V

IH

V

Output low voltage IOL = 1.5 mA, VCC = 2.5 V 0.4 V

OL

Output high voltage IOH = –0.4 mA, VCC = 2.5 V 0.8V

OH

Internal reset threshold

(1)

S
V

CC

= 2.5 V

= VSS or V

IN

CC

voltage

CC

1.0 1.65 V

6mA

2µA

CC

CC

(1)

Symbol Parameter Test condition Min. Max. Unit

I

Input leakage current V

LI

Output leakage current S = VCC, V

I

LO

I

Supply current (Read)

CC

= VSS or V

IN

V

= 1.8 V, C = 0.1VCC/0.9VCC,

CC

Q = open, f

= 1.8 V, C = 0.1VCC/0.9VCC,

V

CC

CC

= VSS or V

OUT

= 2 MHz

C

Q = open, fC = 5 MHz

CC

± 2 µA

± 2 µA

2mA

2mA

V

V

I

I

V

V

V

V

RES

1. If the application uses the M95640-R device with 2.5 V < VCC < 5.5 V and -40 °C < TA < +85 °C, please

2. Characterized only, not 100% tested.

3. 0.7 V with the device identified with process letter K.

4. 1.3 V with the device identified with process letter K.

Supply current (Write) VCC= 1.8 V, during tW, S = V

CC0

Supply current (Standby

CC1

mode)

V

Input low voltage 1.8 V ≤ VCC < 2.5 V –0.45 0.25V

IL

Input high voltage 1.8 V ≤ VCC < 2.5 V 0.75V

IH

Output low voltage VCC = 1.8 V, IOL = 0.15 mA 0.3 V

OL

Output high voltage VCC = 1.8 V, IOH = –0.1 mA 0.8 V

OH

Internal reset threshold

(2)

VCC= 1.8 V, S = VCC,
V

= VSS or V

IN

CC

voltage

refer to Table 15: DC characteristics (M95640-W, device grade 6) instead of the above table.

CC

1.0

(3)

CCVCC

CC

5mA

1µA

CC

+1 V

(4)

1.65

Doc ID 16877 Rev 15 33/48

V

V

V

DC and AC parameters M95640, M95640-W, M95640-R, M95640-DR

Table 18. AC characteristics (M95640, device grade 3)

Test conditions specified in Tab l e 9 and Tab l e 12

Symbol Alt. Parameter Min.

f

C

t

SLCH

t

SHCH

t

SHSL

t

CHSH

t

CHSL

t

CH

(3)

t

CL

t

CLCH

t

CHCL

t

DVC H

t

CHDX

t

HHCH

t

HLCH

t

CLHL

t

CLHH

t

SHQZ

t

CLQV

t

CLQX

t

QLQH

t

QHQL

t

HHQV

t

HLQZ

t

W

1. These timings are offered with grade 3 devices referenced with “/P” process letters only (see the last digits in Part

numbering).

2. These timings are offered with grade 3 devices referenced with “/PC” process letters only (see the last digits in Part

numbering).

3. t

CH

4. Value guaranteed by characterization, not 100% tested in production.

5. t

CLQV

equal to (or greater than) t

f

Clock frequency D.C. 5 D.C. 10 MHz

SCK

t

t

S active setup time 90 30 ns

CSS1

S not active setup time 90 30 ns

CSS2

t

S deselect time 100 40 ns

CS

t

S active hold time 90 30 ns

CSH

S not active hold time 90 30 ns

(3)

t

Clock high time 90 42 ns

CLH

t

Clock low time 90 40 ns

CLL

(4)

t

Clock rise time 1 2 µs

RC

(4)

t

Clock fall time 1 2 µs

FC

t

Data in setup time 20 10 ns

DSU

t

Data in hold time 30 10 ns

DH

Clock low hold time after HOLD not active 70 30 ns

Clock low hold time after HOLD active 40 30 ns

Clock low set-up time before HOLD active 0 0 ns

Clock low set-up time before HOLD not active 0 0 ns

(4)

t

Output disable time 100 40 ns

DIS

(5)

(4)

+ tCL must never be lower than the shortest possible clock period, 1/fC(max).

t

Clock low to output valid 60 40 ns

V

t

Output hold time 0 0 ns

HO

(4)

t

Output rise time 50 40 ns

RO

(4)

t

Output fall time 50 40 ns

FO

t

HOLD high to output valid 50 40 ns

LZ

t

HOLD low to output high-Z 100 40 ns

HZ

t

Write time 5 5 ms

WC

must be compatible with tCL (clock low time): if the SPI bus master offers a Read setup time tSU = 0 ns, tCL can be

; in all other cases, tCL must be equal to (or greater than) t

CLQV

(1)

Max.

(1)

Min.

CLQV+tSU

(2)

.

Max.

(2)

Unit

34/48 Doc ID 16877 Rev 15

M95640, M95640-W, M95640-R, M95640-DR DC and AC parameters

Table 19. AC characteristics (M95640-W products, device grade 6)

Test conditions specified in Tab l e 1 0 and Ta b l e 1 2

Min. Max. Min. Max.

Symbol Alt. Parameter

= 2.5 to 5.5 V

V

CC

f

C

t

SLCH

t

SHCH

t

SHSL

t

CHSH

t

CHSL

t

CH

t

CL

t

CLCH

t

CHCL

t

DVC H

t

CHDX

t

HHCH

t

HLCH

t

CLHL

t

CLHH

t

SHQZ

t

CLQV

t

CLQX

t

QLQH

t

QHQL

t

HHQV

t

HLQZ

t

W

1. Preliminary data for the devices identified with process letter K.

2. t

CH

3. Value guaranteed by characterization, not 100% tested in production.

4. t

CLQV

equal to (or greater than) t

f

Clock frequency D.C. 10 D.C. 20 MHz

SCK

t

t

S active setup time 30 15 ns

CSS1

S not active setup time 30 15 ns

CSS2

t

S deselect time 40 20 ns

CS

t

S active hold time 30 15 ns

CSH

S not active hold time 30 15 ns

(2)

t

Clock high time 42 20 ns

CLH

(2)

(3)

(3)

t

Clock low time 40 20 ns

CLL

t

Clock rise time 2 2 µs

RC

t

Clock fall time 2 2 µs

FC

t

Data in setup time 10 5 ns

DSU

t

Data in hold time 10 10 ns

DH

Clock low hold time after HOLD not active 30 15 ns

Clock low hold time after HOLD active 30 15 ns

Clock low set-up time before HOLD active 0 0 ns

Clock low set-up time before HOLD not active 0 0 ns

(3)

t

Output disable time 40 20 ns

DIS

(4)

(3)

(3)

(3)

+ tCL must never be lower than the shortest possible clock period, 1/fC(max).

t

Clock low to output valid 40 20 ns

V

t

Output hold time 0 0 ns

HO

t

Output rise time 40 20 ns

RO

t

Output fall time 40 20 ns

FO

t

HOLD high to output valid 40 20 ns

LZ

t

HOLD low to output high-Z 40 20 ns

HZ

t

Write time 5 5 ms

WC

must be compatible with tCL (clock low time): if the SPI bus master offers a Read setup time tSU = 0 ns, tCL can be

; in all other cases, tCL must be equal to (or greater than) t

CLQV

New products

VCC = 4.5 to 5.5 V

CLQV+tSU

.

(1)

Unit

Doc ID 16877 Rev 15 35/48

DC and AC parameters M95640, M95640-W, M95640-R, M95640-DR

Table 20. AC characteristics (M95640-W products, device grade 3)

Test conditions: VCC = 2.5 to 5.5 V, TA = –40 to 125°C

Min. Max. Min. Max.

Symbol Alt. Parameter

2.5V to 5.5V

f

C

t

SLCHtCSS1

t

SHCHtCSS2

t

SHSL

t

CHSH

t

CHSL

t

CH

t

CL

t

CLCH

t

CHCL

t

DVC H

t

CHDX

t

HHCH

t

HLCH

t

CLHL

t

CLHH

t

SHQZ

t

CLQV

t

CLQX

t

QLQH

t

QHQL

t

HHQV

t

HLQZ

t

W

1. These timings are offered with grade 3 devices referenced with “/P” process letters only (see the last digits in Part

numbering).

2. These timings are offered with grade 3 devices referenced with “/PC” process letters only (see the last digits in Part

numbering).

3. t

CH

4. Value guaranteed by characterization, not 100% tested in production.

5. t

CLQV

equal to (or greater than) t

f

Clock frequency D.C. 5 D.C. 10 MHz

SCK

S active setup time 90 30 ns

S not active setup time 90 30 ns

t

S deselect time 100 40 ns

CS

t

S active hold time 90 30 ns

CSH

S not active hold time 90 30 ns

(3)

t

Clock high time 90 42 ns

CLH

(3)

(4)

(4)

t

Clock low time 90 40 ns

CLL

t

Clock rise time 1 2 µs

RC

t

Clock fall time 1 2 µs

FC

t

Data in setup time 20 10 ns

DSU

t

Data in hold time 30 10 ns

DH

Clock low hold time after HOLD not active 70 30 ns

Clock low hold time after HOLD active 40 30 ns

Clock low set-up time before HOLD active 0 0 ns

Clock low set-up time before HOLD not active 0 0 ns

(4)

t

Output disable time 100 40 ns

DIS

(5)

t

Clock low to output valid 60 40 ns

V

t

Output hold time 0 0 ns

HO

(4)

t

Output rise time 50 40 ns

RO

(4)

t

Output fall time 50 40 ns

FO

t

HOLD high to output valid 50 40 ns

LZ

(4)

t

HOLD low to output high-Z 100 40 ns

HZ

t

Write time 5 5 ms

WC

+ tCL must never be lower than the shortest possible clock period, 1/fC(max).

must be compatible with tCL (clock low time): if the SPI bus master offers a Read setup time tSU = 0 ns, tCL can be

; in all other cases, tCL must be equal to (or greater than) t

CLQV

(1)

3.0 V to 5.5 V

CLQV+tSU

(2)

.

Unit

36/48 Doc ID 16877 Rev 15

M95640, M95640-W, M95640-R, M95640-DR DC and AC parameters

Table 21. AC characteristics (M95640-R, M95640-DR devices, grade 6)

Test conditions specified in Tab l e 1 1 and Ta b l e 1 3

Min. Max. Min. Max.

Symbol Alt. Parameter

f

C

t

SLCH

t

SHCH

t

SHSL

t

CHSH

t

CHSL

(3)

t

CH

(2)

t

CL

t

CLCH

t

CHCL

t

DVC H

t

CHDX

t

HHCH

t

HLCH

t

CLHL

t

CLHH

t

SHQZ

t

CLQV

t

CLQX

t

QLQH

t

QHQL

t

HHQV

t

HLQZ

t

W

1. Current products are identified by process letters P.

2. Preliminary data for the new products identified by process letter K. If the application uses the M95640-R device with 2.5 V
< V

CC

instead of the above table.

+ tCL must never be lower than the shortest possible clock period, 1/fC(max).

3. t

CH

4. Value guaranteed by characterization, not 100% tested in production.

5. t

CLQV

equal to (or greater than) t

f

Clock frequency D.C. 2 D.C. 5 MHz

SCK

t

t

S active setup time 150 60 ns

CSS1

S not active setup time 150 60 ns

CSS2

t

S deselect time 200 90 ns

CS

t

S active hold time 150 60 ns

CSH

S not active hold time 150 60 ns

t

Clock high time 200 80 ns

CLH

t

Clock low time 200 80 ns

CLL

(4)

t

Clock rise time 2 2 µs

RC

(3)

t

Clock fall time 2 2 µs

FC

t

Data in setup time 50 20 ns

DSU

t

Data in hold time 50 20 ns

DH

Clock low hold time after HOLD not active 150 60 ns

Clock low hold time after HOLD active 150 60 ns

Clock low set-up time before HOLD active 0 0 0

Clock low set-up time before HOLD not active 0 0 0

(3)

t

Output disable time 200 80 ns

DIS

(5)

(3)

(3)

(3)

t

Clock low to output valid 200 80 ns

V

t

Output hold time 0 0 ns

HO

t

Output rise time 200 80 ns

RO

t

Output fall time 200 80 ns

FO

t

HOLD high to output valid 200 80 ns

LZ

t

HOLD low to output high-Z 200 80 ns

HZ

t

Write time 5 5 ms

WC

< 5.5 V and -40 °C < TA < +85 °C, please refer to Table 19: AC characteristics (M95640-W products, device grade 6)

must be compatible with tCL (clock low time): if the SPI bus master offers a Read setup time tSU = 0 ns, tCL can be

; in all other cases, tCL must be equal to (or greater than) t

CLQV

Current

products

(1)

CLQV+tSU

New products

(2)

.

Unit

Doc ID 16877 Rev 15 37/48

DC and AC parameters M95640, M95640-W, M95640-R, M95640-DR

C

D

AI01447d

S

MSB IN

Q

tDVCH

High impedance

LSB IN

tSLCH

tCHDX

tCLCH

tSHCH

tSHSL

tCHSHtCHSL

tCH

tCL

tCHCL

C

Q

AI01448c

S

HOLD

tCLHL

tHLCH

tHHCH

tCLHH

tHHQVtHLQZ

Figure 19. Serial input timing

Figure 20. Hold timing

38/48 Doc ID 16877 Rev 15

M95640, M95640-W, M95640-R, M95640-DR DC and AC parameters

C

Q

AI01449f

S

D

ADDR

LSB IN

tSHQZ

tCH

tCL

tQLQH
tQHQL

tCHCL

tCLQX

tCLQV

tSHSL

tCLCH

Figure 21. Serial output timing

Doc ID 16877 Rev 15 39/48

Package mechanical data M95640, M95640-W, M95640-R, M95640-DR

SO-A

E1

8

ccc

b

e

A

D

c

1

E

h x 45˚

A2

k

0.25 mm

L

L1

A1

GAUGE PLANE

10 Package mechanical data

In order to meet environmental requirements, ST offers these devices in different grades of
ECOPACK
specifications, grade definitions and product status are available at: www.st.com.
ECOPACK

®

packages, depending on their level of environmental compliance. ECOPACK®

®

is an ST trademark.

Figure 22. SO8N – 8-lead plastic small outline, 150 mils body width, package outline

1. Drawing is not to scale.

Table 22. SO8N – 8-lead plastic small outline, 150 mils body width, package

mechanical data

millimeters inches

Symbol

Typ Min Max Typ Min Max

(1)

A 1.75 0.0689

A1 0.10 0.25 0.0039 0.0098

A2 1.25 0.0492

b 0.28 0.48 0.011 0.0189

c 0.17 0.23 0.0067 0.0091

ccc 0.10 0.0039

D 4.90 4.80 5.00 0.1929 0.189 0.1969

E 6.00 5.80 6.20 0.2362 0.2283 0.2441

E1 3.90 3.80 4.00 0.1535 0.1496 0.1575

e1.27– –0.05- -

h 0.25 0.50 0.0098 0.0197

k 0°8° 0°8°

L 0.40 1.27 0.0157 0.05

L1 1.04 0.0409

1. Values in inches are converted from mm and rounded to 4 decimal digits.

40/48 Doc ID 16877 Rev 15

M95640, M95640-W, M95640-R, M95640-DR Package mechanical data

TSSOP8AM

1

8

CP

c

L

EE1

D

A2A

α

eb

4

5

A1

L1

Figure 23. TSSOP8 – 8-lead thin shrink small outline, package outline

1. Drawing is not to scale.

Table 23. TSSOP8 – 8-lead thin shrink small outline, package mechanical data

millimeters inches

Symbol

Typ. Min. Max. Typ. Min. Max.

(1)

A 1.200 0.0472

A1 0.050 0.150 0.0020 0.0059

A2 1.000 0.800 1.050 0.0394 0.0315 0.0413

b 0.190 0.300 0.0075 0.0118

c 0.090 0.200 0.0035 0.0079

CP 0.100 0.0039

D 3.000 2.900 3.100 0.1181 0.1142 0.1220

e 0.650 – – 0.0256 – –

E 6.400 6.200 6.600 0.2520 0.2441 0.2598

E1 4.400 4.300 4.500 0.1732 0.1693 0.1772

L 0.600 0.450 0.750 0.0236 0.0177 0.0295

L1 1.000 0.0394

α 0° 8° 0° 8°

1. Values in inches are converted from mm and rounded to 4 decimal digits.

Doc ID 16877 Rev 15 41/48

Package mechanical data M95640, M95640-W, M95640-R, M95640-DR

$

%

:7?-%E

!

!

EEE

,

E

B

$

,

%

,

,

E B

$

,

%

,

0IN

+

+

-" -#

Figure 24. UFDFPN8 (MLP8) - 8-lead ultra thin fine pitch dual flat no lead, package

outline

1. Drawing is not to scale.

2. The central pad (the area E2 by D2 in the above illustration) is internally pulled to V
connected to any other voltage or signal line on the PCB, for example during the soldering process.

Table 24. UFDFPN8 (MLP8) 8-lead ultra thin fine pitch dual flat package no lead

. It must not be

SS

2 x 3 mm, data

millimeters inches

Symbol

Typ Min Max Typ Min Max

(1)

A 0.550 0.450 0.600 0.0217 0.0177 0.0236

A1 0.020 0.000 0.050 0.0008 0.0000 0.0020

b 0.250 0.200 0.300 0.0098 0.0079 0.0118

D 2.000 1.900 2.100 0.0787 0.0748 0.0827

D2 (rev MB) 1.600 1.500 1.700 0.0630 0.0591 0.0669

D2 (rev MC) 1.200 1.600 0.0472 0.0630

E 3.000 2.900 3.100 0.1181 0.1142 0.1220

E2 (rev MB) 0.200 0.100 0.300 0.0079 0.0039 0.0118

E2 (rev MC) 1.200 1.600 0.0472 0.0630

e 0.500 0.0197

K 0.300 0.0118

L 0.300 0.500 0.0118 0.0197

L1 0.150 0.0059

L3 0.300 0.0118

(2)

eee

1. Values in inches are converted from mm and rounded to 4 decimal digits.

2. Applied for exposed die paddle and terminals. Exclude embedding part of exposed die paddle from
measuring.

0.080 0.0031

42/48 Doc ID 16877 Rev 15

M95640, M95640-W, M95640-R, M95640-DR Part numbering

11 Part numbering

Table 25. Ordering information scheme

Example: M95640 – W MN 6 T P /P

Device type

M95 = SPI serial access EEPROM

Device function

640 = 64 Kbit (8192 × 8)
640-D = 64 Kbit (8192 × 8) plus Identification Page

Operating voltage

blank = V
W = V
R = V

= 4.5 to 5.5 V

CC

= 2.5 to 5.5 V

CC

= 1.8 to 5.5 V

CC

Package

(1)

MN = SO8 (150 mils width)
DW = TSSOP8 (169 mils width)
MB or MC = MLP8 (2 × 3 mm)

Device grade

6 = Industrial temperature range, –40 to 85 °C.
Device tested with standard test flow
3 = Device tested with high reliability certified flow

(2)

automotive temperature range

(–40 to 125 °C)

Option

blank = Standard packing
T = Tape and reel packing

Plating technology

P or G = ECOPACK (RoHS compliant)

Process letter

(3)

/P or /PC = DP26%
K= F8H

1. All packages are ECOPACK2® (RoHS compliant and Halogen-free).

2. ST strongly recommends the use of the Automotive Grade devices for use in an automotive environment.
The high reliability certified flow (HRCF) is described in the quality note QNEE9801. Please ask your
nearest ST sales office for a copy.

3. Used only for devices grade 3.

For a list of available options (speed, package, etc.) or for further information on any aspect
of this device, please contact your nearest ST sales office.

Doc ID 16877 Rev 15 43/48

Revision history M95640, M95640-W, M95640-R, M95640-DR

12 Revision history

Table 26. Document revision history

Date Revision Changes

Human Body Model meets JEDEC std (Table 2). Minor adjustments on pp

13-Jul-2000 1.2

16-Mar-2001 1.3

19-Jul-2001 1.4 M95160 and M95080 devices removed to their own data sheet

1,11,15. New clause on p7. Addition of TSSOP8 package on pp 1, 2,
Ordering Info, Mechanical Data

Test condition added I

and ILO, and specification of t

LI

DLDH

and t

DHDL

removed.

, t

, t

t

CLCH

CHCL

DLDH

and t

changed to 50ns for the -V range.

DHDL

“-V” Voltage range changed to “2.7V to 3.6V” throughout.
Maximum lead soldering time and temperature conditions updated.
Instruction sequence illustrations updated.
“Bus Master and Memory Devices on the SPI bus” illustration updated.
Package Mechanical data updated

06-Dec-2001 1.5

Endurance increased to 1M write/erase cycles
Instruction sequence illustrations updated

18-Dec-2001 2.0 Document reformatted using the new template. No parameters changed.

Announcement made of planned upgrade to 10MHz clock for the 5V, –40

08-Feb-2002 2.1

to 85°C, range.
Endurance set to 100K write/erase cycles

10MHz, 5MHz, 2MHz clock; 5ms, 10ms Write Time; 100K, 1M erase/write

18-Dec-2002 2.2

cycles distinguished on front page, and in the DC and AC Characteristics
tables

26-Mar-2003 2.3

26-Jun-2003 2.4

15-Oct-2003 3.0 Table of contents, and Pb-free options added. V

21-Nov-2003 3.1 V

Process identification letter corrected in footnote to AC Characteristics
table for temp. range 3

-S voltage range upgraded by removing it and inserting -R voltage range
in its place

(min) improved to -0.45V

IL

(min) and VO(min) corrected (improved) to -0.45V

I

28-Jan-2004 4.0 TSSOP8 connections added to DIP and SO connections

M95320-S and M95640-S root part numbers (1.65 to 5.5V Supply) and
related characteristics added.

20MHz Clock rate added.TSSOP14 package removed and MLP8 package
added.

Description of Power On Reset: VCC Lock-Out Write Protect updated.

24-May-2005 5.0

Product List summary table added. Absolute Maximum Ratings for

(min) and VCC(min) improved. Soldering temperature information

V

IO

clarified for RoHS compliant devices. Device Grade 3 clarified, with
reference to HRCF and automotive environments. AEC-Q100-002
compliance. t
process. t

HHQX

(min) and t

CHHL

corrected to t

(min) is tCH for products under “S”

CHHH

.

HHQV

Figure 20: Hold timing updated.

44/48 Doc ID 16877 Rev 15

M95640, M95640-W, M95640-R, M95640-DR Revision history

Table 26. Document revision history (continued)

Date Revision Changes

Document converted to new ST template.
Packages are ECOPACK® compliant. PDIP package removed.

SO8N package specifications updated (see Ta b le 2 2 and Figure 22).
M95640-S and M95320-S part numbers removed (DC and AC parameters

updated accordingly).

How to identify previous, current and new products by the Process
identification letter Table removed.
Figure 4: SPI modes supported updated and Note 2 added. First three

07-Jul-2006 6

09-Oct-2007 7

paragraphs of Section 4: Operating features replaced by Section 4.1:

Supply voltage (VCC).

added to Table 8: Absolute maximum ratings. ICC and I

T

A

updated in

CC1

Ta bl e 1 3 , Tab l e 14 , Ta bl e 15 and Tab le 1 9 . VOL and VOH updated in
Ta bl e 1 5 . I

updated in Ta b l e 16 . Data in Ta b le 1 9 is no longer

CC

preliminary.

updated in Ta b le 1 9 . Table 21: AC characteristics (M95640-R) added.

t

CH

Timing line of t

modified in Figure 21: Serial output timing.

SHQZ

Process letter added to Table 25: Ordering information scheme, Note 2

removed. Note 2 removed from Figure 2.

JEDEC standard revision updated to D in Note 1 below Table 8: Absolute

maximum ratings.

Note 2 removed below Figure 3 and explanatory paragraph added.

Section 4.1: Supply voltage (VCC) updated. Table 7: Address range bits

corrected.
Products operating at V

= 4.5 V to 5.5 V are no longer available in the

CC

device grade 6 TA temperature range.
I

CC

and I

parameters modified in Table 15: DC characteristics

CC1

(M95640-W, device grade 6).

Maximum frequency for M95320-W and M95640-W upgraded from 5 MHz
to 10 MHz in the device grade 6 T

temperature range (Table 19: AC

A

characteristics (M95640-W products, device grade 6) modified

accordingly).

Table 27: Available M95640x products (package, voltage range,
temperature grade): /PB process letter added, /P process letter removed.

Blank option removed below Plating technology in Table 25: Ordering

information scheme.
Ta bl e 2 5 and Tab l e 27 added. Small text changes.
Table 24: UFDFPN8 (MLP8) - 8-lead ultra thin fine pitch dual flat no lead,

package mechanical data updated.

Package mechanical inch values calculated from mm and rounded to 4
decimal digits in Section 10: Package mechanical data.

17-Dec-2007 8

Section 2.7: VSS ground added.

Device behavior when V

passes over the POR threshold updated (see

CC

Section 4.1.2: Device reset and Section 4.1.4: Power-down).

and VIH modified in Table 19: DC characteristics (M95640-DF, device

V

IL

grade 6).

, write time, modified in Table 20: AC characteristics (M95320-R) and

t

W

Table 21: AC characteristics (M95640-R). Small text changes.

Doc ID 16877 Rev 15 45/48

Revision history M95640, M95640-W, M95640-R, M95640-DR

Table 26. Document revision history (continued)

Date Revision Changes

Section 4.1: Supply voltage (VCC) updated.

10 MHz frequencies added to Table 18: AC characteristics (M95640,

20-Mar-2008 9

23-Jun-2008 10

17-Feb-2009 11

07-Dec-2009 12

21-Dec-2010 13

device grade 3) and Table 20: AC characteristics (M95640-W products,
device grade 3).

Small text changes.

Section 4.1: Supply voltage (VCC) updated.
Table 19: DC characteristics (M95640-DF, device grade 6) modified.
Figure 19: Serial input timing, Figure 20: Hold timing and Figure 21: Serial

output timing modified.

Section 4.1: Supply voltage (VCC) and Section 6.4: Write Status Register
(WRSR) updated.

Note added to Section 6.6: Write to Memory Array (WRITE).

Section 7.2: Initial delivery state specified.

Note modified in Table 13: Capacitance. I

at 10 MHz added to Ta bl e 1 4 :

CC

DC characteristics (M95640, device grade 3).

parameter added to DC characteristics tables 14, 15, 16 and 19.

V

RES

Note added to t

in AC characteristics tables 18, 19, 20 and 21.

CLQV

Note added to Table 20: AC characteristics (M95320-R) and Table 21: AC

characteristics (M95640-R).

Process letter modified in Table 25: Ordering information scheme.

32 Kbit densities removed from datasheet.
ECOPACK status of packages specified in Features and in Table 25:

Ordering information scheme.

and IOH added to Table 8: Absolute maximum ratings.

I

OL

Note 2 added below Figure 24: UFDFPN8 (MLP8) - 8-lead ultra thin fine
pitch dual flat no lead, package outline.

Small text changes.

Added part number M95640-DR.
Updated Features, Section 1: Description, Section 6.4: Write Status

Register (WRSR), Section 6.6: Write to Memory Array (WRITE), Ta bl e 8 :
Absolute maximum ratings, all tables in Section 9: DC and AC
parameters, Section 11: Part numbering.

Added Table 4: M95640-DR instruction set, Section 6.7: Read

Identification Page, Section 6.9: Read Lock Status, Section 6.10: Lock ID,
Figure 16: Read Lock Status sequence, Figure 17: Lock ID sequence,
Table 27: Available M95640-DR products (package, voltage range,
temperature grade).

Replaced Ta bl e 2 4 .

46/48 Doc ID 16877 Rev 15

M95640, M95640-W, M95640-R, M95640-DR Revision history

Table 26. Document revision history (continued)

Date Revision Changes

Updated:

- UFDFPN8 package under Features

- Icc @10M Hz in Ta bl e 1 5

(1)

- note

02-Feb-2011 14

- note

- layout of Tab l e 8
Added references to M95640-DR in titles of tables 17 and 21.
Deleted Ta b le 2 6 Available M95640x products (package, voltage range,

temperature grade) and Ta bl e 2 7 Available M95640-DR products
(package, voltage range, temperature grade).

07-Apr-2011 15 Updated MLP8 package data.

under Ta bl e 1 9

(1)

under Ta bl e 2 1

Doc ID 16877 Rev 15 47/48

M95640, M95640-W, M95640-R, M95640-DR

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48/48 Doc ID 16877 Rev 15