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Automotive 512-Kbit serial SPI bus EEPROMs
UFDFPN8 (MC)
2 x 3 mm
TSSOP8 (DW)
169 mil width
SO8 (MN)
150 mil width
Features
■ Compatible with the Serial Peripheral Interface
(SPI) bus
■ Memory array
– 512 Kbits (64 Kbytes) of EEPROM
– Page size: 128 bytes
– Write protection by block: 1/4, 1/2 or whole
memory
– Additional Write lockable Page
(Identification page)
■ Extended temperature and voltage ranges
– Up to 125 °C: 1.8 V to 5.5 V
– Up to 145 °C: 2.5 V to 5.5 V
■ High speed clock frequency
–20MHz for V
–10MHz for V
–5MHz for V
■ Schmitt trigger inputs for noise filtering
■ Short Write cycle time
– Byte Write within 4 ms
– Page Write within 4 ms
■ Write cycle endurance
– 4 million Write cycles at 25 °C
– 1.2 million Write cycles at 85 °C
– 600 k Write cycles at 125 °C
– 400 k Write cycles at 145 °C
■ Data retention
– 40 years at 55 °C
– 100 years at 25 °C
■ ESD Protection (Human Body Model)
– 4000 V
■ Packages
– RoHS-compliant and halogen-free
(ECOPACK2
CC ≥
CC ≥
CC ≥
®
)
4.5 V
2.5 V
1.8 V
M95512-A125
M95512-A145
with high-speed clock
Target specification
February 2012 Doc ID 022682 Rev 1 1/39
This is preliminary information on a new product foreseen to be developed. Details are subject to change without notice.
www.st.com
1
Page 2
Contents M95512-A125 M95512-A145
Contents
1 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
2 Signal description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
2.1 Serial Data output (Q) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
2.2 Serial Data input (D) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
2.3 Serial Clock (C) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
2.4 Chip Select (S
2.5 Hold (HOLD
2.6 Write Protect (W
2.7 V
2.8 V
ground . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
SS
supply voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
CC
) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
3 Operating features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
3.1 Active power and Standby power modes . . . . . . . . . . . . . . . . . . . . . . . . . . 9
3.2 SPI modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
3.3 Hold mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
3.4 Protocol control and data protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
3.4.1 Protocol control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
3.4.2 Status Register and data protection . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
3.5 Identification page . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
4 Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
4.1 Write Enable (WREN) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
4.2 Write Disable (WRDI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
4.3 Read Status Register (RDSR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
4.4 Write Status Register (WRSR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
4.5 Read from Memory Array (READ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
4.6 Write to Memory Array (WRITE) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
4.7 Read Identification Page (RDID) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
4.8 Write Identification Page (WRID) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
4.9 Read Lock Status (RDLS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
4.10 Lock Identification Page (LID) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
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M95512-A125 M95512-A145 Contents
5 Application design recommendations . . . . . . . . . . . . . . . . . . . . . . . . . 24
5.1 Supply voltage (VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
5.1.1 Operating supply voltage V
5.1.2 Power-up conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
5.1.3 Power-down . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
CC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
5.2 Implementing devices on SPI bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
5.3 Cycling with Error Correction Code (ECC) . . . . . . . . . . . . . . . . . . . . . . . . 26
6 Delivery state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
7 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
8 DC and AC parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
9 Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
10 Part numbering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
11 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
Doc ID 022682 Rev 1 3/39
Page 4
List of tables M95512-A125 M95512-A145
List of tables
Table 1. Signal names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Table 2. Status Register format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Table 3. Write-protected block size . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Table 4. Protection modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Table 5. Device identification bytes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Table 6. Instruction set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Table 7. Significant bits within the two address bytes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Table 8. Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Table 9. Cycling performance by groups of 4 bytes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Table 10. Operating conditions (voltage range W, temperature range 4) . . . . . . . . . . . . . . . . . . . . . . 28
Table 11. Operating conditions (voltage range R, temperature range 3) . . . . . . . . . . . . . . . . . . . . . . 28
Table 12. Operating conditions (voltage range R, temperature range 3)
for high speed communications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Table 13. DC characteristics (voltage range W, temperature range 4). . . . . . . . . . . . . . . . . . . . . . . . 29
Table 14. DC characteristics (voltage range R, temperature range 3) . . . . . . . . . . . . . . . . . . . . . . . . 30
Table 15. AC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Table 16. SO8N – 8-lead plastic small outline, 150 mils body width, package mechanical data . . . . 34
Table 17. TSSOP8 – 8-lead thin shrink small outline, package mechanical data. . . . . . . . . . . . . . . . 35
Table 18. UFDFPN8 (MLP8) 8-lead ultra thin fine pitch dual flat package no lead
2 x 3 mm, data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
Table 19. Ordering information scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
Table 20. Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
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M95512-A125 M95512-A145 List of figures
List of figures
Figure 1. Logic diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Figure 2. 8-pin package connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Figure 3. SPI modes supported . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Figure 4. Hold mode activation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Figure 5. Write Enable (WREN) sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Figure 6. Write Disable (WRDI) sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Figure 7. Read Status Register (RDSR) sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Figure 8. Write Status Register (WRSR) sequence. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Figure 9. Read from Memory Array (READ) sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Figure 10. Byte Write (WRITE) sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Figure 11. Page Write (WRITE) sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Figure 12. Read Identification Page sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Figure 13. Write Identification Page sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Figure 14. Read Lock Status sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Figure 15. Lock ID sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Figure 16. Bus master and memory devices on the SPI bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Figure 17. AC measurement I/O waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Figure 18. Serial input timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Figure 19. Hold timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Figure 20. Serial output timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Figure 21. SO8N – 8-lead plastic small outline, 150 mils body width, package outline . . . . . . . . . . . . 34
Figure 22. TSSOP8 – 8-lead thin shrink small outline, package outline . . . . . . . . . . . . . . . . . . . . . . . 35
Figure 23. UFDFPN8 (MLP8) - 8-lead ultra thin fine pitch dual flat no lead, package
outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
Doc ID 022682 Rev 1 5/39
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Description M95512-A125 M95512-A145
-36
(/,$
3
7
#ONTROLLOGIC
(IGHVOLTAGE
GENERATOR
)/SHIFTREGISTER
!DDRESSREGISTER
ANDCOUNTER
$ATA
REGISTER
PAGE
8DECODER
9DECODER
#
$
1
3IZEOFTHE
2EADONLY
%%02/AREA
3TATUS
REGISTER
)DENTIFICATIONPAGE
1 Description
The M95512-A125 and M95512-A145 are 512-Kbit serial EEPROM Automotive grade
devices operating up to 145°C. They are compliant with the very high level of reliability
defined by the Automotive standard AEC-Q100 grade 0.
The devices are accessed by a simple serial SPI compatible interface running up to 20 MHz.
The memory array is based on advanced true EEPROM technology (Electrically Erasable
PROgrammable Memory). The M95512-A125 and M95512-A145 are byte-alterable
memories (65536 × 8 bits) organized as 512 pages of 128 bytes in which the data integrity is
significantly improved with an embedded Error Correction Code logic.
The M95512-A125 and M95512-A145 offer an additional Identification Page (128 bytes) in
which the ST device identification can be read. This page can also be used to store sensitive
application parameters which can be later permanently locked in read-only mode.
Figure 1. Logic diagram
6/39 Doc ID 022682 Rev 1
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M95512-A125 M95512-A145 Description
DV
SS
C
HOLDQ
SV
CC
W
AI01790D
M95xxx
1
2
3
4
8
7
6
5
Figure 2. 8-pin package connections
1. See Package mechanical data section for package dimensions and how to identify pin-1.
Table 1. Signal names
Signal name Description
C Serial Clock
D Serial data input
Q Serial data output
S Chip Select
W
Write Protect
HOLD
V
CC
V
SS
Hold
Supply voltage
Ground
Doc ID 022682 Rev 1 7/39
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Signal description M95512-A125 M95512-A145
2 Signal description
All input signals must be held high or low (according to voltages of VIH or VIL, as specified in
Ta bl e 1 3 and Ta bl e 1 4 )). These signals are described below.
2.1 Serial Data output (Q)
This output signal is used to transfer data serially out of the device during a Read operation.
Data is shifted out on the falling edge of Serial Clock (C), most significant bit (MSB) first. In
all other cases, the Serial Data output is in high impedance.
2.2 Serial Data input (D)
This input signal is used to transfer data serially into the device. D input receives
instructions, addresses, and the data to be written. Values are latched on the rising edge of
Serial Clock (C), most significant bit (MSB) first.
2.3 Serial Clock (C)
This input signal allows to synchronize the timing of the serial interface. Instructions,
addresses, or data present at Serial Data Input (D) are latched on the rising edge of Serial
Clock (C). Data on Serial Data Output (Q) changes after the falling edge of Serial Clock (C).
2.4 Chip Select (S)
Driving Chip Select (S) low selects the device in order to start communication. Driving Chip
Select (S
state.
) high deselects the device and Serial Data output (Q) enters the high impedance
2.5 Hold (HOLD)
The Hold (HOLD) signal is used to pause any serial communications with the device without
deselecting the device.
2.6 Write Protect (W)
This pin is used to write-protect the Status Register.
2.7 VSS ground
VSS is the reference for all signals, including the VCC supply voltage.
2.8 VCC supply voltage
VCC is the supply voltage pin.
Refer to Section 3.1: Active power and Standby power modes and to Section 5.1: Supply
voltage (VCC).
8/39 Doc ID 022682 Rev 1
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M95512-A125 M95512-A145 Operating features
AI01438B
C
MSB
CPHA
D
0
1
CPOL
0
1
Q
C
MSB
3 Operating features
3.1 Active power and Standby power modes
When Chip Select (S) is low, the device is selected and in the Active power mode.
When Chip Select (S
progress, the device then goes in to the Standby power mode, and the device consumption
drops to I
, as specified in Ta bl e 1 3 and Ta bl e 1 4 .
CC1
3.2 SPI modes
The device can be driven by a microcontroller with its SPI peripheral running in either of the
two following modes:
● CPOL=0, CPHA=0
● CPOL=1, CPHA=1
For these two modes, input data is latched in on the rising edge of Serial Clock (C), and
output data is available from the falling edge of Serial Clock (C).
The difference between the two modes, as shown in Figure 3, is the clock polarity when the
bus master is in Stand-by mode and not transferring data:
● C remains at 0 for (CPOL=0, CPHA=0)
● C remains at 1 for (CPOL=1, CPHA=1)
Figure 3. SPI modes supported
) is high, the device is deselected. If a Write cycle is not currently in
Doc ID 022682 Rev 1 9/39
Page 10
Operating features M95512-A125 M95512-A145
(/,$
#
(OLD
CONDITION
#
N
(OLD
CONDITION
-36
3.3 Hold mode
The Hold (HOLD) signal is used to pause any serial communications with the device without
resetting the clocking sequence.
The Hold mode starts when the Hold (HOLD
) signal is driven low and the Serial Clock (C) is
low (as shown in Figure 4). During the Hold mode, the Serial Data output (Q) is high
impedance, and the signals present on Serial Data input (D) and Serial Clock (C) are not
decoded. The Hold mode ends when the Hold (HOLD
Clock (C) is or becomes low.
Figure 4. Hold mode activation
Deselecting the device while it is in Hold mode resets the paused communication.
3.4 Protocol control and data protection
) signal is driven high and the Serial
ONDITIO
3.4.1 Protocol control
The Chip Select (S) input offers a built-in safety feature, as the S input is edge-sensitive as
well as level-sensitive: after power-up, the device is not selected until a falling edge has first
been detected on Chip Select (S
prior to going low, in order to start the first operation.
For Write commands (WRITE, WRSR, WRID, LID) to be accepted and executed:
● the Write Enable Latch (WEL) bit must be set by a Write Enable (WREN) instruction
● a falling edge and a low state on Chip Select (S) during the whole command must be
decoded
● instruction, address and input data must be sent as multiple of eight bits
● the command must include at least one data byte
● Chip Select (S) must be driven high exactly after a data byte boundary
Write command can be discarded at any time by a rising edge on Chip Select (S
a byte boundary.
To execute Read commands (READ, RDSR, RDID, RDLS), the device must decode:
● a falling edge and a low level on Chip Select (S) during the whole command
● instruction and address as multiples of eight bits (bytes)
From this step, data bits are shifted out until the rising edge on Chip Select (S
). This ensures that Chip Select (S) must have been high
) outside of
).
10/39 Doc ID 022682 Rev 1
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M95512-A125 M95512-A145 Operating features
3.4.2 Status Register and data protection
The Status Register format is shown in Ta b le 2 and the status and control bits of the Status
Register are as follows:
Table 2. Status Register format
b7 b6 b5 b4 b3 b2 b1 b0
SRWD 0 0 0 BP1 BP0 WEL WIP
Status Register Write Protect
Block Protect bits
Write Enable Latch bit
Write In Progress bit
Note: Bits b6, b5, b4 are always read as 0.
WIP bit
The WIP bit (Write In Progress) is a read-only flag that indicates the Ready/Busy state of the
device. When a Write command (WRITE, WRSR, WRID, LID) has been decoded and a
Write cycle (t
the device is ready to decode a new command.
) is in progress, the device is busy and the WIP bit is set to 1. When WIP=0,
W
During a Write cycle, reading continuously the WIP bit allows to detect when the device
becomes ready (WIP=0) to decode a new command.
WEL bit
The WEL bit (Write Enable Latch) bit is a flag that indicates the status of the internal Write
Enable Latch. When WEL is set to 1, the Write instructions (WRITE, WRSR, WRID, LID) are
executed; when WEL is set to 0, any decoded Write instruction is not executed.
The WEL bit is set to 1 with the WREN instruction. The WEL bit is reset to 0 after the
following events:
● Write Disable (WRDI) instruction completion
● Write instructions (WRITE, WRSR, WRID, LID) completion including the write cycle
time t
W
Power-up
●
BP1, BP0 bits
The Block Protect bits (BP1, BP0) are non-volatile. BP1,BP0 bits define the size of the
memory block to be protected against write instructions, as defined in Ta bl e 2 . These bits
are written with the Write Status Register (WRSR) instruction, provided that the Status
Register is not protected (refer to SRWD bit and W input signal).
Doc ID 022682 Rev 1 11/39
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Operating features M95512-A125 M95512-A145
Table 3. Write-protected block size
Status Register bits
Protected block Protected array addresses
BP1 BP0
0 0 None None
0 1 Upper quarter C000h - FFFFh
1 0 Upper half 8000h - FFFFh
1 1 Whole memory 0000h - FFFFh plus Identification page
SRWD bit and W input signal
The Status Register Write Disable (SRWD) bit is operated in conjunction with the Write
Protect pin (W
Register, regardless of whether the pin Write Protect (W
When the SRWD bit is written to 1, two cases have to be considered, depending on the
state of the W
● Case 1: if pin W is driven high, it is possible to write the Status Register.
● Case 2: if pin W is driven low, it is not possible to write the Status Register (WRSR is
discarded) and therefore SRWD,BP1,BP0 bits cannot be changed (the size of the
protected memory block defined by BP1,BP0 bits is frozen).
) signal. When the SRWD bit is written to 0, it is possible to write the Status
) is driven high or low.
input pin:
Case 2 can be entered in either sequence:
● Writing SRWD bit to 1 after driving pin W low, or
● Driving pin W low after writing SRWD bit to 1.
The only way to exit Case 2 is to pull pin W
Note: if pin W
is permanently tied high, the Status Register cannot be write-protected.
high.
The protection features of the device are summarized in Tab l e 4 .
Table 4. Protection modes
SRWD bit W signal Status
0X
11
1 0 Status Register is write-protected.
Status Register is writable.
12/39 Doc ID 022682 Rev 1
Page 13
M95512-A125 M95512-A145 Operating features
3.5 Identification page
The M95512-A125 and M95512-A145 offer an Identification Page (128 bytes) in addition to
the 512 Kbit memory. This page can be used for several purposes:
● Device identification: the three first bytes of the Identification page are programmed by
STMicroelectronics with the Device identification code, as shown in Tab le 5 .
● Storage of specific parameters: each byte in the Identification page can be written if the
Identification page is not permanently locked in Read-only mode.
● Write protection: once the application specific parameters are written in the
Identification page, the whole Identification page can be permanently locked in read
only mode.
Table 5. Device identification bytes
Address in
Identification page
00h
01h
02h Memory Density code
ST Manufacturer code 20h
Content Value
SPI Family code 00h
10h (512 Kbit)
Read, write and lock Identification Page are detailed in Section 4: Instructions.
Doc ID 022682 Rev 1 13/39
Page 14
Instructions M95512-A125 M95512-A145
4 Instructions
Each command is composed of bytes (MSBit transmitted first), initiated with the instruction
byte, as summarized in Tab l e 6 .
If an invalid instruction is sent (one not contained in Ta bl e 6 ), the device automatically enters
a Wait state until deselected.
Table 6. Instruction set
Instruction Description
WREN Write Enable 0000 0110
WRDI Write Disable 0000 0100
RDSR Read Status Register 0000 0101
WRSR Write Status Register 0000 0001
READ Read from Memory Array 0000 0011
WRITE Write to Memory Array 0000 0010
(1)
RDID
(1)
WRID
(1)
RDLS
(1)
LID
1. Instruction available for the M95512-D device only (see Section 10: Part numbering).
Read Identification Page 1000 0011
Write Identification Page 1000 0010
Reads the Identification Page lock status. 1000 0011
Locks the Identification page in read-only mode. 1000 0010
For read and write commands to memory array and Identification Page, the address is
defined by two bytes as explained in Tab le 7 .
Table 7. Significant bits within the two address bytes
MSB Address byte LSB Address byte
Instructions
b15 b14 b13 b12 b11 b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0
Instruction
format
(1)
READ or
WRITE
RDID or
WRID
RDLS or
LID
1. A: Significant address bit.
A15 A14 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0
000000000A6A5A4A3A2A1A0
0000010000000000
14/39 Doc ID 022682 Rev 1
Page 15
M95512-A125 M95512-A145 Instructions
C
D
AI02281E
S
Q
21 34567
High Impedance
0
Instruction
C
D
AI03750D
S
Q
21 34567
High Impedance
0
Instruction
4.1 Write Enable (WREN)
The WREN instruction must be decoded by the device before a write instruction (WRITE,
WRSR, WRID or LID).
As shown in Figure 5, to send this instruction to the device, Chip Select (S
bits of the instruction byte are shifted in (MSB first) on Serial Data Input (D) after what the
Chip Select (S
) input is driven high and the WEL bit is set (Status Register bit).
Figure 5. Write Enable (WREN) sequence
4.2 Write Disable (WRDI)
One way of resetting the WEL bit (in the Status Register) is to send a Write Disable
instruction to the device.
) is driven low, the
As shown in Figure 6, to send this instruction to the device, Chip Select (S
) is driven low,
and the bits of the instruction byte are shifted in (MSB first), on Serial Data Input (D), after
what the Chip Select (S
) input is driven high and the WEL bit is reset (Status Register bit).
If a Write cycle is currently in progress, the WRDI instruction is decoded and executed and
the WEL bit is reset to 0 with no effect on the ongoing Write cycle.
Figure 6. Write Disable (WRDI) sequence
Doc ID 022682 Rev 1 15/39
Page 16
Instructions M95512-A125 M95512-A145
C
D
S
21 3456789101112131415
Instruction
0
AI02031E
Q
7 6543210
Status Register Out
High Impedance
MSB
7 6543210
Status Register Out
MSB
7
4.3 Read Status Register (RDSR)
The Read Status Register (RDSR) instruction is used to read the content of the Status
Register.
As shown in Figure 7, to send this instruction to the device, Chip Select (S
) is first driven low.
The bits of the instruction byte are shifted in (MSB first) on Serial Data Input (D), the Status
Register content is then shifted out (MSB first) on Serial Data Output (Q).
If Chip Select (S
) continues to be driven low, the Status Register content is continuously
shifted out.
The Status Register can always be read, even if a Write cycle (t
) is in progress. The Status
W
Register functionality is detailed in Section 3.4.2: Status Register and data protection.
Figure 7. Read Status Register (RDSR) sequence
4.4 Write Status Register (WRSR)
The Write Status Register (WRSR) instruction allows new values to be written to the Status
Register. Before it can be accepted, a Write Enable (WREN) instruction must previously
have been executed.
The Write Status Register (WRSR) instruction is entered (MSB first) by driving Chip Select
(S
) low, sending the instruction code followed by the data byte on Serial Data input (D), and
driving the Chip Select (S
The contents of the SRWD and BP1, BP0 bits are updated after the completion of the
WRSR instruction, including the Write cycle (t
The Write Status Register (WRSR) instruction has no effect on the b6, b5, b4, b1 and b0
bits in the Status Register (see Table 2: Status Register format).
The Status Register functionality is detailed in Section 3.4.2: Status Register and data
protection.
The instruction is not accepted, and is not executed, if a Write cycle is currently in progress.
16/39 Doc ID 022682 Rev 1
) signal high.
).
W
Page 17
M95512-A125 M95512-A145 Instructions
C
D
AI02282D
S
Q
21 3456789101112131415
High Impedance
Instruction Status
Register In
0
765432 0
1
MSB
Figure 8. Write Status Register (WRSR) sequence
4.5 Read from Memory Array (READ)
The READ instruction is used to read the content of the memory.
As shown in Figure 9, to send this instruction to the device, Chip Select (S
) is first driven low.
The bits of the instruction byte and address bytes are shifted in (MSB first) on Serial Data
Input (D) and the addressed data byte is then shifted out (MSB first) on Serial Data Output
(Q). The first addressed byte can be any byte within any page.
If Chip Select (S
) continues to be driven low, the internal address register is automatically
incremented, and the next byte of data is shifted out. The whole memory can therefore be
read with a single READ instruction.
When the highest address is reached, the address counter rolls over to zero, allowing the
Read cycle to be continued indefinitely.
The Read cycle is terminated by driving Chip Select (S
) high at any time when the data bits
are shifted out on Serial Data Output (Q).
The instruction is not accepted, and is not executed, if a Write cycle is currently in progress.
Doc ID 022682 Rev 1 17/39
Page 18
Instructions M95512-A125 M95512-A145
C
D
AI01793D
S
Q
15
21 345678910 2021222324252627
1413 3210
28 29 30
76543 1 7
0
High Impedance
Data Out 1
Instruction 16-Bit Address
0
MSB
MSB
2
31
Data Out 2
C
D
AI01795D
S
Q
15
21 345678910 2021222324252627
1413 3210
28 29 30
High Impedance
Instruction 16-Bit Address
0
765432 0
1
Data Byte
31
Figure 9. Read from Memory Array (READ) sequence
1. Depending on the memory size, as shown in Table 7, the most significant address bits are Don’t Care.
4.6 Write to Memory Array (WRITE)
The WRITE instruction is used to write new data in the memory.
As shown in Figure 10, to send this instruction to the device, Chip Select (S
) is first driven
low. The bits of the instruction byte, address bytes, and at least one data byte are then
shifted in (MSB first), on Serial Data Input (D). The instruction is terminated by driving Chip
Select (S
) high at a data byte boundary. Figure 10 shows a single byte write.
Figure 10. Byte Write (WRITE) sequence
1. Depending on the memory size, as shown in Table 8, the most significant address bits are Don’t Care.
A Page write is used to write several bytes inside a page, with a single internal Write cycle.
For a Page write, Chip Select (S
data bytes are shifted in. Each time a new data byte is shifted in, the least significant bits of
the internal address counter are incremented. If the address counter exceeds the page
boundary (the page size is 128 bytes), the internal address pointer rolls over to the
) has to remain low, as shown in Figure 11, so that the next
18/39 Doc ID 022682 Rev 1
Page 19
M95512-A125 M95512-A145 Instructions
C
D
AI01796D
S
3433 35 36 37 38 39 40 41 42 44 45 46 4732
C
D
S
15
21 345678910 2021222324252627
1413 3210
28 29 30
Instruction 16-Bit Address
0
765432 0
1
Data Byte 1
31
43
765432 0
1
Data Byte 2
765432 0
1
Data Byte 3
65432 0
1
Data Byte N
beginning of the same page where next data bytes will be written. If more than 128 bytes are
received, only the last 128 bytes are written.
For both Byte write and Page write, the self-timed Write cycle starts from the rising edge of
Chip Select (S
), and continues for a period tW (as specified in Ta bl e 1 5).
The instruction is discarded, and is not executed, under the following conditions:
● if a Write cycle is already in progress
● if the addressed page is in the region protected by the Block Protect (BP1 and BP0)
bits
● if one of the conditions defined in Section 3.4.1 is not satisfied
Note: The self-timed Write cycle t
events: [Erase addressed byte(s)], followed by [Program addressed byte(s)]. An erased bit is
read as “0” and a programmed bit is read as “1”.
Figure 11. Page Write (WRITE) sequence
is internally executed as a sequence of two consecutive
W
1. Depending on the memory size, as shown in Table 7, the most significant address bits are Don’t Care.
Doc ID 022682 Rev 1 19/39
Page 20
Instructions M95512-A125 M95512-A145
#
$
!I
3
1
(IGHIMPEDANCE
$ATA/UT
)NSTRUCTION BITADDRESS
-3"
-3"
$ATA/UT
4.7 Read Identification Page (RDID)
The Read Identification Page instruction is used to read the Identification Page (additional
page of 128 bytes which can be written and later permanently locked in Read-only mode).
The Chip Select (S
) signal is first driven low, the bits of the instruction byte and address
bytes are then shifted in (MSB first) on Serial Data input (D). Address bit A10 must be 0,
address bits [A15:A11] and [A9:A7] are Don't Care (it might be easier to define these bits as
0, as shown in Ta bl e 7 ). The data byte pointed to by [A6:A0] is shifted out (MSB first) on
Serial Data output (Q).
The first byte addressed can be any byte within the identification page.
If Chip Select (S
) continues to be driven low, the internal address register is automatically
incremented and the byte of data at the new address is shifted out.
Note that there is no roll over feature in the Identification Page. The address of bytes to read
must not exceed the page boundary.
The read cycle is terminated by driving Chip Select (S
Select (S
) signal can occur at any time when the data bits are shifted out.
The instruction is not accepted, and is not executed, if a Write cycle is currently in progress.
Figure 12. Read Identification Page sequence
) high. The rising edge of the Chip
The first three bytes of the Identification page offer information about the device itself.
Please refer to Section 3.5: Identification page for more information.
20/39 Doc ID 022682 Rev 1
Page 21
M95512-A125 M95512-A145 Instructions
4.8 Write Identification Page (WRID)
The Write Identification Page instruction is used to write the Identification Page (additional
page of 128 bytes which can also be permanently locked in Read-only mode).
The Chip Select signal (S
) is first driven low, and then the bits of the instruction byte,
address bytes, and at least one data byte are shifted in (MSB first) on Serial Data input (D).
Address bit A10 must be 0, address bits [A15:A11] and [A9:A7] are Don't Care (it might be
easier to define these bits as 0, as shown in Tab le 7 ). The [A6:A0] address bits define the
byte address inside the identification page.
The self-timed Write cycle starts from the rising edge of Chip Select (S
period t
(as specified in Ta bl e 1 5).
W
), and continues for a
Figure 13. Write Identification Page sequence
3
#
)NSTRUCTION BITADDRESS
$
(IGHIMPEDANCE
1
$ATABYTE
!I
Note: The first three bytes of the Identification page offer the Device Identification code (Please
refer to Section 3.5: Identification page for more information). Using the WRID command on
these first three bytes overwrites the Device Identification code.
The instruction is discarded, and is not executed, under the following conditions:
● If a Write cycle is already in progress
● If the Block Protect bits (BP1,BP0) = (1,1)
● If one of the conditions defined in Section 3.4.1: Protocol control is not satisfied.
4.9 Read Lock Status (RDLS)
The Read Lock Status instruction is used to read the lock status.
To send this instruction to the device, Chip Select (S
the instruction byte and address bytes are then shifted in (MSB first) on Serial Data input
(D). Address bit A10 must be 1; all other address bits are Don't Care (it might be easier to
define these bits as 0, as shown in Tab l e 7 ). The Lock bit is the LSB (Least Significant Bit) of
the byte read on Serial Data output (Q). It is at ‘1’ when the lock is active and at ‘0’ when the
lock is not active. If Chip Select (S
) continues to be driven low, the same data byte is shifted
out.
The read cycle is terminated by driving Chip Select (S
shown in Figure 14.
) first has to be driven low. The bits of
) high. The instruction sequence is
Doc ID 022682 Rev 1 21/39
Page 22
Instructions M95512-A125 M95512-A145
#
$
!I
3
1
(IGHIMPEDANCE
$ATA/UT
)NSTRUCTION BITADDRESS
-3"
-3"
$ATA/UT
The Read Lock Status instruction is not accepted and not executed if a Write cycle is
currently in progress.
Figure 14. Read Lock Status sequence
4.10 Lock Identification Page (LID)
The Lock Identification Page (LID) command is used to permanently lock the Identification
Page in Read-only mode.
The LID instruction is issued by driving Chip Select (S) low, sending (MSB first) the
instruction code, the address and a data byte on Serial Data input (D), and driving Chip
Select (S) high. In the address sent, A10 must be equal to 1. All other address bits are Don't
Care (it might be easier to define these bits as 0, as shown in Ta bl e 7 ). The data byte sent
must be equal to the binary value xxxx xx1x, where x = Don't Care. The LID instruction is
terminated by driving Chip Select (S) high at a data byte boundary, otherwise, the instruction
is not executed.
Figure 15. Lock ID sequence
3
#
)NSTRUCTION BITADDRESS
$
(IGHIMPEDANCE
1
$ATABYTE
!I
Driving Chip Select (S
22/39 Doc ID 022682 Rev 1
cycle which duration is t
Figure 15.
) high at a byte boundary of the input data triggers the self-timed Write
(specified in Ta bl e 1 5). The instruction sequence is shown in
W
Page 23
M95512-A125 M95512-A145 Instructions
The instruction is discarded, and is not executed, under the following conditions:
● If a Write cycle is already in progress
● If the Block Protect bits (BP1,BP0) = (1,1)
● If one of the conditions defined in Section 3.4.1: Protocol control is not satisfied.
Doc ID 022682 Rev 1 23/39
Page 24
Application design recommendations M95512-A125 M95512-A145
5 Application design recommendations
5.1 Supply voltage (VCC)
5.1.1 Operating supply voltage V
Prior to selecting the memory and issuing instructions to it, a valid and stable VCC voltage
within the specified [V
CC(min)
, V
CC(max)
This voltage must remain stable and valid until the end of the transmission of the instruction
and, for a Write instruction, until the completion of the internal Write cycle (t
secure a stable DC supply voltage, it is recommended to decouple the V
suitable capacitor (usually of the order of 10 nF to 100 nF) close to the V
pins.
5.1.2 Power-up conditions
When the power supply is turned on, VCC continuously rises from VSS to VCC. During this
time, the Chip Select (S
therefore recommended to connect the S
Figure 16).
The V
voltage has to rise continuously from 0 V up to the minimum VCC operating voltage
CC
defined in Ta bl e 1 3 and Ta bl e 1 4 .
In order to prevent inadvertent write operations during power-up, a power-on-reset (POR)
circuit is included.
At power-up, the device does not respond to any instruction until V
threshold voltage (this threshold is defined in the DC characteristics tables 13 and 14 as
VRES).
) line is not allowed to float but should follow the VCC voltage. It is
CC
] range must be applied (see Tab l e 1 0 and Ta bl e 1 1).
). In order to
W
line with a
CC
CC/VSS
package
line to VCC via a suitable pull-up resistor (see
reaches the internal
CC
When V
● in the Standby power mode
● deselected
● Status register values:
passes over the POR threshold, the device is reset and in the following state:
CC
– Write Enable Latch (WEL) bit is reset to 0.
– Write In Progress (WIP) bit is reset to 0.
– SRWD, BP1 and BP0 bits remain unchanged (non-volatile bits).
● not in the Hold condition
As soon as the V
voltage has reached a stable value within [VCC(min), VCC(max)] range,
CC
the device is ready for operation.
24/39 Doc ID 022682 Rev 1
Page 25
M95512-A125 M95512-A145 Application design recommendations
30)BUSMASTER
3$/
3$)
3#+
#1$
#1$#1$
#3 #3 #3
30)INTERFACEWITH
#0/,#0(!
OR
30)MEMORY
DEVICE
3
7
(/,$
222
6
##
6
##
6
##
6
##
-36
6
33
30)MEMORY
DEVICE
3
7
(/,$
30)MEMORY
DEVICE
3
7
(/,$
5.1.3 Power-down
During power-down (continuous decrease in the VCC supply voltage below the minimum
V
operating voltage defined in Ta bl e 1 3 and Ta bl e 1 4 ), the device must be:
CC
● deselected (Chip Select (S) should be allowed to follow the voltage applied on V
● in Standby power mode (there should not be any internal Write cycle in progress).
CC
),
5.2 Implementing devices on SPI bus
Figure 16 shows an example of three devices, connected to the SPI bus master. Only one
device is selected at a time, so that only the selected device drives the Serial Data output
(Q) line. All the other devices outputs are then in high impedance.
Figure 16. Bus master and memory devices on the SPI bus
1. The Write Protect (W) and Hold (HOLD) signals must be driven high or low as appropriate.
A pull-up resistor connected on each /S input (represented in Figure 16) ensures that each
device is not selected if the bus master leaves the /S
Doc ID 022682 Rev 1 25/39
line in the high impedance state.
Page 26
Application design recommendations M95512-A125 M95512-A145
5.3 Cycling with Error Correction Code (ECC)
The Error Correction Code (ECC) is an internal logic function which is transparent for the
SPI communication protocol.
The ECC logic is implemented on each group of four EEPROM bytes
single bit out of the four bytes happens to be erroneous during a Read operation, the ECC
detects this bit and replaces it with the correct value. The read reliability is therefore much
improved.
Even if the ECC function is performed on groups of four bytes, a single byte can be
written/cycled independently. In this case, the ECC function also writes/cycles the three
other bytes located in the same group
(a)
. As a consequence, the maximum cycling budget is
defined at group level and the cycling can be distributed over the 4 bytes of the group: the
sum of the cycles seen by byte0, byte1, byte2 and byte3 of the same group must remain
below the maximum value defined in Table 9: Cycling performance by groups of 4 bytes.
Example1: maximum cycling limit reached with 1 million cycles per byte
Each byte of a group can be equally cycled 1 million times (at 25 °C) so that the group
cycling budget is 4 million cycles.
Example2: maximum cycling limit reached with unequal byte cycling
(a)
. Inside a group, if a
Inside a group, byte0 can be cycled 2 millions times, byte1 can be cycled 1 million times,
byte2 and byte3 can be cycled 500,000 times, so that the group cycling budget is 4 millions
cycles.
a. A group of four bytes is located at addresses [4*N, 4*N+1, 4*N+2, 4*N+3], where N is an integer.
26/39 Doc ID 022682 Rev 1
Page 27
M95512-A125 M95512-A145 Delivery state
6 Delivery state
The device is delivered with:
● the memory array set to all 1s (each byte = FFh),
● Status register: bit SRWD =0, BP1 =0 and BP0 =0,
● Identification page:
– the first three bytes define the device identification (value defined in Ta bl e 5 )
– the 125 following bytes set to FFh.
7 Absolute maximum ratings
Stressing the device outside the ratings listed in Ta bl e 8 may cause permanent damage to
the device. These are stress ratings only, and operation of the device at these, or any other
conditions outside those indicated in the operating sections of this specification, is not
implied. Exposure to absolute maximum rating conditions for extended periods may affect
device reliability.
Table 8. Absolute maximum ratings
Symbol Parameter Min. Max. Unit
T
STG
T
AMR
T
LEAD
V
O
V
I
OL
I
OH
V
CC
V
ESD
1. Compliant with JEDEC Std J-STD-020 (for small body, Sn-Pb or Pb assembly), the ST ECOPACK®
7191395 specification, and the European directive on Restrictions on Hazardous Substances (RoHS)
2002/95/EU
2. Positive and negative pulses applied on pin pairs, in accordance with AEC-Q100-002 (compliant with
JEDEC Std JESD22-A114, C1=100 pF, R1=1500 Ω, R2=500 Ω)
Storage temperature –65 150 °C
Ambient operating temperature –40 150 °C
Lead temperature during soldering See note
Voltage on Q pin –0.50 VCC+0.6 V
Input voltage –0.50 6.5 V
I
DC output current (Q = 0) 5 mA
DC output current (Q = 1) 5 mA
Supply voltage –0.50 6.5 V
Electrostatic pulse (Human Body Model)
(2)
(1)
4000 V
°C
Doc ID 022682 Rev 1 27/39
Page 28
DC and AC parameters M95512-A125 M95512-A145
8 DC and AC parameters
This section summarizes the operating conditions and the DC/AC characteristics of the
device.
Table 9. Cycling performance by groups of 4 bytes
Symbol Parameter Test condition Min. Max. Unit
Ncycle Write cycle endurance
1. The Write cycle endurance is defined for groups of four data bytes located at addresses [4*N, 4*N+1, 4*N+2, 4*N+3] where
N is an integer, or for the status register byte (refer also to Section 5.3: Cycling with Error Correction Code (ECC)). The
Write cycle endurance is defined by characterization and qualification.
2. A Write cycle is executed when either a Page Write, a Byte Write, a WRSR, a WRID or an LID instruction is decoded. When
using the Byte Write, the Page Write or the WRID, refer also to Section 5.3: Error Correction Code (ECC).
3. For temperature range 4 only.
TA ≤ 25 °C, 1.8 V < VCC < 5.5 V 4,000,000
TA = 85 °C, 1.8 V < VCC < 5.5 V 1,200,000
(1)
TA = 125 °C, 1.8 V < V
(3)
TA = 145 °C
, 2.5 V < VCC < 5.5 V 400,000
< 5.5 V 600,000
CC
Write
cycle
(2)
Table 10. Operating conditions (voltage range W, temperature range 4)
Symbol Parameter Conditions Min. Max. Unit
V
T
Table 11. Operating conditions (voltage range R, temperature range 3)
Supply voltage 2.5 5.5 V
CC
Ambient operating temperature –40 145 °C
A
f
Operating clock frequency
C
5.5 V ≥ V
capacitive load on Q pin ≤ 100pF
CC
≥ 2.5 V,
10 MHz
Symbol Parameter Conditions Min. Max. Unit
V
T
Table 12. Operating conditions (voltage range R, temperature range 3)
Supply voltage 1.8 5.5 V
CC
Ambient operating temperature –40 125 °C
A
V
≥ 2.5 V, capacitive load on Q pin ≤ 100pF 10
f
Operating clock frequency
C
CC
≥ 1.8 V, capacitive load on Q pin ≤ 100pF 5
V
CC
for high speed communications
Symbol Parameter Conditions Min. Max. Unit
MHz
V
T
Supply voltage 4.5 5.5 V
CC
Ambient operating temperature –40 85 °C
A
f
Operating clock frequency V
C
≥ 4.5 V, capacitive load on Q pin ≤ 60 pF 20 MHz
CC
28/39 Doc ID 022682 Rev 1
Page 29
M95512-A125 M95512-A145 DC and AC parameters
Table 13. DC characteristics (voltage range W, temperature range 4)
Specific test conditions
Symbol Parameter
(2)
C
OUT
C
Output capacitance (Q) V
(2)
Input capacitance V
IN
Input leakage current V
I
LI
Output leakage current S = VCC, V
I
LO
V
C = 0.1VCC/0.9V
I
Supply current (Read)
CC
V
C = 0.1VCC/0.9V
I
CC0
(1)
Supply current (Write)
2.5 V < VCC < 5.5 V, during tW,
S = V
t° = 85 °C, V
VIN = VSS or V
t° = 85 °C, VCC = 5.5 V, S = V
VIN = VSS or V
t° = 125 °C, VCC = 2.5 V, S = V
I
CC1
Supply current
(Standby power mode)
VIN = VSS or V
t° = 125 °C, V
VIN = VSS or V
t° = 145 °C, V
VIN = VSS or V
t° = 145 °C, V
VIN = VSS or V
V
Input low voltage –0.45 0.3V
IL
V
Input high voltage 0.7VCCVCC+1
IH
V
V
V
RES
1. Average value during the Write cycle (tW)
2. Characterized only, not 100% tested
Output low voltage IOL = 2 mA 0.4
OL
Output high voltage IOH = -2 mA 0.8V
OH
Internal reset threshold
(2)
voltage
(in addition to conditions
specified in
= 0 V 8
OUT
= 0 V 6
IN
= VSS or V
IN
OUT
= 2.5 V, fC = 10 MHz,
CC
= 5.5 V, fC = 10 MHz,
CC
CC
Table 10 )
CC
= VSS or V
Q = open
CC,
Q = open
CC,
= 2.5 V, S = V
CC
CC
CC
CC
= 5.5 V, S = V
CC
CC
= 2.5 V, S = V
CC
CC
= 5.5 V, S = V
CC
CC
CC
CC
CC
CC
CC
CC
CC
Min. Max. Unit
pF
2
µA
3
2
4
mA
2
(2)
2
(2)
3
15
µA
20
25
40
CC
V
CC
0.5 1.3
Doc ID 022682 Rev 1 29/39
Page 30
DC and AC parameters M95512-A125 M95512-A145
Table 14. DC characteristics (voltage range R, temperature range 3)
Test conditions
Symbol Parameter
(3)
C
V
OUT
C
I
CC0
RES
I
V
V
Output capacitance (Q) V
(3)
Input capacitance V
IN
Input leakage current V
I
LI
Output leakage current S = VCC, V
I
LO
Supply current (Read)
I
CC
(2)
Supply current (Write)
Supply current
CC1
(Standby mode)
Input low voltage
V
IL
V
Input high voltage
IH
Output low voltage
OL
Output high voltage
OH
Internal reset threshold
(3)
voltage
(in addition to conditions
specified in
= 0 V 8
OUT
= 0 V 6
IN
= VSS or V
IN
= 1.8 V, C = 0.1VCC/0.9VCC,
V
CC
CC
= VSS or V
OUT
Tabl e 1 1 )
CC
Q = open, fC = 5 MHz
= 2.5 V, C = 0.1VCC/0.9VCC,
V
CC
Q = open, f
= 5.5 V, fC = 20 MHz
V
CC
= 10 MHz
C
(1)
C = 0.1VCC/0.9VCC, Q = open
1.8 V ≤ V
= V
S
t° = 85 °C, VCC = 1.8 V, S = V
VIN = VSS or V
t° = 85 °C, VCC = 2.5 V, S = V
VIN = VSS or V
t° = 85 °C, VCC = 5.5 V, S = V
VIN = VSS or V
t° = 125 °C, VCC = 1.8 V, S = V
VIN = VSS or V
t° = 125 °C, VCC = 2.5 V, S = V
VIN = VSS or V
t° = 125 °C, VCC = 5.5 V, S = V
VIN = VSS or V
1.8 V ≤ V
2.5 V ≤ V
1.8 V ≤ V
2.5 V ≤ V
< 5.5 V during tW,
CC
CC
CC,
CC
CC,
CC
CC,
CC
CC,
CC
CC,
CC
CC,
CC
< 2.5 V –0.45 0.25 V
CC
< 5.5 V –0.45 0.3 V
CC
< 2.5 V 0.75 V
CC
< 5.5 V 0.7 V
CC
VCC = 1.8 V, IOL = 1 mA 0.3
≥ 2.5 V, IOL = 2 mA 0.4
V
CC
V
= 1.8 V, IOH = 1 mA 0.8 V
CC
VCC ≥ 2.5 V, IOH = -2 mA 0.8 V
Min. Max. Unit
pF
2
µA
3
2
2
mA
5
(3)
2
1
2
3
µA
15
15
20
CC
CC
CCVCC
CCVCC
+0.5
+0.5
V
CC
CC
0.5 1.3
1. When –40 °C < t° < 85 °C.
2. Average value during the Write cycle (tW)
3. Characterized only, not 100% tested
30/39 Doc ID 022682 Rev 1
Page 31
M95512-A125 M95512-A145 DC and AC parameters
Table 15. AC characteristics
Min. Max. Min. Max. Min. Max.
Test
Symbol Alt. Parameter
Test
conditions
specified in
Table 11
f
f
C
t
SLCH
t
SHCHtCSS2
t
SHSL
t
CHSH
t
CHSL
t
CH
t
CL
t
CLCH
t
CHCL
t
DVC H
t
CHDX
t
HHCH
t
HLCH
t
CLHL
t
CLHH
t
SHQZ
t
CLQV
t
CLQX
t
QLQH
t
QHQL
t
HHQV
t
HLQZ
t
W
1. tCH + tCL must never be lower than the shortest possible clock period, 1/fC(max).
2. Value guaranteed by characterization, not 100% tested in production.
3. t
CLQV
(or greater than) t
t
(1)
(1)
(2)
(2)
(2)
(3)
(2)
(2)
(2)
must be compatible with tCL (clock low time): if tSU is the Read setup time of the SPI bus master, tCL must be equal to
Clock frequency 5 10 20 MHz
SCK
S active setup time 60 30 15
CSS1
S not active setup time 60 30 15
t
S deselect time 90 40 20
CS
t
S active hold time 60 30 15
CSH
S not active hold time 60 30 15
t
Clock high time 80 40 20
CLH
t
Clock low time 80 40 20
CLL
t
Clock rise time 2 2 2
RC
t
Clock fall time 2 2 2
FC
t
Data in setup time 20 10 5
DSU
t
Data in hold time 20 10 10
DH
Clock low hold time after HOLD not active 60 30 15
Clock low hold time after HOLD active 60 30 15
Clock low set-up time before HOLD active 0 0 0
Clock low set-up time before HOLD not
active
t
Output disable time 80 40 20
DIS
t
Clock low to output valid 80 40 20
V
t
Output hold time 0 0 0
HO
t
Output rise time 20 20 20
RO
t
Output fall time 20 20 20
FO
t
HOLD high to output valid 80 40 20
LZ
t
HOLD low to output high-Z 80 40 20
HZ
t
Write time 4 4 4 ms
WC
CLQV+tSU
.
000
conditions
specified in
Table 10
and
Table 11
Test
conditions
specified in
Tabl e 1 2
Unit
ns
µs
ns
Doc ID 022682 Rev 1 31/39
Page 32
DC and AC parameters M95512-A125 M95512-A145
!)#
6
##
6
##
6
##
6
##
)NPUTANDOUTPUT
TIMINGREFERENCELEVELS
)NPUTVOLTAGELEVELS
C
D
AI01447d
S
MSB IN
Q
tDVCH
High impedance
LSB IN
tSLCH
tCHDX
tCLCH
tSHCH
tSHSL
tCHSHtCHSL
tCH
tCL
tCHCL
C
Q
AI01448c
S
HOLD
tCLHL
tHLCH
tHHCH
tCLHH
tHHQVtHLQZ
Figure 17. AC measurement I/O waveform
Figure 18. Serial input timing
Figure 19. Hold timing
32/39 Doc ID 022682 Rev 1
Page 33
M95512-A125 M95512-A145 DC and AC parameters
C
Q
AI01449f
S
D
ADDR
LSB IN
tSHQZ
tCH
tCL
tQLQH
tQHQL
tCHCL
tCLQX
tCLQV
tSHSL
tCLCH
Figure 20. Serial output timing
Doc ID 022682 Rev 1 33/39
Page 34
Package mechanical data M95512-A125 M95512-A145
SO-A
E1
8
ccc
b
e
A
D
c
1
E
h x 45˚
A2
k
0.25 mm
L
L1
A1
GAUGE PLANE
9 Package mechanical data
In order to meet environmental requirements, ST offers these devices in different grades of
ECOPACK
specifications, grade definitions and product status are available at: www.st.com.
ECOPACK
®
packages, depending on their level of environmental compliance. ECOPACK®
®
is an ST trademark.
Figure 21. SO8N – 8-lead plastic small outline, 150 mils body width, package outline
1. Drawing is not to scale.
Table 16. SO8N – 8-lead plastic small outline, 150 mils body width, package
mechanical data
millimeters inches
Symbol
Typ Min Max Typ Min Max
(1)
A 1.75 0.0689
A1 0.10 0.25 0.0039 0.0098
A2 1.25 0.0492
b 0.28 0.48 0.011 0.0189
c 0.17 0.23 0.0067 0.0091
ccc 0.10 0.0039
D 4.90 4.80 5.00 0.1929 0.189 0.1969
E 6.00 5.80 6.20 0.2362 0.2283 0.2441
E1 3.90 3.80 4.00 0.1535 0.1496 0.1575
e1.27– –0.05- -
h 0.25 0.50 0.0098 0.0197
k 0°8° 0°8°
L 0.40 1.27 0.0157 0.05
L1 1.04 0.0409
1. Values in inches are converted from mm and rounded to 4 decimal digits.
34/39 Doc ID 022682 Rev 1
Page 35
M95512-A125 M95512-A145 Package mechanical data
TSSOP8AM
1
8
CP
c
L
EE1
D
A2A
α
eb
4
5
A1
L1
Figure 22. TSSOP8 – 8-lead thin shrink small outline, package outline
1. Drawing is not to scale.
Table 17. TSSOP8 – 8-lead thin shrink small outline, package mechanical data
millimeters inches
Symbol
Typ. Min. Max. Typ. Min. Max.
(1)
A 1.200 0.0472
A1 0.050 0.150 0.0020 0.0059
A2 1.000 0.800 1.050 0.0394 0.0315 0.0413
b 0.190 0.300 0.0075 0.0118
c 0.090 0.200 0.0035 0.0079
CP 0.100 0.0039
D 3.000 2.900 3.100 0.1181 0.1142 0.1220
e 0.650 – – 0.0256 – –
E 6.400 6.200 6.600 0.2520 0.2441 0.2598
E1 4.400 4.300 4.500 0.1732 0.1693 0.1772
L 0.600 0.450 0.750 0.0236 0.0177 0.0295
L1 1.000 0.0394
α 0° 8° 0° 8°
1. Values in inches are converted from mm and rounded to four decimal digits.
Doc ID 022682 Rev 1 35/39
Page 36
Package mechanical data M95512-A125 M95512-A145
$
%
:7?-%E
!
!
EEE
,
E
B
$
,
%
,
,
E B
$
,
%
,
0IN
+
+
-" -#
Figure 23. UFDFPN8 (MLP8) - 8-lead ultra thin fine pitch dual flat no lead, package
outline
1. Drawing is not to scale.
2. The central pad (the area E2 by D2 in the above illustration) is internally pulled to V
connected to any other voltage or signal line on the PCB, for example during the soldering process.
Table 18. UFDFPN8 (MLP8) 8-lead ultra thin fine pitch dual flat package no lead
. It must not be
SS
2 x 3 mm, data
millimeters inches
Symbol
Typ Min Max Typ Min Max
(1)
A 0.550 0.450 0.600 0.0217 0.0177 0.0236
A1 0.020 0.000 0.050 0.0008 0.0000 0.0020
b 0.250 0.200 0.300 0.0098 0.0079 0.0118
D 2.000 1.900 2.100 0.0787 0.0748 0.0827
D2 (rev MB) 1.600 1.500 1.700 0.0630 0.0591 0.0669
D2 (rev MC) 1.200 1.600 0.0472 0.0630
E 3.000 2.900 3.100 0.1181 0.1142 0.1220
E2 (rev MB) 0.200 0.100 0.300 0.0079 0.0039 0.0118
E2 (rev MC) 1.200 1.600 0.0472 0.0630
e 0.500 0.0197
K (rev MB) 0.800 0.0315
K (rev MC) 0.300 0.0118
L 0.300 0.500 0.0118 0.0197
L1 0.150 0.0059
L3 0.300 0.0118
(2)
eee
1. Values in inches are converted from mm and rounded to four decimal digits.
2. Applied for exposed die paddle and terminals. Exclude embedding part of exposed die paddle from
measuring.
0.080 0.0031
36/39 Doc ID 022682 Rev 1
Page 37
M95512-A125 M95512-A145 Part numbering
10 Part numbering
Table 19. Ordering information scheme
Example: M95512-D W DW 4 T P /K
Device type
M95 = SPI serial access EEPROM
Device function
512-D = 512 Kbit (64 Kbytes × 8) plus Identification Page
512 = 512 Kbit (64 Kbytes × 8)
Operating voltage
W = V
R = V
Package
= 2.5 to 5.5 V
CC
= 1.8 to 5.5 V
CC
(1)
MN = SO8 (150 mils width)
DW = TSSOP8 (169 mils width)
MB or MC = MLP8 (2 × 3 mm)
Device grade
3 = –40 to 125 °C. Device tested with high reliability certified flow
4 = –40 to 145 °C. Device tested with high reliability certified flow
(2)
(2)
Option
blank = Standard packing
T = Tape and reel packing
Plating technology
P or G = ECOPACK (RoHS compliant)
Process letter
/K= Manufacturing technology code
1. All packages are ECOPACK2® (RoHS compliant and Halogen-free).
2. The high reliability certified flow (HRCF) is described in quality note QNEE9801. Please ask your nearest ST
sales office for a copy.
For a list of available options (speed, package, etc.) or for further information on any aspect
of this device, please contact your nearest ST sales office.
Doc ID 022682 Rev 1 37/39
Page 38
Revision history M95512-A125 M95512-A145
11 Revision history
Table 20. Document revision history
Date Revision Changes
14-Feb-2012 1 Initial release.
38/39 Doc ID 022682 Rev 1
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M95512-A125 M95512-A145
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