Datasheet M95256-WMW1T, M95256-WMW1, M95256-WBN6, M95256-WBN5, M95256-VMW6 Datasheet (SGS Thomson Microelectronics)

1/21

PRELIMINARY DATA

March 2000

This is preliminary information on a new product now in development or undergoing evaluation. Details are subject to change without notice.

M95256
M95128

256/128 Kbit Serial SPI Bus EEPROM

With High Speed Clock

■ SPI Bus Compatible Serial Interface

■ Supports Positive Clock SPI Modes

■ 5 MHz Clock Rate (maximum)

■ Single Supply Voltage:

– 4.5V to 5.5V for M95xxx
– 2.7V to 3.6V for M95xxx-V
– 2.5V to 5.5V for M95xxx-W
– 1.8V to 3.6V for M95xxx-R

■ Status Register

■ Hardware and Software Protection of the Status

Register

■ BYTE and PAGE WRITE (up to 64 Bytes)

■ Self-Tim ed P ro gr a m ming Cycle

■ Resizeable Read-Only EEPROM Area

■ Enhanced ESD Protection

■ 100,000 Erase/Write Cycles (minimum)

■ 40 Year Data Retention (minimum)

DESCRIPTION

These SPI-compatible electrically erasable
programmable memory (EEPROM) devices are
organized as 32K x 8 bits (M9525 6) and 16K x 8
bits (M95128), and operate down to 2.7 V (for the

Figure 1. Logic Diagram

AI01789C

S

V

CC

M95xxx

HOLD

V

SS

W

Q

C

D

Table 1. Signal Names

C Serial Clock
D Serial Data Input
Q Serial Data Output

S

Chip Select

W

Write Protect

HOLD

Hold

V

CC

Supply Voltage

V

SS

Ground

PSDIP8 (BN)

0.25 mm frame

SO8 (MN)

150 mil width

TSSOP14 (DL)

169 mil width

8

1

8

1

14

1

SO8 (MW)

200 mil width

8

1

M95256, M95128

2/21

-V version), 2.5 V (for the -W version), and down
to 1.8 V (for the -R version of each device).

The M95256 and M 95128 are available in Plastic
Dual-in-Line, Plastic Small Outline and Thin Shrink
Small Outline packages.

Each memory device is accessed by a simple
serial interface that is SPI bus compatible. The bus
signals are C, D and Q, as shown in Table 1 and
Figure 3.

The device is selected when t he chip select input
(S

) is held low. Communications with the chip can

be interrupted using the hold input (HOLD

).

Figure 2A. DIP Connections

Figure 2B. SO C on ne ct i on s

DV

SS

C

HOLDQ

SV

CC

W

AI01790C

M95xxx

1
2
3
4

8
7
6
5

1

AI01791C

2
3
4

8
7
6
5

DV

SS

C

HOLDQ

SV

CC

W

M95xxx

Figure 2C. TSSOP Connections

Note: 1. NC = Not Connected

1

AI02346

2
3
4

14

9

10

8

DV

SS

WC

S

HOLD

M95128

NC

Q

NC

NC NC

NC

NC

5
6
7

12

13

11

V

CC

Table 2. Absolute Maximum Ratings

1

Note: 1. Except for the rating “Operating Tempera ture Range”, stres ses above th ose listed i n the Tabl e “Absolute Maxim um Ratings” may

cause permanent damage to the device. These are stress ratings only, and operation of the device at these or any other conditions
above those indicated in the Operating sections of this specification is not implied. Exposure to Absolute Maximum Rating
conditions for extended periods may affect device reliability. Refer also to the ST SURE Program and other relevant quality
document s.

2. M IL-STD-883C, 3015.7 (100 pF, 1500 Ω)

Symbol Parameter Value Unit

T

A

Ambient Operating Temperature -40 to 125 °C

T

STG

Storage Temperature -65 to 150 °C

T

LEAD

Lead Temperature during Soldering

PSDIP8: 10 sec
SO8: 40 sec
TSSOP14: t.b.c.

260
215

t.b.c.

°C

V

O

Output Voltage Range

-0.3 to V

CC

+0.6

V

V

I

Input Voltage Range -0.3 to 6.5 V

V

CC

Supply Voltage Range -0.3 to 6.5 V

V

ESD

Electrostatic Discharge Voltage (Human Body model)

2

4000 V

3/21

M95256, M95128

SIGNAL DESCRIPTION
Seria l O utput ( Q )

The output pin is used to transfer data serially out
of the Memory. Data is shifted out on the falling
edge of the serial clock.

Serial Inpu t ( D )

The input pin is used to transfer data serially into
the device. Instructions, addresses, and the data
to be written, are each received this way . Input is
latched on the rising edge of the serial clock.

Serial Clock (C)

The serial clock provides the timing for the serial
interface (as shown in Figure 4). Instructions,
addresses, or data are latched, from the input pin,
on the rising edge of the clock input. The output
data on the Q pin chang es state after the falling
edge of the clock input.

Chip Select (S

)

When S

is high, the memory device is deselected,
and the Q output pin is held in its high impe dance
state. Unless an internal write operation is
underway, the memory device is placed in its
stand-by power mode.

After power-on, a high-to-low transition on S

is

required prior to the start of any operation.

Write Protect (W

)

The protection features of t he m em ory device are
summarized in Table 3.

The hardware write protection, controlled by the W
pin, restricts write access to the Status Register

(though not to the WIP and WEL bits, which are
set or reset by the device internal logic).

Bit 7 of the status register (as shown in Table 5) is
the Status Register Write Disable bit (SRWD).
When this is set to 0 (its initial delivery state) it is
possible to write to the status register if the WEL
bit (Write Enable Latch) has been set by the
WREN instruction (irrespective of the l evel being
applied to the W

input).

When bit 7 (SRWD) of the st atus register is set to
1, the ability to write to the status register depends
on the logic level being presented at pin W

:

–If W

pin is high, it is possible to write to the
status register, after having set the WEL bit
using the WREN instruction (Write Enable
Latch).

–If W

pin is low, any attempt to modify the status
register is ignored by the device, even if the
WEL bit has been set. As a consequence, all the
data bytes in the EE PROM area, protected by
the BPn bits of the status register, are also
hardware protected against data corruption,
and appear as a Read Only EEPROM area for
the microcontroller. This mode is called the
Hardware Protected Mode (HPM).

It is possible to enter the Hardware Protected
Mode (HPM) either by s etting the SRWD bi t after
pulling low the W

pin, or by pulling low the W pin

after setting the SRWD bit.
The only way to abort the Hardware Protected

Mode, once entered, is to pull high the W

pin.

If W

pin is permanently t ied to the hi gh level, the

Hardware Protected Mode is never activated, and

Figure 3. Microcontroller and Memor y Devices on the SPI Bus

AI01958C

Master

(ST6, ST7, ST9,

ST10, Others)

M95xxx

SDO

SDI

SCK

CQD

S

M95xxx

CQD

S

M95xxx

CQD

S

CS3 CS2 CS1

SPI Interface with
(CPOL, CPHA) =
('0', '0') or ('1', '1')

M95256, M95128

4/21

the memory device only allows the user to protect
a part of the memory, usi ng the BPn bits of the
status register, in the Software Protected Mode
(SPM).

Hold (HOLD

)

The HOLD

pin is used to pause the serial
communications between the SPI memory and
controller, without losing bits that have already
been decoded in the serial sequence. For a hold
condition to occur, the memory device must
already have been selected (S

= 0). The hold

condition starts when the HOLD

pin is held low
while the clock pin (C) is also low (as shown in
Figure 5).

During the hold condition, the Q output pin i s held
in its high impedance sta te, and the level s on the
input pins (D and C) are ignored by the memory
device.

It is possible to deselect the device whe n it is still
in the hold state, thereby resetting whatever
transfer had been in progress. The memory
remains in the hold state as long as the HOLD

pin
is low. To restart communication with the device, it
is necessary both to remove the hold condition (by
takin g HO LD

high) and to select the memory (by

taking S

low).

OPERATIONS

All instructions, addresses and data are shifted
serially in and out of the chip. The most significant
bit is presented first, with the data input (D)
sampled on the first rising edge of the clock (C)
after the chip select (S

) goes low.

Every instruction starts with a single-byte code, as
summarized in Table 4. This code is entered via
the data input (D), and latched on the rising edge
of the clock input (C). To enter an instruction code,
the product must have been previously selected (S
held low). If an invalid i nstruction is sent (one not
contained in Table 4), the chip automatically
deselects itself.

Write Enable (WREN) and Write Disable (WRDI)

The write enable latch, inside the memory device,
must be set prior to each WRITE and WRSR
operation. The WREN instruction (write enable)
sets this latch, and the WRDI instruction (write
disable) resets it.

The latch becomes reset by any of the following
events:

– Power on
– WRDI instruction completion
– WRSR in s t ru ctio n completio n
– WRITE instruction completion.

Table 3. Write Protection Control on the M95256 and M95128

W

SRWD

Bit

Mode Status Register

Data Bytes

Protected Area Unprotected Area

0 or 1 0 Software

Protected

(SPM)

Writeable (if the WREN

instruction has set the

WEL bit)

Software write protected

by the BPn of the status

register

Writeable (if the WREN

instruction has set the

WEL bit)

11

01

Hardware
Protected

(HPM)

Hardware write protected

Hardware write protected

by the BPn bits of the

status register

Writeable (if the WREN

instruction has set the

WEL bit)

Figure 4. Dat a and Clock Timi ng

AI01438

C

C

MSB LSB

CPHA

D or Q

0

1

CPOL

0

1

5/21

M95256, M95128

Figure 5. Hold Condition Activation

Figure 6. Block Diagram

Note: 1. The cell

An

represents the byte at the highest address in the memory

AI02029B

HOLD PIN

CLOCK

ACTIVE

MEMORY
STATUS

HOLD ACTIVE HOLD ACTIVE

AI02030B

HOLD

S

W

Control Logic

High Voltage

Generator

I/O Shift Register

Address Register

and Counter

Data

Register

64 Bytes

X Decoder

Y Decoder

Size of the
Read only
area of the
EEPROM

C

D

Q

Status

Register

AnAn - 63

003Fh0000h

M95256, M95128

6/21

As soon as the WREN or WRDI instruction is
received, the memory device first executes the
instruction, then enters a wait mode until the
device is deselected.

Read Status Register (RDSR)

The RDSR instruction allows the status register to
be read, and can be sent at any time, even during
a Write operation. Indeed, when a Write is in
progress, it is recommended th at the value of t he
Write-In-Progress (WIP) bit be checked. The value
in the WIP bit (whose position in the status register
is shown in Table 5) can be continuously p olled,
before sending a new WRITE instruction, using
the timing shown in Figure 7. The Write-In­Process (WIP) bit is read-only, and indicates
whether the memory is busy with a Write

operation. A ’1’ indicates that a write is in progress,
and a ’0’ that no write is in progress.

The Write Enable Latch (WEL) bit indicates the
status of the write enable latch. It, too, is read-only.

Its value can only be changed by one of the events
listed in the previous paragraph, or as a result of
executing WREN or WRDI instruction. It cannot be
changed using a WRSR instruction. A ’1’ indicates
that the latch is set (the forthcoming Write
instruction will be executed), and a ’0’ that it is
reset (and any forthcoming Write instructions will
be ignored).

The Block Protect (BP0 and BP1) bits indicate the
amount of the memory that is to be write­protected. These two bits are non-volatile. They
are set using a WRSR instruction.

During a Write operation (whether it be to the
memory area or to the status register), all bits of
the status register remain valid, and can be read
using the RDSR instruction. However, during a
Write operation, the values of the no n-vo latile bits
(SRWD, BP0, BP1) be come frozen at a constant
value. The updated value of these bi ts becomes
available when a new RDSR instruction is
executed, after completio n of the write cycle. On
the other hand, the two read-only bits (WEL, WIP)
are dynamically updated during internal write
cycles. U sing t his fac ility, it is possib le to p oll the
WIP bit to detect the end of the internal write cycle.

Write Status Register (WRSR)

The format of the WRSR instruction is shown in
Figure 8. After the instruction and the eigh t bits of
the status register have been latched-in, the
internal Write cycle is triggered by the rising edge
of the S

line. This must occur before the rising

edge of the 17

th

clock pulse (as indicated in Figure

14), otherwise the internal write sequence is not
performed.

The WRSR instruction is used for the following:

■ to select the size of memory area that is to be

write-protected

■ to select between SPM (Software Protected

Mode) and HPM (Hardware Protected Mode).

Figure 7. RDSR: Read Status Register Sequence

C

D

S

21 3456789101112131415

INSTRUCTION

0

AI02031

Q

7 6543210

STATUS REG. OUT

HIGH IMPEDANCE

MSB

7 6543210

STATUS REG. OUT

MSB MSB

7

Table 4. Instruction Set

Table 5. Status Register Format

Note: 1. SRWD, BP0 and BP1 are Read and wri te bits.

2. WEL and WIP are Read only bits.

Instruc

tion

Description

Instruction

Format

WREN Set Write Enable Latch 0000 0110
WRDI Reset Write Enable Latch 0000 0100
RDSR Read Status Register 0000 0101
WRSR Write Status Register 0000 0001
READ Read Data from Memory Array 0000 0011
WRITE Write Data to Memory Array 0000 0010

b7 b0

SRWD X X X BP1 BP0 WEL WIP

7/21

M95256, M95128

The size of the write-protection area applies
equally in SPM and HPM. The BP1 and BP0 bits
of the status register have the appropriate value
(see Table 6) written into them after the contents
of the protected area of the EEPROM have been
written.

The initial delivery state of the BP1 and BP0 bits is
00, indicating a write-protection size of 0.

Software Protected Mode (SPM)

The act of writing a non-zero value to the BP1 and
BP0 bits causes the Software Protected Mode
(SPM) to be started. All attempts to write a byte or
page in the protected area are ignored, even if the
Write Enable Latch is set. However, writing is still
allowed in the unprotected area of the memory
array and to the SRWD, BP 1 and BP 0 bits of the
status register, provided that the WEL bit is first
set.

Hardware Prot ected Mode (H P M)

The Hardware Protected Mode (HPM) offers a
higher level of protection, and can be selected by
setting the SRWD bit after pulling down the W

pin
or by pulling down the W

pin after setting the
SRWD bit. The SRWD is set by the WSR
instruction, provided that the WEL bit is first set.

The setting of the SRWD bit can be made
independently of, or at the same time as, writing a
new value to the BP1 and BP0 bits.

Once the device is in the Hardware Protected
Mode, the data bytes in the protected area of the
memory array,

and

the content of the status
register, are write-protected. The only way to re­enable writing new v alue s t o t he s tatus register is
to pull the W

pin high. This cause the device to
leave the Hardware Protected Mode, and to revert
to being in the Software Protected Mode. (The
value in the BP1 and BP0 bits will not have been
changed).

Further details of the operation of the Write Protect
pin (W

) is given earlier, on page 3.

Typical Use of HPM and SPM

The W

pin can be dynamically driven by an output
port of a microcontroller. It is also possible,
though, to connect it permanently to V

SS

(by a
solder connection, or through a pull-down
resistor). The manufacturer of such a printed
circuit board can take the memory device, still in its
initial delivery state, and can solder it directly on to
the board. After power on, the microcontroller can
be instructed to write the protected data into the

Table 6. Write Protected Block Size

Status Register Bits

Protected Block

Array Addresses Protected

BP1 BP0 M95256 M95128

0 0 none none none
0 1 Upper quarter 6000h - 7FFFh 3000h - 3FFFh
1 0 Upper half 4000h - 7FFFh 2000h - 3FFFh
1 1 Whole memory 0000h - 7FFFh 0000h - 3FFFh

Figure 8. WRSR: Write Status Register Sequence

C

D

AI02282

S

Q

21 3456789101112131415

HIGH IMPEDANCE

INSTRUCTION STATUS REG.

0

765432 0

1

MSB

M95256, M95128

8/21

appropriate area of the memory. When it has
finished, the appropriate v alues a re written to the
BP1, BP0 and SRWD bits, thereby putting the
device in the hardware protected mode.

An alternative method is to write the protected
data, and to set the BP1, BP0 and SRWD bits,
before soldering the memory device to the board.
Again, this results in the memory device being
placed in its hardware protected mode.

If the W

pin has been connect ed to VSS by a pull-

down resistor, the mem ory device can be taken

out of the hardware protected mode by driving the
W

pin high, to override the pull-down resistor.

If the W

pin has been directly soldered to VSS,
there is only one way of taking the memory device
out of the hardware protect ed mode: t he memory
device must be de-soldered from the board, and
connected to external equipment in which the W
pin is allowed to be taken high.

Read Operation

The chip is first selected by holding S

low. The
serial one byte read instruction is followed by a two
byte address (A15-A0), each bit being latched-in
during the rising edge of the clock (C).

The data stored in the memory, at the selected
address, is shifted out on the Q output pin. Eac h
bit is shifted out during the falling edge of the clock
(C) as shown in Figure 9. The internal address
counter is automatically increment ed to the next
higher address after ea ch byte of data has b een
shifted out. The data stored i n t he m em ory, at t he

Figure 9. Rea d EEPRO M Arr a y Oper a t ion Sequence

Note: 1. Depending on the memory size, as shown in Table 7, the most significant address bits are Don’t Care.

C

D

AI01793

S

Q

15

21 345678910 2021222324252627

1413 3210

28 29 30

765432 0

1

HIGH IMPEDANCE

DATA OUT

INSTRUCTION 16 BIT ADDRESS

0

MSB

Table 7. Address Range Bits

Note: 1. b15 is Don’t Care on t he M 9 5256 series.

b15 and b14 ar e Don’t Care on t he M95128 se ri es.

Device M95256 M95128

Address Bits A14-A0 A13-A0

Figure 10. Write Enable Latch Sequen ce

C

D

AI02281B

S

Q

21 34567

HIGH IMPEDANCE

0

INSTRUCTION

9/21

M95256, M95128

a write cycle, it is rejected, and the memory device
deselects itself.

Byte Write Operat ion

Before any write can take place, the WEL bit must
be set, using the WREN instruction. The write
state is entered by selecting the chip, issuing three

next address, can be read by successive clock
pulses. When the highest addres s is reached, the

address counter rolls over to “0000h”, allowing the
read cycle to be continued indefini tely. The read
operation is terminated by deselecting the chip.
The chip can be deselected at any time during
data output. If a read instruction is received during

Figure 11. Byte Write Operation Sequence

Note: 1. Depending on the memory size, as shown in Table 7, the most significant address bits are Don’t Care.

C

D

AI01795

S

Q

15

21 345678910 2021222324252627

1413 3210

28 29 30

HIGH IMPEDANCE

INSTRUCTION 16 BIT ADDRESS

0

765432 0

1

DATA BYTE

31

Figure 12. Page Write Operation Sequence

Note: 1. Depending on the memory size , as shown in Table 7, the mo st si gnifica nt address bit s are Don’t Care.

C

D

AI01796

S

3433 35 36 37 38 39 40 41 42 44 45 46 4732

C

D

S

15

21 345678910 2021222324252627

1413 3210

28 29 30

INSTRUCTION 16 BIT ADDRESS

0

765432 0

1

DATA BYTE 1

31

43

765432 0

1

DATA BYTE 2

765432 0

1

DATA BYTE 3

65432 0

1

DATA BYTE N

M95256, M95128

10/21

bytes of instruction and address, and one byte of
data. Chip Select (S

) must remain low t hroughout
the operation, as shown in Figure 11. The product
must be deselected just after t he eighth b it of the
data byte has been latched in, otherwise the write
process is cancelled. As soon as the memory
device is deselected, the self-timed internal write
cycle is initiated. While the write is in progress, the
status register may be read t o c heck the s tatus of
the SRWD, BP1, BP0, WEL and WIP bits. In

particular, WIP contains a ‘1’ during the self-timed
write cycle, and a ‘0’ when the cycle is complete,
(at which point the write enable latch is also reset).

Page Write Operation

A maximum of 64 bytes of data can be written
during one Write time, t

W

, provided that they are all
to the same page (see Figure 6). The Page Write
operation is the same as the Byte Write operation,
except that instead of deselecting the device after
the first byte of data, up to 63 additional bytes can
be shifted in (and t hen the device is deselected
after the last byte).

Any address of the memory can be chosen as the
first address to be wri tten. If the addres s counter
reaches the end of the page (an add ress of the
form xxxx xx11 1111) and t he cl ock continues, the
counter rolls over to the first address of the same
page (xxxx xx00 0000) and over-writes any
previously written data.

As before, the Write cycle only starts if the S
transition occurs just after the eighth bit of the last
data byte has been received, as shown in Figure

12.

DATA PROTECTION AND PROTOCOL SAFETY

To protect the data in the memory from inadvertent
corruption, the memory device only responds to
correctly formulated commands. The main
security measures can be summarized as follows:

– The WEL bit is reset at power-up.
–S

must rise after the eighth clock count (or
multiple thereof) in ord er to start a non-volatile
write cycle (in the memory array or in the status
register).

– Accesses to the memory array are ignored

during the non-volatile programming cycle, and
the programming cycle continues unaffected.

– After execution of a WREN, WRDI, or RDSR

instruction, the chip enters a wait state, and
waits to be deselected.

– Inva lid S

and HOLD transitions are ignored.

POWE R O N STATE

After power-on, the memory device is in the
following state:

– low power stand-by state
– deselected (after power-on, a high-to-low

transition is required on the S

input before any

operations can be started).

– not in the hold condition
– the WEL bit is reset
– the SRWD, BP1 and BP0 bits of the status

register are un-changed from the previous
power-down (they are non-volatile bits).

INITIAL DELIVERY STATE

The device is delivered with the memory array in a
fully erased state (all data set at all “1’s” or FFh).
The status register bits are initialized to 00h, as
shown in Table 8.

Table 8. Initial Status Register Format

Table 9. AC Measurement Conditions

Note: 1. Output Hi-Z is defined as the point where data is no

longer driven.

b7 b0

0 0000 0 0 0

Input Rise and Fall Times

≤

50 ns

Input Pulse Voltages

0.2V

CC

to 0.8V

CC

Input and Output Timing
Reference Voltages

0.3V

CC

to 0.7V

CC

Output Load

C

L

= 100 pF

Table 10. Input Parameters1 (TA = 25 °C, f = 5 MHz)

Note: 1. Sampled only, not 100% tested.

Symbol Parameter Test Condition Min. Max. Unit

C

OUT

Output Capacitance (Q) 8 pF

C

IN

Input Capacitance (other pins) 6 pF

Figure 13. AC Testing Input Output Waveforms

AI00825

0.8V

CC

0.2V

CC

0.7V

CC

0.3V

CC

11/21

M95256, M95128

Table 11. DC Characteristics

(T

A

= 0 to 70 °C, –40 to 85 °C or –40 to 125 °C; VCC = 4.5 to 5.5 V)

(T

A

= 0 to 70 °C or –40 to 85 °C; VCC = 2.7 to 3.6 V)

(T

A

= 0 to 70 °C or –40 to 85 °C; VCC = 2.5 to 5.5 V)

(T

A

= 0 to 70 °C or –20 to 85 °C; VCC = 1.8 to 3.6 V)

Note: 1. For all 5V range devi ces, the devi ce meets th e out put requi rem ents for b oth TTL and CMOS standards.

Symbol Parameter

Voltage

Range

Temp.
Range

Test Condition Min. Max. Unit

I

LI

Input Leakage
Current

all all ± 2 µA

I

LO

Output Leakage
Current

all all ± 2 µA

I

CC

Supply Current

4.5-5.5 6

C=0.1V

CC

/0.9. VCC at 5 MHz,

V

CC

= 5 V, Q = open

4mA

4.5-5.5 3

C=0.1V

CC

/0.9. VCC at 2 MHz,

V

CC

= 5 V, Q = open

4mA

2.7-3.6 6

C=0.1V

CC

/0.9. VCC at 5 MHz,

V

CC

= 2.7 V, Q = open

3mA

2.5-5.5 6

C=0.1V

CC

/0.9. VCC at 2 MHz,

V

CC

= 2.5 V, Q = open

2mA

1.8-3.6 5

C=0.1V

CC

/0.9. VCC at 1 MHz,

V

CC

= 1.8 V, Q = open

2mA

I

CC1

Supply Current
(Stand-by)

4.5-5.5 6

S

= VCC, V

IN

= VSS or V

CC

, V

CC

= 5 V

10 µA

4.5-5.5 3

S

= VCC, V

IN

= VSS or V

CC

, V

CC

= 5 V

20 µA

2.7-3.6 6

S

= VCC, V

IN

= VSS or V

CC

, V

CC

= 2.7 V

2µA

2.5-5.5 6 S

= VCC, V

IN

= VSS or V

CC

, V

CC

= 2.5 V 2 µA

1.8-3.6 5 S

= VCC, V

IN

= VSS or V

CC

, V

CC

= 1.8 V 1 µA

V

IL

Input Low
Voltage

all all – 0.3

0.3 V

CC

V

V

IH

Input High
Voltage

all all

0.7 V

CC

VCC+1

V

V

OL

1

Output Low
Voltage

4.5-5.5 6 I

OL

= 2 mA, VCC = 5 V 0.4 V

4.5-5.5 3

I

OL

= 2 mA, VCC = 5 V

0.4 V

2.7-3.6 6 I

OL

= 1.5 mA, VCC = 2.7 V 0.4 V

2.5-5.5 6

I

OL

= 1.5 mA, VCC = 2.5 V

0.4 V

1.8-3.6 5 I

OL

= 0.15 mA, VCC = 1.8 V

0.3

V

V

OH

1

Output High
Voltage

4.5-5.5 6

I

OH

= –2 mA, VCC = 5 V 0.8 V

CC

V

4.5-5.5 3

I

OH

= –2 mA, VCC = 5 V

0.8 V

CC

V

2.7-3.6 6 I

OH

= –0.4 mA, VCC = 2.7V 0.8 V

CC

V

2.5-5.5 6 I

OH

= –0.4 mA, VCC = 2.5V 0.8 V

CC

V

1.8-3.6 5 I

OH

= –0.1 mA, VCC = 1.8V 0.8 V

CC

V

M95256, M95128

12/21

Table 12A. AC Characteristics

Note: 1. tCH + tCL ≥ 1 / fC.

2. Value guarant eed by characterization, not 100% tested in pro duction.

Symbol Alt. Parameter

M95256 / M95128

Unit

V

CC

=4.5 to 5.5 V

T

A

=0 to 70°C or

-40 to 85°C

V

CC

=4.5 to 5.5 V

T

A

=-40 to 125°C

Min Max Min Max

f

C

f

SCK

Clock Frequency D.C. 5 D.C. 2 MHz

t

SLCH

t

CSS1

S Active Setup Time 90 200 ns

t

SHCH

t

CSS2

S Not Active Setup Time 90 200 ns

t

SHSL

t

CS

S Deselect Time 100 200 ns

t

CHSH

t

CSH

S Active Hold Time 90 200 ns

t

CHSL

S Not Active Hold Time 90 200 ns

t

CH

1

t

CLH

Clock High Time 90 200 ns

t

CL

1

t

CLL

Clock Low Time 90 200 ns

t

CLCH

2

t

RC

Clock Rise Time 1 1 µs

t

CHCL

2

t

FC

Clock Fall Time 1 1 µs

t

DVCH

t

DSU

Data In Setup Time 20 40 ns

t

CHDX

t

DH

Data In Hold Time 30 50 ns

t

DLDH

2

t

RI

Data In Rise Time 1 1 µs

t

DHDL

2

t

FI

Data In Fall Time 1 1 µs

t

HHCH

Clock Low Hold Time after HOLD not Active 70 140 ns

t

HLCH

Clock Low Hold Time after HOLD Active 40 90 ns

t

CHHL

Clock High Set-up Time before HOLD Active 60 120 ns

t

CHHH

Clock High Set-up Time before HOLD not Active 60 120 ns

t

SHQZ

2

t

DIS

Output Disable Time 100 250 ns

t

CLQV

t

V

Clock Low to Output Valid 60 150 ns

t

CLQX

t

HO

Output Hold Time 0 0 ns

t

QLQH

2

t

RO

Output Rise Time 50 100 ns

t

QHQL

2

t

FO

Output Fall Time 50 100 ns

t

HHQX

2

t

LZ

HOLD High to Output Low-Z 50 100 ns

t

HLQZ

2

t

HZ

HOLD Low to Output High-Z 100 250 ns

t

W

t

WC

Write Time 10 10 ms

13/21

M95256, M95128

Table 12B. AC Characteristics

Note: 1. tCH + tCL ≥ 1 / fC.

2. Value guarant eed by characterization, not 100% tested in pro duction.

Symbol Alt. Parameter

M95256-V /

M95128-V

M95256-W /

M95128-W

M95256-R /

M95128-R

Unit

V

CC

=

2.7 to 3.6 V

T

A

=0 to 70°C

or –40 to 85°C

V

CC

=

2.5 to 5.5 V

T

A

=0 to 70°C

or –40 to 85°C

V

CC

=

1.8 to 3.6 V

T

A

=0 to 70°C

or –20 to 85°C

Min Max Min Max Min Max

f

C

f

SCK

Clock Frequency D.C. 5 D.C. 2 D.C. 1 MHz

t

SLCHtCSS1

S Active Setup Time 90 200 400 ns

t

SHCHtCSS2

S Not Active Setup Time 90 200 400 ns

t

SHSL

t

CS

S Deselect Time 100 200 300 ns

t

CHSHtCSH

S Active Hold Time 90 200 400 ns

t

CHSL

S Not Active Hold Time 90 200 400 ns

t

CH

1

t

CLH

Clock High Time 90 200 400 ns

t

CL

1

t

CLL

Clock Low Time 90 200 400 ns

t

CLCH

2

t

RC

Clock Rise Time 0.05 1 1 µs

t

CHCL

2

t

FC

Clock Fall Time 0.05 1 1 µs

t

DVCHtDSU

Data In Setup Time 20 40 60 ns

t

CHDX

t

DH

Data In Hold Time 30 50 100 ns

t

DLDH

2

t

RI

Data In Rise Time 0.05 1 1 µs

t

DHDL

2

t

FI

Data In Fall Time 0.05 1 1 µs

t

HHCH

Clock Low Hold Time after HOLD not
Active

70 140 350 ns

t

HLCH

Clock Low Hold Time after HOLD Active 40 90 200 ns

t

CHHL

Clock High Set-up Time before HOLD
Active

60 120 250 ns

t

CHHH

Clock High Set-up Time before HOLD
not Active

60 120 250 ns

t

SHQZ

2

t

DIS

Output Disable Time 100 250 500 ns

t

CLQV

t

V

Clock Low to Output Valid 60 150 380 ns

t

CLQX

t

HO

Output Hold Time 0 0 0 ns

t

QLQH

2

t

RO

Output Rise Time 50 100 200 ns

t

QHQL

2

t

FO

Output Fall Time 50 100 200 ns

t

HHQX

2

t

LZ

HOLD High to Output Low-Z 50 100 250 ns

t

HLQZ

2

t

HZ

HOLD Low to Output High-Z 100 250 500 ns

t

W

t

WC

Write Time 10 10 10 ms

M95256, M95128

14/21

Figure 14. Serial Input Timing

Figure 15. Hol d Timing

Figure 16. Output Timing

C

D

AI01447

S

MSB IN

Q

tDVCH

HIGH IMPEDANCE

LSB IN

tSLCH

tCHDX

tDLDH
tDHDL

tCHCL

tCLCH

tSHCH

tSHSL

tCHSHtCHSL

C

Q

AI02032

S

D

HOLD

tCHHL

tHLCH

tHHCH

tCHHH

tHHQXtHLQZ

C

Q

AI01449B

S

LSB OUT

D

ADDR.LSB IN

tSHQZ

tCH

tCL

tQLQH
tQHQL

tCLQX

tCLQV

15/21

M95256, M95128

Table 13. Ordering Information Scheme

Note: 1. Temperature range available only on re quest.

2. Produced with High Reliability Certified Flow (HRCF), in V

CC

range 4.5 V to 5.5 V only.

3. T he -R version (V

CC

range 1.8 V t o 3. 6 V) only avail able in temperature ra nges 5 or 1.

4. SO8, 150 mil width, package is availa bl e for the M95128 series only.

5. T SSOP14, 169 mil wi dth, package is availa bl e for the M95128 series on ly.

Example: M95256 –R MW 6 T

Memory Capacity Option

256 256 Kbit (32K x 8) T Tape and Reel Packing
128 128 Kbit (16K x 8)

Temperature Range

1

1

0 °C to 70 °C

5 –20 °C to 85 °C

Operating Voltage 6 –40 °C to 85 °C

blank 4.5 V to 5.5 V

3

2

–40 °C to 125 °C

V

2.7 V to 3.6 V
W 2.5 V to 5.5 V Package
R

3

1.8 V to 3.6 V BN PSDIP8 (0.25 mm frame)

MW SO8 (200 mil width)
MN

4

SO8 (150 mil width)

DL

5

TSSOP14 (169 mil width)

ORDERING INFORMATION

The notation used for the device number is as
shown in Table 13. For a list of available options
(speed, package, etc.) or for further information on
any aspect of this device, please contact your
nearest ST Sales Office.

M95256, M95128

16/21

Figure 17. PSDIP8 (BN)

Note: 1. D rawing is not to scale.

PSDIP-a

A2

A1AL

e1

D

E1 E

N

1

C

eA
eB

B1

B

Table 14. PSDIP8 - 8 pin Plastic Skinny DIP, 0.25mm lead frame

Symb.

mm inches

Typ. Min. Max. Typ. Min. Max.

A 3.90 5.90 0.154 0.232

A1 0.49 – 0.019 –

A2 3.30 5.30 0.130 0.209

B 0.36 0.56 0.014 0.022

B1 1.15 1.65 0.045 0.065

C 0.20 0.36 0.008 0.0 14
D 9.20 9.90 0.362 0.3 90

E 7.62 – – 0.300 – –
E1 6.00 6.70 0.236 0.264
e1 2.54 – – 0.100 – –
eA 7.80 – 0.307 –
eB 10.00 0.394

L 3 .00 3.80 0.118 0.150

N8 8

17/21

M95256, M95128

Table 15. SO8 - 8 lead Plastic Small Outline, 150 mils body width

Symb.

mm inches

Typ. Min. Max. Typ. Min. Max.

A 1.35 1.75 0.053 0.069
A1 0.10 0.25 0.004 0.010

B 0.33 0.51 0.013 0.020

C 0.19 0.25 0.007 0.0 10

D 4.80 5.00 0.189 0.1 97

E 3.80 4.00 0.150 0.157

e 1 .27 – – 0.050 – –

H 5.80 6.20 0.228 0.2 44

h 0 .25 0.50 0.010 0.020

L 0 .40 0.90 0.016 0.035

α

0° 8° 0° 8°

N8 8

CP 0.10 0.004

Figure 18. SO8 narrow (MN)

Note: 1. D rawing is not to scale.

SO-a

E

N

CP

B

e

A

D

C

LA1 α

1

H

h x 45˚

M95256, M95128

18/21

Table 16. SO8 - 8 lead Plastic Small Outline, 200 mils body width

Symb.

mm inches

Typ. Min. Max. Typ. Min. Max.

A 2.03 0.080
A1 0.10 0.25 0.004 0.010
A2 1.78 0.070

B 0.35 0.45 0.014 0.018

C 0.20 – – 0.008 – –

D 5.15 5.35 0.203 0.2 11

E 5.20 5.40 0.205 0.213

e 1 .27 – – 0.050 – –

H 7.70 8.10 0.303 0.3 19

L 0 .50 0.80 0.020 0.031

α

0° 10° 0° 10°

N8 8

CP 0.10 0.004

Figure 19. SO8 wide (MW)

Note: 1. D rawing is not to scale.

SO-b

E

N

CP

B

e

A2

D

C

LA1 α

H

A

1

19/21

M95256, M95128

Table 17. TSSOP14 - 14 lead Thin Shrink Small Outline

Symb.

mm inches

Typ. Min. Max. Typ. Min. Max.

A 1.10 0.043
A1 0.05 0.15 0.002 0.006
A2 0.85 0.95 0.033 0.037

B 0.19 0.30 0.007 0.012

C 0.09 0.20 0.004 0.0 08

D 4.90 5.10 0.193 0.1 97

E 6.25 6.50 0.246 0.256
E1 4.30 4.50 0.169 0.177

e 0 .65 – – 0.026 – –

L 0 .50 0.70 0.020 0.028

α

0° 8° 0° 8°

N14 14

CP 0.08 0.003

Figure 20. TSSOP14 (DL)

Note: 1. D rawing is not to scale.

TSSOP

1

N

CP

N/2

DIE

C

L

A1

EE1

D

A2A

α

eB

M95256, M95128

20/21

Table 18. Revision History

Date Description of Revision

17-Nov-1999

New -V voltage range added (including the tables for DC characteristics, AC characteristics, and
ordering information).

07-Feb-2000

New -V voltage range extended to M95256 (including AC characteristics, and ordering

information).
22-Feb-2000 tCLCH and tCHCL, for the M95xxx-V, changed from 1us to 100ns
15-Mar-2000 -V voltage range changed to 2.7-3.6V

21/21

M95256, M95128

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