Page 1
M95128-W M95128-R M95128-DF
SO8 (MN)
150 mil width
TSSOP8 (DW)
169 mil width
WLCSP (CS)
UFDFPN8 (MC)
2 x 3 mm (MLP)
128-Kbit serial SPI bus EEPROM with high-speed clock
Datasheet − production data
Features
■ Compatible with the Serial Peripheral Interface
(SPI) bus
■ Memory array
– 128 Kb (16 Kbytes) of EEPROM
– Page size: 64 bytes
■ Write
– Byte Write within 5 ms
– Page Write within 5 ms
■ Write Protect: quarter, half or whole memory
array
■ High-speed clock: 20 MHz
■ Single supply voltage:
– 2.5 V to 5.5 V for M95128-W
– 1.8 V to 5.5 V for M95128-R
– 1.7 V to 5.5 V for M95128-DF
■ Operating temperature range: from -40°C up to
+85°C
■ Enhanced ESD protection
■ More than 4 million Write cycles
■ More than 200-year data retention
■ Packages
– RoHS compliant and halogen-free
(ECOPACK
®
)
August 2012 Doc ID 5798 Rev 15 1/49
This is information on a product in full production.
www.st.com
1
Page 2
Contents M95128-W M95128-R M95128-DF
Contents
1 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
2 Memory organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
3 Signal description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
3.1 Serial Data Output (Q) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
3.2 Serial Data Input (D) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
3.3 Serial Clock (C) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
3.4 Chip Select (S
3.5 Hold (HOLD
3.6 Write Protect (W
3.7 V
3.8 V
supply voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
CC
ground . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
SS
) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
4 Connecting to the SPI bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
4.1 SPI modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
5 Operating features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
5.1 Supply voltage (VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
5.1.1 Operating supply voltage V
5.1.2 Device reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
5.1.3 Power-up conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
5.1.4 Power-down . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
5.2 Active Power and Standby Power modes . . . . . . . . . . . . . . . . . . . . . . . . . 14
5.3 Hold condition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
CC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
5.4 Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
5.5 Data protection and protocol control . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
6 Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
6.1 Write Enable (WREN) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
6.2 Write Disable (WRDI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
6.3 Read Status Register (RDSR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
6.3.1 WIP bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
2/49 Doc ID 5798 Rev 15
Page 3
M95128-W M95128-R M95128-DF Contents
6.3.2 WEL bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
6.3.3 BP1, BP0 bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
6.3.4 SRWD bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
6.4 Write Status Register (WRSR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
6.5 Read from Memory Array (READ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
6.6 Write to Memory Array (WRITE) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
6.6.1 Cycling with Error Correction Code (ECC) . . . . . . . . . . . . . . . . . . . . . . 25
6.7 Read Identification Page (available only in M95128-D devices) . . . . . . . . 26
6.8 Write Identification Page (available only in M95128-D devices) . . . . . . . . 27
6.9 Read Lock Status (available only in M95128-D devices) . . . . . . . . . . . . . 28
6.10 Lock ID (available only in M95128-D devices) . . . . . . . . . . . . . . . . . . . . . 29
7 Power-up and delivery state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
7.1 Power-up state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
7.2 Initial delivery state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
8 Maximum rating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
9 DC and AC parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
10 Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
11 Part numbering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
12 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
Doc ID 5798 Rev 15 3/49
Page 4
List of tables M95128-W M95128-R M95128-DF
List of tables
Table 1. Signal names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Table 2. Write-protected block size . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Table 3. Instruction set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Table 4. M95128-D instruction set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Table 5. Address range bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Table 6. Status Register format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Table 7. Protection modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Table 8. Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Table 9. Operating conditions (M95128-W, device grade 6) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Table 10. Operating conditions (M95128-R, device grade 6) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Table 11. Operating conditions (M95128-DF, device grade 6) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Table 12. AC measurement conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Table 13. Capacitance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Table 14. Cycling performance by groups of four bytes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Table 15. Memory cell data retention . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Table 16. DC characteristics (M95128-W, device grade 6) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
Table 17. DC characteristics (M95128-R, device grade 6) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
Table 18. DC characteristics (M95128-DF, device grade 6). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
Table 19. AC characteristics (M95128-W, device grade 6) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
Table 20. AC characteristics (M95128-R, M95128-DR device grade 6). . . . . . . . . . . . . . . . . . . . . . . 38
Table 21. AC characteristics (M95128-DF device grade 6) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
Table 22. SO8N – 8-lead plastic small outline, 150 mils body width, mechanical data . . . . . . . . . . . 42
Table 23. UFDFPN8 (MLP8) 8-lead ultra thin fine pitch dual flat package no lead
2 x 3 mm, data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
Table 24. TSSOP8 – 8-lead thin shrink small outline, package mechanical data. . . . . . . . . . . . . . . . 44
Table 25. M95128-DFCS6TP/K, WLCSP 8-bump wafer-level chip scale package mechanical data. 46
Table 26. Ordering information scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
Table 27. Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
4/49 Doc ID 5798 Rev 15
Page 5
M95128-W M95128-R M95128-DF List of figures
List of figures
Figure 1. Logic diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Figure 2. 8-pin package connections (top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Figure 3. WLCSP connections (top view, marking side, with balls on the underside) . . . . . . . . . . . . . 7
Figure 4. Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Figure 5. Bus master and memory devices on the SPI bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Figure 6. SPI modes supported . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Figure 7. Hold condition activation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Figure 8. Write Enable (WREN) sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Figure 9. Write Disable (WRDI) sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Figure 10. Read Status Register (RDSR) sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Figure 11. Write Status Register (WRSR) sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Figure 12. Read from Memory Array (READ) sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Figure 13. Byte Write (WRITE) sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Figure 14. Page Write (WRITE) sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Figure 15. Read Identification Page sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Figure 16. Write identification page sequence. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Figure 17. Write identification page sequence. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Figure 18. Read Lock Status sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Figure 19. Lock ID sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Figure 20. AC measurement I/O waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Figure 21. Serial input timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
Figure 22. Hold timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
Figure 23. Serial output timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
Figure 24. SO8N – 8-lead plastic small outline, 150 mils body width, package outline . . . . . . . . . . . . 42
Figure 25. UFDFPN8 (MLP8) - 8-lead ultra thin fine pitch dual flat no lead, package
outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
Figure 26. TSSOP8 – 8-lead thin shrink small outline, package outline . . . . . . . . . . . . . . . . . . . . . . . 44
Figure 27. M95128-DFCS6TP/K, WLCSP 8-bump wafer-level chip scale package outline . . . . . . . . 45
Doc ID 5798 Rev 15 5/49
Page 6
Description M95128-W M95128-R M95128-DF
AI01789C
S
V
CC
M95xxx
HOLD
V
SS
W
Q
C
D
1 Description
The M95128 devices are Electrically Erasable PROgrammable Memories (EEPROMs)
organized as 16384 x 8 bits, accessed through the SPI bus.
The M95128-W can operate with a supply voltage from 2.5 V to 5.5 V, the M95128-R can
operate with a supply voltage from 1.8 V to 5.5 V, and the M95128-DF can operate with a
supply voltage from 1.7 V to 5.5 V, over an ambient temperature range of -40 °C / +85 °C.
The M95128-DF offers an additional page, named the Identification Page (64 bytes). The
Identification Page can be used to store sensitive application parameters which can be
(later) permanently locked in Read-only mode.
Figure 1. Logic diagram
The SPI bus signals are C, D and Q, as shown in Figure 1 and Tab l e 1 . The device is
selected when Chip Select (S
interrupted when the HOLD
Table 1. Signal names
Signal name Function Direction
C Serial Clock Input
D Serial Data Input Input
Q Serial Data Output Output
S
W
6/49 Doc ID 5798 Rev 15
Hold Input
HOLD
V
CC
V
SS
) is driven low. Communications with the device can be
is driven low.
Chip Select Input
Write Protect Input
Supply voltage
Ground
Page 7
M95128-W M95128-R M95128-DF Description
DV
SS
C
HOLDQ
SV
CC
W
AI01790D
M95xxx
1
2
3
4
8
7
6
5
-36
1
3
7
6
##
#
$
(/,$
6
33
Figure 2. 8-pin package connections (top view)
1. See Section 10: Package mechanical data section for package dimensions, and how to identify pin 1.
Figure 3. WLCSP connections (top view, marking side, with balls on the underside)
Caution: As EEPROM cells lose their charge (and so their binary value) when exposed to ultra violet
(UV) light, EEPROM dice delivered in wafer form or in WLCSP package by
STMicroelectronics must never be exposed to UV light.
Doc ID 5798 Rev 15 7/49
Page 8
Memory organization M95128-W M95128-R M95128-DF
AI01272d
HOLD
S
W
Control logic
High voltage
generator
I/O shift register
Address register
and counter
Data
register
1 page
X decoder
Y decoder
C
D
Q
Size of the
read-only
EEPROM
area
Status
Register
2 Memory organization
The memory is organized as shown in the following figure.
Figure 4. Block diagram
8/49 Doc ID 5798 Rev 15
Page 9
M95128-W M95128-R M95128-DF Signal description
3 Signal description
During all operations, VCC must be held stable and within the specified valid range:
V
(min) to VCC(max).
CC
All of the input and output signals must be held high or low (according to voltages of V
V
, VIL or VOL, as specified in Section 9: DC and AC parameters). These signals are
OH
described next.
3.1 Serial Data Output (Q)
This output signal is used to transfer data serially out of the device. Data is shifted out on the
falling edge of Serial Clock (C).
3.2 Serial Data Input (D)
This input signal is used to transfer data serially into the device. It receives instructions,
addresses, and the data to be written. Values are latched on the rising edge of Serial Clock
(C).
,
IH
3.3 Serial Clock (C)
This input signal provides the timing of the serial interface. Instructions, addresses, or data
present at Serial Data Input (D) are latched on the rising edge of Serial Clock (C). Data on
Serial Data Output (Q) change from the falling edge of Serial Clock (C).
3.4 Chip Select (S)
When this input signal is high, the device is deselected and Serial Data Output (Q) is at high
impedance. The device is in the Standby Power mode, unless an internal Write cycle is in
progress. Driving Chip Select (S
After power-up, a falling edge on Chip Select (S
instruction.
3.5 Hold (HOLD)
The Hold (HOLD) signal is used to pause any serial communications with the device without
deselecting the device.
During the Hold condition, the Serial Data Output (Q) is high impedance, and Serial Data
Input (D) and Serial Clock (C) are Don’t Care.
To start the Hold condition, the device must be selected, with Chip Select (S
) low selects the device, placing it in the Active Power mode.
) is required prior to the start of any
) driven low.
Doc ID 5798 Rev 15 9/49
Page 10
Signal description M95128-W M95128-R M95128-DF
3.6 Write Protect (W)
The main purpose of this input signal is to freeze the size of the area of memory that is
protected against Write instructions (as specified by the values in the BP1 and BP0 bits of
the Status Register).
This pin must be driven either high or low, and must be stable during all Write instructions.
3.7 V
supply voltage
CC
VCC is the supply voltage.
3.8 VSS ground
VSS is the reference for all signals, including the VCC supply voltage.
10/49 Doc ID 5798 Rev 15
Page 11
M95128-W M95128-R M95128-DF Connecting to the SPI bus
AI12836b
SPI Bus Master
SPI Memory
Device
SDO
SDI
SCK
CQD
S
SPI Memory
Device
CQD
S
SPI Memory
Device
CQD
S
CS3 CS2 CS1
SPI Interface with
(CPOL, CPHA) =
(0, 0) or (1, 1)
W
HOLD
W
HOLD
W
HOLD
RR R
V
CC
V
CC
V
CC
V
CC
V
SS
V
SS
V
SS
V
SS
R
4 Connecting to the SPI bus
All instructions, addresses and input data bytes are shifted in to the device, most significant
bit first. The Serial Data Input (D) is sampled on the first rising edge of the Serial Clock (C)
after Chip Select (S
All output data bytes are shifted out of the device, most significant bit first. The Serial Data
Output (Q) is latched on the first falling edge of the Serial Clock (C) after the instruction
(such as the Read from Memory Array and Read Status Register instructions) have been
clocked into the device.
Figure 5. Bus master and memory devices on the SPI bus
) goes low.
1. The Write Protect (W) and Hold (HOLD) signals should be driven, high or low as appropriate.
Figure 5 shows an example of three memory devices connected to an SPI bus master. Only
one memory device is selected at a time, so only one memory device drives the Serial Data
Output (Q) line at a time. The other memory devices are high impedance.
The pull-up resistor R (represented in Figure 5) ensures that a device is not selected if the
Bus Master leaves the S
line in the high impedance state.
In applications where the Bus Master may leave all SPI bus lines in high impedance at the
same time (for example, if the Bus Master is reset during the transmission of an instruction),
the clock line (C) must be connected to an external pull-down resistor so that, if all
inputs/outputs become high impedance, the C line is pulled low (while the S
high): this ensures that S
t
requirement is met. The typical value of R is 100 kΩ..
SHCH
and C do not become high at the same time, and so, that the
Doc ID 5798 Rev 15 11/49
line is pulled
Page 12
Connecting to the SPI bus M95128-W M95128-R M95128-DF
AI01438B
C
MSB
CPHA
D
0
1
CPOL
0
1
Q
C
MSB
4.1 SPI modes
These devices can be driven by a microcontroller with its SPI peripheral running in either of
the following two modes:
● CPOL=0, CPHA=0
● CPOL=1, CPHA=1
For these two modes, input data is latched in on the rising edge of Serial Clock (C), and
output data is available from the falling edge of Serial Clock (C).
The difference between the two modes, as shown in Figure 6, is the clock polarity when the
bus master is in Stand-by mode and not transferring data:
● C remains at 0 for (CPOL=0, CPHA=0)
● C remains at 1 for (CPOL=1, CPHA=1)
Figure 6. SPI modes supported
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5 Operating features
5.1 Supply voltage (VCC)
5.1.1 Operating supply voltage V
Prior to selecting the memory and issuing instructions to it, a valid and stable VCC voltage
within the specified [V
(min), VCC(max)] range must be applied (see Operating conditions
CC
in Section 9: DC and AC parameters). This voltage must remain stable and valid until the
end of the transmission of the instruction and, for a Write instruction, until the completion of
the internal write cycle (t
recommended to decouple the V
10 nF to 100 nF) close to the V
). In order to secure a stable DC supply voltage, it is
W
CC
CC/VSS
5.1.2 Device reset
In order to prevent erroneous instruction decoding and inadvertent Write operations during
power-up, a power-on-reset (POR) circuit is included. At power-up, the device does not
respond to any instruction until VCC reaches the POR threshold voltage. This threshold is
lower than the minimum V
and AC parameters).
At power-up, when V
CC
following state:
● in Standby Power mode,
● deselected,
● Status Register values:
– The Write Enable Latch (WEL) bit is reset to 0.
– The Write In Progress (WIP) bit is reset to 0.
– The SRWD, BP1 and BP0 bits remain unchanged (non-volatile bits).
operating voltage (see Operating conditions in Section 9: DC
CC
passes over the POR threshold, the device is reset and is in the
CC
line with a suitable capacitor (usually of the order of
device pins.
It is important to note that the device must not be accessed until V
stable level within the specified [V
conditions in Section 9: DC and AC parameters.
5.1.3 Power-up conditions
When the power supply is turned on, VCC rises continuously from VSS to VCC. During this
time, the Chip Select (S
therefore recommended to connect the S
Figure 5).
In addition, the Chip Select (S
sensitive as well as level-sensitive: after power-up, the device does not become selected
until a falling edge has first been detected on Chip Select (S
(S
) must have been high, prior to going low to start the first operation.
The V
voltage has to rise continuously from 0 V up to the minimum VCC operating voltage
CC
defined under Operating conditions in Section 9: DC and AC parameters, and the rise time
must not vary faster than 1 V/µs.
) line is not allowed to float but should follow the VCC voltage. It is
reaches a valid and
(min), VCC(max)] range, as defined under Operating
CC
CC
line to VCC via a suitable pull-up resistor (see
) input offers a built-in safety feature, as the S input is edge-
). This ensures that Chip Select
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Operating features M95128-W M95128-R M95128-DF
ai02029E
c
HOLD
Hold
condition
Hold
condition
5.1.4 Power-down
During power-down (continuous decrease of the VCC supply voltage below the minimum
V
operating voltage defined under Operating conditions in Section 9: DC and AC
CC
parameters), the device must be:
● deselected (Chip Select S should be allowed to follow the voltage applied on V
● in Standby Power mode (there should not be any internal write cycle in progress).
CC
),
5.2 Active Power and Standby Power modes
When Chip Select (S) is low, the device is selected, and in the Active Power mode. The
device consumes I
When Chip Select (S
.
CC
) is high, the device is deselected. If a Write cycle is not currently in
progress, the device then goes into the Standby Power mode, and the device consumption
drops to I
, as specified in DC characteristics (see Section 9: DC and AC parameters).
CC1
5.3 Hold condition
The Hold (HOLD) signal is used to pause any serial communications with the device without
resetting the clocking sequence.
To enter the Hold condition, the device must be selected, with Chip Select (S
) low.
During the Hold condition, the Serial Data Output (Q) is high impedance, and the Serial
Data Input (D) and the Serial Clock (C) are Don’t Care.
Normally, the device is kept selected for the whole duration of the Hold condition.
Deselecting the device while it is in the Hold condition has the effect of resetting the state of
the device, and this mechanism can be used if required to reset any processes that had
been in progress.
(a)(b)
Figure 7. Hold condition activation
The Hold condition starts when the Hold (HOLD) signal is driven low when Serial Clock (C)
is already low (as shown in Figure 7).
a. This resets the internal logic, except the WEL and WIP bits of the Status Register.
b. In the specific case where the device has shifted in a Write command (Inst + Address + data bytes, each data
byte being exactly 8 bits), deselecting the device also triggers the Write cycle of this decoded command.
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The Hold condition ends when the Hold (HOLD) signal is driven high when Serial Clock (C)
is already low.
Figure 7 also shows what happens if the rising and falling edges are not timed to coincide
with Serial Clock (C) being low.
5.4 Status Register
The Status Register contains a number of status and control bits that can be read or set (as
appropriate) by specific instructions. See Section 6.3: Read Status Register (RDSR) for a
detailed description of the Status Register bits.
5.5 Data protection and protocol control
The device features the following data protection mechanisms:
● Before accepting the execution of the Write and Write Status Register instructions, the
device checks whether the number of clock pulses comprised in the instructions is a
multiple of eight.
● All instructions that modify data must be preceded by a Write Enable (WREN)
instruction to set the Write Enable Latch (WEL) bit.
● The Block Protect (BP1, BP0) bits in the Status Register are used to configure part of
the memory as read-only.
● The Write Protect (W) signal is used to protect the Block Protect (BP1, BP0) bits in the
Status Register.
For any instruction to be accepted, and executed, Chip Select (S
) must be driven high after
the rising edge of Serial Clock (C) for the last bit of the instruction, and before the next rising
edge of Serial Clock (C).
Two points should be noted in the previous sentence:
● The “last bit of the instruction” can be the eighth bit of the instruction code, or the eighth
bit of a data byte, depending on the instruction (except for Read Status Register
(RDSR) and Read (READ) instructions).
● The “next rising edge of Serial Clock (C)” might (or might not) be the next bus
transaction for some other device on the SPI bus.
Table 2. Write-protected block size
Status Register bits
Protected block Protected array addresses
BP1 BP0
0 0 none none
0 1 Upper quarter 6000h - 7FFFh
1 0 Upper half 4000h - FFh
1 1 Whole memory 0000h - 7FFFh
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Instructions M95128-W M95128-R M95128-DF
6 Instructions
Each instruction starts with a single-byte code, as summarized in Ta b le 3 .
If an invalid instruction is sent (one not contained in Ta bl e 3 ), the device automatically
deselects itself.
Table 3. Instruction set
Instruction Description Instruction format
WREN Write Enable 0000 0110
WRDI Write Disable 0000 0100
RDSR Read Status Register 0000 0101
WRSR Write Status Register 0000 0001
READ Read from Memory Array 0000 0011
WRITE Write to Memory Array 0000 0010
Table 4. M95128-D instruction set
Instruction Description
Instruction
format
WREN Write Enable 0000 0110
WRDI Write Disable 0000 0100
RDSR Read Status Register 0000 0101
WRSR Write Status Register 0000 0001
READ Read from Memory Array 0000 0011
WRITE Write to Memory Array 0000 0010
Read Identification
Page
Write Identification
Page
Reads the page dedicated to identification. 1000 0011
Writes the page dedicated to identification. 1000 0010
Read Lock Status Reads the lock status of the Identification Page. 1000 0011
Lock ID Locks the Identification page in read-only mode. 1000 0010
1. Address bit A10 must be 0, all other address bits are Don't Care.
2. Address bit A10 must be 1, all other address bits are Don't Care.
Table 5. Address range bits
Address significant bits A13-A0
1. Upper MSBs are Don’t Care.
(1)
(1)
(1)
(2)
(2)
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0
Instruction
6.1 Write Enable (WREN)
The Write Enable Latch (WEL) bit must be set prior to each WRITE and WRSR instruction.
The only way to do this is to send a Write Enable instruction to the device.
As shown in Figure 8, to send this instruction to the device, Chip Select (S
) is driven low,
and the bits of the instruction byte are shifted in, on Serial Data Input (D). The device then
enters a wait state. It waits for the device to be deselected, by Chip Select (S
) being driven
high.
Figure 8. Write Enable (WREN) sequence
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Instruction
6.2 Write Disable (WRDI)
One way of resetting the Write Enable Latch (WEL) bit is to send a Write Disable instruction
to the device.
As shown in Figure 9, to send this instruction to the device, Chip Select (S
) is driven low,
and the bits of the instruction byte are shifted in, on Serial Data Input (D).
The device then enters a wait state. It waits for a the device to be deselected, by Chip Select
(S
) being driven high.
The Write Enable Latch (WEL) bit, in fact, becomes reset by any of the following events:
● Power-up
● WRDI instruction execution
● WRSR instruction completion
● WRITE instruction completion.
Figure 9. Write Disable (WRDI) sequence
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S
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Instruction
0
AI02031E
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7 6543210
Status Register Out
High Impedance
MSB
7 6543210
Status Register Out
MSB
7
6.3 Read Status Register (RDSR)
The Read Status Register (RDSR) instruction is used to read the Status Register. The
Status Register may be read at any time, even while a Write or Write Status Register cycle
is in progress. When one of these cycles is in progress, it is recommended to check the
Write In Progress (WIP) bit before sending a new instruction to the device. It is also possible
to read the Status Register continuously, as shown in Figure 10.
Figure 10. Read Status Register (RDSR) sequence
The status and control bits of the Status Register are as follows:
6.3.1 WIP bit
The Write In Progress (WIP) bit indicates whether the memory is busy with a Write or Write
Status Register cycle. When set to 1, such a cycle is in progress, when reset to 0, no such
cycle is in progress.
6.3.2 WEL bit
The Write Enable Latch (WEL) bit indicates the status of the internal Write Enable Latch.
When set to 1, the internal Write Enable Latch is set. When set to 0, the internal Write
Enable Latch is reset, and no Write or Write Status Register instruction is accepted.
The WEL bit is returned to its reset state by the following events:
● Power-up
● Write Disable (WRDI) instruction completion
● Write Status Register (WRSR) instruction completion
● Write (WRITE) instruction completion
6.3.3 BP1, BP0 bits
The Block Protect (BP1, BP0) bits are non volatile. They define the size of the area to be
software-protected against Write instructions. These bits are written with the Write Status
Register (WRSR) instruction. When one or both of the Block Protect (BP1, BP0) bits is set
to 1, the relevant memory area (as defined in Ta bl e 2 ) becomes protected against Write
(WRITE) instructions. The Block Protect (BP1, BP0) bits can be written provided that the
Hardware Protected mode has not been set.
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High Impedance
Instruction Status
Register In
0
765432 0
1
MSB
6.3.4 SRWD bit
The Status Register Write Disable (SRWD) bit is operated in conjunction with the Write
Protect (W
signal enable the device to be put in the Hardware Protected mode (when the Status
Register Write Disable (SRWD) bit is set to 1, and Write Protect (W
mode, the non-volatile bits of the Status Register (SRWD, BP1, BP0) become read-only bits
and the Write Status Register (WRSR) instruction is no longer accepted for execution.
Table 6. Status Register format
Status Register Write Protect
) signal. The Status Register Write Disable (SRWD) bit and Write Protect (W)
) is driven low). In this
b7 b0
SRWD 0 0 0 BP1 BP0 WEL WIP
Block Protect bits
Write Enable Latch bit
Write In Progress bit
6.4 Write Status Register (WRSR)
The Write Status Register (WRSR) instruction is used to write new values to the Status
Register. Before it can be accepted, a Write Enable (WREN) instruction must have been
previously executed.
The Write Status Register (WRSR) instruction is entered by driving Chip Select (S
followed by the instruction code, the data byte on Serial Data input (D) and Chip Select (S
driven high. Chip Select (S
latches in the eighth bit of the data byte, and before the next rising edge of Serial Clock (C).
Otherwise, the Write Status Register (WRSR) instruction is not executed.
The instruction sequence is shown in Figure 11.
Figure 11. Write Status Register (WRSR) sequence
) must be driven high after the rising edge of Serial Clock (C) that
) low,
)
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Driving the Chip Select (S) signal high at a byte boundary of the input data triggers the selftimed Write cycle that takes t
to complete (as specified in AC tables under Section 9: DC
W
and AC parameters).
While the Write Status Register cycle is in progress, the Status Register may still be read to
check the value of the Write in progress (WIP) bit: the WIP bit is 1 during the self-timed
Write cycle t
also reset at the end of the Write cycle t
, and 0 when the Write cycle is complete. The WEL bit (Write Enable Latch) is
W
.
W
The Write Status Register (WRSR) instruction enables the user to change the values of the
BP1, BP0 and SRWD bits:
● The Block Protect (BP1, BP0) bits define the size of the area that is to be treated as
read-only, as defined in Ta bl e 2 .
● The SRWD (Status Register Write Disable) bit, in accordance with the signal read on
the Write Protect pin (W
), enables the user to set or reset the Write protection mode of
the Status Register itself, as defined in Tab l e 7 . When in Write-protected mode, the
Write Status Register (WRSR) instruction is not executed.
The contents of the SRWD and BP1, BP0 bits are updated after the completion of the
WRSR instruction, including the t
Write cycle.
W
The Write Status Register (WRSR) instruction has no effect on the b6, b5, b4, b1, b0 bits in
the Status Register. Bits b6, b5, b4 are always read as 0.
Table 7. Protection modes
W
SRWD
signal
10
00
11
01
1. As defined by the values in the Block Protect (BP1, BP0) bits of the Status Register. See Table 2.
bit
Mode
Softwareprotected
(SPM)
Hardware-
protected
(HPM)
Write protection of the
Status Register
Status Register is
writable (if the WREN
instruction has set the
WEL bit).
The values in the BP1
and BP0 bits can be
changed.
Status Register is
Hardware writeprotected.
The values in the BP1
and BP0 bits cannot be
changed.
Protected area
Write-protected
Write-protected
Memory content
(1)
Unprotected area
Ready to accept
Write instructions
Ready to accept
Write instructions
The protection features of the device are summarized in Tab l e 7 .
When the Status Register Write Disable (SRWD) bit in the Status Register is 0 (its initial
delivery state), it is possible to write to the Status Register (provided that the WEL bit has
previously been set by a WREN instruction), regardless of the logic level applied on the
Write Protect (W
) input pin.
(1)
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1413 3210
28 29 30
76543 1 7
0
High Impedance
Data Out 1
Instruction 16-Bit Address
0
MSB
MSB
2
31
Data Out 2
When the Status Register Write Disable (SRWD) bit in the Status Register is set to 1, two
cases should be considered, depending on the state of the Write Protect (W
● If Write Protect (W) is driven high, it is possible to write to the Status Register (provided
) input pin:
that the WEL bit has previously been set by a WREN instruction).
● If Write Protect (W) is driven low, it is not possible to write to the Status Register even if
the WEL bit has previously been set by a WREN instruction. (Attempts to write to the
Status Register are rejected, and are not accepted for execution). As a consequence,
all the data bytes in the memory area, which are Software-protected (SPM) by the
Block Protect (BP1, BP0) bits in the Status Register, are also hardware-protected
against data modification.
Regardless of the order of the two events, the Hardware-protected mode (HPM) can be
entered by:
● either setting the SRWD bit after driving the Write Protect (W) input pin low,
● or driving the Write Protect (W) input pin low after setting the SRWD bit.
Once the Hardware-protected mode (HPM) has been entered, the only way of exiting it is to
pull high the Write Protect (W
) input pin.
If the Write Protect (W
) input pin is permanently tied high, the Hardware-protected mode
(HPM) can never be activated, and only the Software-protected mode (SPM), using the
Block Protect (BP1, BP0) bits in the Status Register, can be used.
6.5 Read from Memory Array (READ)
As shown in Figure 12, to send this instruction to the device, Chip Select (S) is first driven
low. The bits of the instruction byte and address bytes are then shifted in, on Serial Data
Input (D). The address is loaded into an internal address register, and the byte of data at
that address is shifted out, on Serial Data Output (Q).
Figure 12. Read from Memory Array (READ) sequence
1. Depending on the memory size, as shown in Table 5, the most significant address bits are Don’t Care.
If Chip Select (S) continues to be driven low, the internal address register is incremented
automatically, and the byte of data at the new address is shifted out.
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High Impedance
Instruction 16-Bit Address
0
765432 0
1
Data Byte
31
When the highest address is reached, the address counter rolls over to zero, allowing the
Read cycle to be continued indefinitely. The whole memory can, therefore, be read with a
single READ instruction.
The Read cycle is terminated by driving Chip Select (S
Select (S
) signal can occur at any time during the cycle.
The instruction is not accepted, and is not executed, if a Write cycle is currently in progress.
6.6 Write to Memory Array (WRITE)
As shown in Figure 13, to send this instruction to the device, Chip Select (S) is first driven
low. The bits of the instruction byte, address byte, and at least one data byte are then shifted
in, on Serial Data Input (D).
The instruction is terminated by driving Chip Select (S
data. The self-timed Write cycle, triggered by the Chip Select (S
period t
end of which the Write in Progress (WIP) bit is reset to 0.
Figure 13. Byte Write (WRITE) sequence
(as specified in AC characteristics in Section 9: DC and AC parameters), at the
W
) high. The rising edge of the Chip
) high at a byte boundary of the input
) rising edge, continues for a
1. Depending on the memory size, as shown in Table 5, the most significant address bits are Don’t Care.
In the case of Figure 13, Chip Select (S) is driven high after the eighth bit of the data byte
has been latched in, indicating that the instruction is being used to write a single byte.
However, if Chip Select (S
) continues to be driven low, as shown in Figure 14, the next byte
of input data is shifted in, so that more than a single byte, starting from the given address
towards the end of the same page, can be written in a single internal Write cycle.
Each time a new data byte is shifted in, the least significant bits of the internal address
counter are incremented. If more bytes are sent than will fit up to the end of the page, a
condition known as “roll-over” occurs. In case of roll-over, the bytes exceeding the page size
are overwritten from location 0 of the same page.
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3433 35 36 37 38 39 40 41 42 44 45 46 4732
C
D
S
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Instruction 16-Bit Address
0
765432 0
1
Data Byte 1
31
43
765432 0
1
Data Byte 2
765432 0
1
Data Byte 3
65432 0
1
Data Byte N
The instruction is not accepted, and is not executed, under the following conditions:
● if the Write Enable Latch (WEL) bit has not been set to 1 (by executing a Write Enable
instruction just before),
● if a Write cycle is already in progress,
● if the device has not been deselected, by driving high Chip Select (S), at a byte
boundary (after the eighth bit, b0, of the last data byte that has been latched in),
● if the addressed page is in the region protected by the Block Protect (BP1 and BP0)
bits.
Note: The self-timed write cycle t
is internally executed as a sequence of two consecutive
W
events: [Erase addressed byte(s)], followed by [Program addressed byte(s)]. An erased bit is
read as “0” and a programmed bit is read as “1”.
Figure 14. Page Write (WRITE) sequence
1. Depending on the memory size, as shown in Table 5, the most significant address bits are Don’t Care.
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6.6.1 Cycling with Error Correction Code (ECC)
M95128 and M95128-D devices offer an Error Correction Code (ECC) logic. The ECC is an
internal logic function which is transparent for the SPI communication protocol.
The ECC logic is implemented on each group of four EEPROM bytes
single bit out of the four bytes happens to be erroneous during a Read operation, the ECC
detects this bit and replaces it with the correct value. The read reliability is therefore much
improved.
Even if the ECC function is performed on groups of four bytes, a single byte can be
written/cycled independently. In this case, the ECC function also writes/cycles the three
other bytes located in the same group
(c)
. As a consequence, the maximum cycling budget is
defined at group level and the cycling can be distributed over the four bytes of the group: the
sum of the cycles seen by byte0, byte1, byte2 and byte3 of the same group must remain
below the maximum value defined in Tab le 1 4 .
(c)
. Inside a group, if a
c. A group of four bytes is located at addresses [4*N, 4*N+1, 4*N+2, 4*N+3], where N is an integer.
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$
!I
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1
(IGHIMPEDANCE
$ATA/UT
)NSTRUCTION BITADDRESS
-3"
-3"
$ATA/UT
6.7 Read Identification Page (available only in M95128-D devices)
The Identification Page (64 bytes) is an additional page which can be written and (later)
permanently locked in Read-only mode.
Reading this page is achieved with the Read Identification Page instruction (see Ta bl e 4 ).
The Chip Select signal (S
bytes are then shifted in, on Serial Data Input (D). Address bit A10 must be 0, upper
address bits are Don't Care, and the data byte pointed to by the lower address bits [A5:A0]
is shifted out on Serial Data Output (Q). If Chip Select (S
internal address register is automatically incremented, and the byte of data at the new
address is shifted out.
The number of bytes to read in the ID page must not exceed the page boundary, otherwise
unexpected data is read (e.g.: when reading the ID page from location 24d, the number of
bytes should be less than or equal to 40d, as the ID page boundary is 64 bytes).
) is first driven low, the bits of the instruction byte and address
) continues to be driven low, the
The read cycle is terminated by driving Chip Select (S
Select (S
) signal can occur at any time during the cycle. The first byte addressed can be any
byte within any page.
The instruction is not accepted, and is not executed, if a write cycle is currently in progress.
Figure 15. Read Identification Page sequence
) high. The rising edge of the Chip
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#
$
!I
3
1
(IGHIMPEDANCE
)NSTRUCTION BITADDRESS
$ATABYTE
6.8 Write Identification Page (available only in M95128-D devices)
The Identification Page (64 bytes) is an additional page which can be written and (later)
permanently locked in Read-only mode.
Writing this page is achieved with the Write Identification Page instruction (see Ta b le 4 ). The
Chip Select signal (S
at least one data byte are then shifted in on Serial Data Input (D). Address bit A10 must be
0, upper address bits are Don't Care, the lower address bits [A5:A0] address bits define the
byte address inside the identification page. The instruction sequence is shown in Figure 17.
Figure 16. Write identification page sequence
) is first driven low. The bits of the instruction byte, address bytes, and
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#
$
!I
3
1
(IGHIMPEDANCE
$ATA/UT
)NSTRUCTION BITADDRESS
-3"
-3"
$ATA/UT
6.9 Read Lock Status (available only in M95128-D devices)
The Read Lock Status instruction (see Ta bl e 4 ) is used to check whether the Identification
Page is locked or not in Read-only mode. The Read Lock Status sequence is defined with
the Chip Select (S
then shifted in on Serial Data Input (D). Address bit A10 must be 1, all other address bits are
Don't Care. The Lock bit is the LSB (least significant bit) of the byte read on Serial Data
Output (Q). It is at “1” when the lock is active and at “0” when the lock is not active. If Chip
Select (S
) continues to be driven low, the same data byte is shifted out. The read cycle is
terminated by driving Chip Select (S
The instruction sequence is shown in Figure 18.
Figure 18. Read Lock Status sequence
) first driven low. The bits of the instruction byte and address bytes are
) high.
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6.10 Lock ID (available only in M95128-D devices)
The Lock ID instruction permanently locks the Identification Page in read-only mode. Before
this instruction can be accepted, a Write Enable (WREN) instruction must have been
executed.
The Lock ID instruction is issued by driving Chip Select (S
code, the address and a data byte on Serial Data Input (D), and driving Chip Select (S
) low, sending the instruction
) high.
In the address sent, A10 must be equal to 1, all other address bits are Don't Care. The data
byte sent must be equal to the binary value xxxx xx1x, where x = Don't Care.
Chip Select (S
) must be driven high after the rising edge of Serial Clock (C) that latches in
the eighth bit of the data byte, and before the next rising edge of Serial Clock (C). Otherwise,
the Lock ID instruction is not executed.
Driving Chip Select (S
cycle whose duration is t
) high at a byte boundary of the input data triggers the self-timed write
(as specified in AC characteristics in Section 9: DC and AC
W
parameters). The instruction sequence is shown in Figure 19.
The instruction is discarded, and is not executed, under the following conditions:
● If a Write cycle is already in progress,
● If the Block Protect bits (BP1,BP0) = (1,1),
● If a rising edge on Chip Select (S) happens outside of a byte boundary.
Figure 19. Lock ID sequence
3
#
)NSTRUCTION BITADDRESS
$ATABYTE
$
(IGHIMPEDANCE
1
!I
Doc ID 5798 Rev 15 29/49
Page 30
Power-up and delivery state M95128-W M95128-R M95128-DF
7 Power-up and delivery state
7.1 Power-up state
After power-up, the device is in the following state:
● Standby power mode,
● deselected (after power-up, a falling edge is required on Chip Select (S) before any
instructions can be started),
● not in the Hold condition,
● the Write Enable Latch (WEL) is reset to 0,
● Write In Progress (WIP) is reset to 0.
The SRWD, BP1 and BP0 bits of the Status Register are unchanged from the previous
power-down (they are non-volatile bits).
7.2 Initial delivery state
The device is delivered with the memory array set to all 1s (each byte = FFh). The Status
Register Write Disable (SRWD) and Block Protect (BP1 and BP0) bits are initialized to 0.
30/49 Doc ID 5798 Rev 15
Page 31
M95128-W M95128-R M95128-DF Maximum rating
8 Maximum rating
Stressing the device outside the ratings listed in Ta bl e 8 may cause permanent damage to
the device. These are stress ratings only, and operation of the device at these, or any other
conditions outside those indicated in the operating sections of this specification, is not
implied. Exposure to absolute maximum rating conditions for extended periods may affect
device reliability.
Table 8. Absolute maximum ratings
Symbol Parameter Min. Max. Unit
Ambient operating temperature –40 130 °C
T
STG
T
LEAD
V
V
V
I
OL
I
OH
V
ESD
1. Compliant with JEDEC Std J-STD-020 (for small body, Sn-Pb or Pb assembly), with the ST ECOPACK®
7191395 specification, and with the European directive on Restrictions on Hazardous Substances (RoHS)
2002/95/EU.
2. Positive and negative pulses applied on different combinations of pin connections, according to AEC-
Q100-002 (compliant with JEDEC Std JESD22-A114, C1=100 pF, R1=1500 Ω, R2=500 Ω).
O
CC
Storage temperature –65 150 °C
Lead temperature during soldering See note
Output voltage –0.50 VCC+0.6 V
Input voltage –0.50 6.5 V
I
Supply voltage –0.50 6.5 V
DC output current (Q = 0) 5 mA
DC output current (Q = 1) 5 mA
Electrostatic discharge voltage (human body model)
(2)
4000 V
(1)
°C
Doc ID 5798 Rev 15 31/49
Page 32
DC and AC parameters M95128-W M95128-R M95128-DF
!)#
6
##
6
##
6
##
6
##
)NPUTANDOUTPUT
TIMINGREFERENCELEVELS
)NPUTVOLTAGELEVELS
9 DC and AC parameters
This section summarizes the operating conditions and the DC/AC characteristics of the
device.
Table 9. Operating conditions (M95128-W, device grade 6)
Symbol Parameter Min. Max. Unit
V
T
Table 10. Operating conditions (M95128-R, device grade 6)
Supply voltage 2.5 5.5 V
CC
Ambient operating temperature –40 85 °C
A
Symbol Parameter Min. Max. Unit
V
CC
T
A
Supply voltage 1.8 5.5 V
Ambient operating temperature –40 85 °C
Table 11. Operating conditions (M95128-DF, device grade 6)
Symbol Parameter Min. Max. Unit
V
T
Table 12. AC measurement conditions
Symbol Parameter Min. Max. Unit
1. See AC tables 19, 20 and 21.
Supply voltage 1.7 5.5 V
CC
Ambient operating temperature –40 85 °C
A
C
Load capacitance
L
Input rise and fall times 50 ns
Input pulse voltages 0.2 V
Input and output timing reference voltages 0.3 V
to 0.8 V
CC
to 0.7 V
CC
30 or
100
(1)
CC
CC
pF
V
V
Figure 20. AC measurement I/O waveform
32/49 Doc ID 5798 Rev 15
Page 33
M95128-W M95128-R M95128-DF DC and AC parameters
Table 13. Capacitance
Symbol Parameter Test conditions
(1)
Min. Max. Unit
C
OUT
Output capacitance (Q) V
= 0 V 8 pF
OUT
Input capacitance (D) VIN = 0 V 8 pF
C
IN
Input capacitance (other pins) V
1. Sampled only, not 100% tested, at TA = 25 °C and a frequency of 5 MHz.
Table 14. Cycling performance by groups of four bytes
Symbol Parameter
(1)
Test conditions Min. Max. Unit
TA ≤ 25 °C,
Ncycle Write cycle endurance
(2)
(min) < VCC < VCC(max)
V
CC
TA = 85 °C,
(min) < VCC < VCC(max)
V
CC
1. Cycling performance for products identified by process letter K.
2. The Write cycle endurance is defined for groups of four data bytes located at addresses [4*N, 4*N+1,
4*N+2, 4*N+3] where N is an integer. The Write cycle endurance is defined by characterization and
qualification.
3. A Write cycle is executed when either a Page Write, a Byte Write, a WRSR, a WRID or an LID instruction is
decoded. When using the Byte Write, the Page Write or the WRID instruction, refer also to Section 6.6.1:
Cycling with Error Correction Code (ECC).
Table 15. Memory cell data retention
= 0 V 6 pF
IN
4,000,000
Write cycle
1,200,000
Parameter Test conditions Min. Unit
Data retention
1. For products identified by process letter K. The data retention behavior is checked in production. The 200-
year limit is defined from characterization and qualification results.
(1)
TA = 55 °C 200 Year
(3)
Doc ID 5798 Rev 15 33/49
Page 34
DC and AC parameters M95128-W M95128-R M95128-DF
Table 16. DC characteristics (M95128-W, device grade 6)
Symbol Parameter Test conditions Min. Max. Unit
Input leakage
I
I
I
LO
I
CC
CC0
I
CC1
V
V
V
LI
current
Output leakage
current
Supply current
(Read)
Supply current
(3)
(Write)
Supply current
(Standby)
Input low voltage –0.45 0.3 V
IL
Input high voltage 0.7 VCCVCC+1 V
IH
Output low voltage
OL
= VSS or V
V
IN
= VCC, V
S
= 2.5 V, C = 0.1 VCC/0.9 V
V
CC
CC
OUT
= VSS or V
CC
at 5 MHz, Q = open
V
= 2.5 V, C = 0.1 VCC/0.9 V
CC
at 10 MHz, Q = open
VCC= 5.5 V, C = 0.1 VCC/0.9 V
at 5 MHz, Q = open
VCC= 5.5 V, C = 0.1 VCC/0.9 V
at 20 MHz, Q = open
During tW, S = VCC,
2.5 V < V
= VCC, VCC = 5.5 V,
S
V
= VSS or VCC,
IN
= VCC, VCC = 2.5 V,
S
V
= VSS or VCC,
IN
= 2.5 V and IOL = 1.5 mA or
V
CC
< 5.5 V
CC
VCC = 5 V and IOL = 2 mA
CC
CC
CC
CC
± 2 µA
± 2 µA
(1)
3
(2)
2
mA
(1)
5
(2)
5
mA
(4)
3
µA
(4)
2
CC
0.4 V
V
V
= 2.5 V and IOH = –0.4 mA or
V
1. For previous products identified with process letter A.
2. For the M95128 devices identified by process letter K.
3. Characterized only, not tested in production.
4. 5 µA for previous M95128 devices identified by process letter A.
Output high voltage
OH
CC
VCC = 5 V and IOH = –2 mA
0.8 V
CC
V
34/49 Doc ID 5798 Rev 15
Page 35
M95128-W M95128-R M95128-DF DC and AC parameters
Table 17. DC characteristics (M95128-R, device grade 6)
Symbol Parameter Test conditions
I
LI
I
LO
I
CC
I
CC0
I
CC1
V
IL
V
IH
V
OL
V
OH
1. If the application uses the M95128-R device at 2.5 V ≤ VCC ≤ 5.5 V and –40 °C ≤ TA ≤ +85 °C, please refer to Table 16: DC
characteristics (M95128-W, device grade 6), rather than to the above table.
2. Value tested only for previous M95128 devices identified by process letter A.
3. Only the M95128 devices identified by process letter K.
4. Characterized only, not tested in production.
5. 3 µA for previous M95128 devices identified by process letter A.
Input leakage
current
Output leakage
current
Supply current
(Read)
= VSS or V
V
IN
= VCC, voltage applied on Q = V
S
V
= 1.8V, C = 0.1V
CC
CC
or 0.9 VCC,
CC
at 2 MHz, Q = open
= 1.8V, C = 0.1V
V
CC
or 0.9 VCC,
CC
(1)
SS
or V
CC
Min. Max. Unit
at 5 MHz, Q = open
Supply current
(4)
(Write)
Supply current
(Standby)
Input low voltage 1.8 V ≤ V
Input high voltage 1.8 V ≤ V
V
= 1.8 V, during tW, S = V
CC
= 1.8 V, S = VCC, V
V
CC
< 2.5 V –0.45 0.25 V
CC
< 2.5 V 0.75 V
CC
CC
= VSS or V
IN
CC
CC
Output low voltage IOL = 0.15 mA, VCC = 1.8 V 0.3 V
Output high voltage IOH = –0.1 mA, VCC = 1.8 V 0.8 V
CC
± 2 µA
± 2 µA
(2)
1
(3)
2
3mA
(5)
1
CC
VCC+1 V
mA
µA
V
V
Doc ID 5798 Rev 15 35/49
Page 36
DC and AC parameters M95128-W M95128-R M95128-DF
Table 18. DC characteristics (M95128-DF, device grade 6)
Symbol Parameter Test conditions
I
LI
I
LO
I
CC
I
CC0
I
CC1
V
IL
V
IH
V
OL
V
OH
1. If the application uses the M95128-DF devices at 2.5 V ≤ VCC ≤ 5.5 V and –40 °C ≤ TA ≤ +85 °C, please refer to Table 16: DC
characteristics (M95128-W, device grade 6), rather than to the above table.
2. Characterized only, not tested in production.
Input leakage
current
Output leakage
current
Supply current
(Read)
Supply current
(2)
(Write)
Supply current
(Standby)
Input low voltage 1.7 V ≤ V
Input high voltage 1.7 V ≤ V
= VSS or V
V
IN
= VCC, voltage applied on Q = V
S
= 1.7V, C = 0.1V
V
CC
CC
or 0.9 VCC,
CC
at 5 MHz, Q = open
V
= 1.7 V, during tW, S = V
CC
= 1.7 V, S = VCC, V
V
CC
< 2.5 V –0.45 0.25 V
CC
< 2.5 V 0.75 V
CC
CC
= VSS or V
IN
(1)
SS
or V
CC
CC
Min. Max. Unit
CC
Output low voltage IOL = 0.15 mA, VCC = 1.7 V 0.3 V
Output high voltage IOH = –0.1 mA, VCC = 1.7 V 0.8 V
CC
± 2 µA
± 2 µA
2mA
3mA
1µA
CC
VCC+1 V
V
V
36/49 Doc ID 5798 Rev 15
Page 37
M95128-W M95128-R M95128-DF DC and AC parameters
Table 19. AC characteristics (M95128-W, device grade 6)
(1)
New products
CL ≤ 30 pF
V
≥ 2.5V Vcc ≥ 4.5V
cc
Test conditions specified in
Tabl e 9 and Ta b l e 1 2
Previous
and new
products
CL ≤ 100 pF
Symbol Alt. Parameter Min. Max. Min. Max. Min. Max.
(2)
Unit
f
C
t
SLCH
t
SHCH
t
SHSL
t
CHSH tCSH
t
CHSL
t
CH
t
CL
t
CLCH
t
CHCL
t
DVC H
t
CHDX
t
HHCH
t
HLCH
t
CLHL
t
CLHH
t
SHQZ
t
CLQV
t
CLQX
t
QLQH
t
QHQL
t
HHQV
t
HLQZ
t
W
1. Previous products are identified by process letters A.
2. New products are M95128 devices identified by process letter K.
3. tCH + tCL must never be less than the shortest possible clock period, 1 / fC(max).
4. Characterized only, not tested in production.
(3)
(3)
(3)
(3)
(4)
(4)
(4)
(4)
f
Clock frequency D.C. 5 D.C. 10 D.C. 20 MHz
SCK
t
S active setup time 90 30 15 ns
CSS1
t
S not active setup time 90 30 15 ns
CSS2
t
S deselect time 100 40 20 ns
CS
S active hold time 90 30 15 ns
S not active hold time 90 30 15 ns
t
Clock high time 90 40 20 ns
CLH
t
Clock low time 90 40 20 ns
CLL
t
Clock rise time 1 2 2 µs
RC
t
Clock fall time 1 2 2 µs
FC
t
Data in setup time 20 10 5 ns
DSU
t
Data in hold time 30 10 10 ns
DH
Clock low hold time after
HOLD not active
Clock low hold time after
HOLD active
Clock low setup time
before HOLD active
Clock low setup time
before HOLD not active
t
Output disable time 100 40 20 ns
DIS
t
Clock low to output valid 60 40 20 ns
V
t
Output hold time 0 0 0 ns
HO
t
Output rise time 50 20 10 ns
RO
t
Output fall time 50 20 10 ns
FO
HOLD high to output
t
LZ
valid
HOLD low to output
t
HZ
High-Z
t
Write time 5 5 5 ms
WC
70 30 15 ns
40 30 15 ns
000ns
000ns
50 40 20 ns
100 40 20 ns
Doc ID 5798 Rev 15 37/49
Page 38
DC and AC parameters M95128-W M95128-R M95128-DF
Table 20. AC characteristics (M95128-R, M95128-DR device grade 6)
Test conditions specified in Tab l e 1 0 and Ta b l e 1 2
New products
Symbol Alt. Parameter
Previous
products
C
≤ 100 pF
L
(1)
VCC ≥ 1.8V
C
≤ 100 pF
L
Min. Max. Min. Max. Min. Max. Min. Max.
f
f
C
t
SLCHtCSS1
t
SHCHtCSS2
t
SHSLtCS
t
CHSHtCSH
t
CHSL
(3)
t
CH
(3)
t
CL
(4)
t
CLCH
(4)
t
CHCL
t
DVC HtDSU
t
CHDXtDH
t
HHCH
t
HLCH
Clock frequency 2 5 10 20 MHz
SCK
S active setup time 200 60 30 15 ns
S not active setup time 200 60 30 15 ns
S deselect time 200 90 40 20 ns
S active hold time 200 60 30 15 ns
S not active hold time 200 60 30 15 ns
t
Clock high time 200 80 40 20 ns
CLH
t
Clock low time 200 80 40 20 ns
CLL
t
Clock rise time 1 2 2 2 µs
RC
tFCClock fall time 1 2 2 2 µs
Data in setup time 40 20 10 5 ns
Data in hold time 50 20 10 10 ns
Clock low hold time after HOLD
not active
Clock low hold time after HOLD
active
140 60 30 15 ns
90 60 30 15 ns
V
CC
C
L
≥ 2.5V
≤ 30 pF
(2)
V
CC
C
≥ 4.5V
≤ 30 pF
L
Unit
t
CLHL
t
CLHH
(4)
t
SHQZ
t
CLQV
t
CLQXtHO
(4)
t
QLQH
(4)
t
QHQL
t
HHQVtLZ
(4)
t
HLQZ
t
W
1. Previous products are identified by process letters A.
2. New products are the M95256 devices identified by process letter K.
+ tCL must never be less than the shortest possible clock period, 1 / fC(max).
3. t
CH
4. Characterized only, not tested in production.
Clock low setup time before HOLD
active
Clock low setup time before HOLD
not active
t
Output disable time 250 80 40 20 ns
DIS
0000ns
0000ns
tVClock low to output valid 150 80 40 20 ns
Output hold time 0 0 0 0 ns
t
Output rise time 100 20 20 10 ns
RO
tFOOutput fall time 100 20 20 10 ns
HOLD high to output valid 100 80 40 20 ns
tHZHOLD low to output High-Z 250 80 40 20 ns
t
Write time 5 5 5 5 ms
WC
38/49 Doc ID 5798 Rev 15
Page 39
M95128-W M95128-R M95128-DF DC and AC parameters
Table 21. AC characteristics (M95128-DF device grade 6)
Test conditions specified in Tab l e 1 0 and Ta b l e 1 2
Parameter
f
C
t
SLCHtCSS1
t
SHCHtCSS2
t
SHSL
t
CHSHtCSH
t
CHSL
t
CH
t
CL
t
CLCH
t
CHCL
t
DVC H
t
CHDX
t
HHCH
t
HLCH
t
CLHL
t
CLHH
t
SHQZ
t
CLQV
t
CLQX
t
QLQH
t
QHQL
t
HHQV
t
HLQZ
t
W
1. Preliminary data.
2. t
CH
3. Characterized only, not tested in production.
f
Clock frequency 5 10 20 MHz
SCK
S active setup time 60 30 15 ns
S not active setup time 60 30 15 ns
t
S deselect time 90 40 20 ns
CS
S active hold time 60 30 15 ns
S not active hold time 60 30 15 ns
(2)
t
Clock high time 80 40 20 ns
CLH
(3)
t
Clock low time 80 40 20 ns
CLL
(3)
t
Clock rise time 2 2 2 µs
RC
(4)
t
Clock fall time 2 2 2 µs
FC
t
Data in setup time 20 10 5 ns
DSU
t
Data in hold time 20 10 10 ns
DH
Clock low hold time after HOLD not active 60 30 15 ns
Clock low hold time after HOLD active 60 30 15 ns
Clock low setup time before HOLD active 0 0 0 ns
Clock low setup time before HOLD not active 0 0 0 ns
(4)
t
Output disable time 80 40 20 ns
DIS
tVClock low to output valid 80 40 20 ns
t
Output hold time 0 0 0 ns
HO
(4)
t
Output rise time 20 20 10 ns
RO
(4)
t
Output fall time 20 20 10 ns
FO
t
HOLD high to output valid 80 40 20 ns
LZ
(4)
t
HOLD low to output High-Z 80 40 20 ns
HZ
t
Write time 5 5 5 ms
WC
+ tCL must never be less than the shortest possible clock period, 1 / fC(max).
(1)
V
≥ 1.7 V
CC
C
≤ 100 pF
L
V
CC
C
≥ 2.5 V
≤ 30 pF
L
V
CC
C
≥ 4.5 V
≤ 30 pF
L
Min. Max. Min. Max. Min. Max.
Unit
Doc ID 5798 Rev 15 39/49
Page 40
DC and AC parameters M95128-W M95128-R M95128-DF
C
Q
AI01448c
S
HOLD
tCLHL
tHLCH
tHHCH
tCLHH
tHHQVtHLQZ
Figure 21. Serial input timing
tSHSL
S
tSLCH
C
tDVCH
tCHCL
tCHDX
tCH
tCL
tCHSHtCHSL
tCLCH
tSHCH
D
Q
High impedance
Figure 22. Hold timing
MSB IN
LSB IN
AI01447d
40/49 Doc ID 5798 Rev 15
Page 41
M95128-W M95128-R M95128-DF DC and AC parameters
C
Q
AI01449f
S
D
ADDR
LSB IN
tSHQZ
tCH
tCL
tQLQH
tQHQL
tCHCL
tCLQX
tCLQV
tSHSL
tCLCH
Figure 23. Serial output timing
Doc ID 5798 Rev 15 41/49
Page 42
Package mechanical data M95128-W M95128-R M95128-DF
SO-A
E1
8
ccc
b
e
A
D
c
1
E
h x 45˚
A2
k
0.25 mm
L
L1
A1
GAUGE PLANE
10 Package mechanical data
In order to meet environmental requirements, ST offers these devices in different grades of
ECOPACK
specifications, grade definitions and product status are available at: www.st.com.
ECOPACK
®
packages, depending on their level of environmental compliance. ECOPACK®
®
is an ST trademark.
Figure 24. SO8N – 8-lead plastic small outline, 150 mils body width, package outline
1. Drawing is not to scale.
Table 22. SO8N – 8-lead plastic small outline, 150 mils body width, mechanical data
millimeters inches
Symbol
Typ Min Max Typ Min Max
(1)
A 1.750 0.0689
A1 0.100 0.250 0.0039 0.0098
A2 1.250 0.0492
b 0.280 0.480 0.0110 0.0189
c 0.170 0.230 0.0067 0.0091
ccc 0.100 0.0039
D 4.900 4.800 5.000 0.1929 0.1890 0.1969
E 6.000 5.800 6.200 0.2362 0.2283 0.2441
E1 3.900 3.800 4.000 0.1535 0.1496 0.1575
e 1.270 - - 0.0500 - -
h 0.250 0.500 0.0098 0.0197
k 0°8° 0°8°
L 0.400 1.270 0.0157 0.0500
L1 1.040 0.0409
1. Values in inches are converted from mm and rounded to four decimal digits.
42/49 Doc ID 5798 Rev 15
Page 43
M95128-W M95128-R M95128-DF Package mechanical data
$
%
:7?-%E
!
!
EEE
,
E
B
$
,
%
,
,
E B
$
,
%
,
0IN
+
+
-" -#
Figure 25. UFDFPN8 (MLP8) - 8-lead ultra thin fine pitch dual flat no lead, package
outline
1. Drawing is not to scale.
2. The central pad (the area E2 by D2 in the above illustration) is internally pulled to V
connected to any other voltage or signal line on the PCB, for example during the soldering process.
Table 23. UFDFPN8 (MLP8) 8-lead ultra thin fine pitch dual flat package no lead
. It must not be
SS
2 x 3 mm, data
millimeters inches
Symbol
Typ Min Max Typ Min Max
(1)
A 0.550 0.450 0.600 0.0217 0.0177 0.0236
A1 0.020 0.000 0.050 0.0008 0.0000 0.0020
b 0.250 0.200 0.300 0.0098 0.0079 0.0118
D 2.000 1.900 2.100 0.0787 0.0748 0.0827
D2 (rev MB) 1.600 1.500 1.700 0.0630 0.0591 0.0669
D2 (rev MC) 1.200 1.600 0.0472 0.0630
E 3.000 2.900 3.100 0.1181 0.1142 0.1220
E2 (rev MB) 0.200 0.100 0.300 0.0079 0.0039 0.0118
E2 (rev MC) 1.200 1.600 0.0472 0.0630
e 0.500 0.0197
K (rev MB) 0.800 0.0315
K (rev MC) 0.300 0.0118
L 0.300 0.500 0.0118 0.0197
L1 0.150 0.0059
L3 0.300 0.0118
(2)
eee
1. Values in inches are converted from mm and rounded to four decimal digits.
2. Applied for exposed die paddle and terminals. Exclude embedding part of exposed die paddle from
measuring.
0.080 0.0031
Doc ID 5798 Rev 15 43/49
Page 44
Package mechanical data M95128-W M95128-R M95128-DF
TSSOP8AM
1
8
CP
c
L
EE1
D
A2A
α
eb
4
5
A1
L1
Figure 26. TSSOP8 – 8-lead thin shrink small outline, package outline
1. Drawing is not to scale.
Table 24. TSSOP8 – 8-lead thin shrink small outline, package mechanical data
millimeters inches
Symbol
Typ Min Max Typ Min Max
(1)
A 1.200 0.0472
A1 0.050 0.150 0.0020 0.0059
A2 1.000 0.800 1.050 0.0394 0.0315 0.0413
b 0.190 0.300 0.0075 0.0118
c 0.090 0.200 0.0035 0.0079
CP 0.100 0.0039
D 3.000 2.900 3.100 0.1181 0.1142 0.1220
e 0.650 - - 0.0256 - -
E 6.400 6.200 6.600 0.2520 0.2441 0.2598
E1 4.400 4.300 4.500 0.1732 0.1693 0.1772
L 0.600 0.450 0.750 0.0236 0.0177 0.0295
L1 1.000 0.0394
α 0° 8° 0° 8°
N8 8
1. Values in inches are converted from mm and rounded to four decimal digits.
44/49 Doc ID 5798 Rev 15
Page 45
M95128-W M95128-R M95128-DF Package mechanical data
Figure 27. M95128-DFCS6TP/K, WLCSP 8-bump wafer-level chip scale package outline
BBB
:
$
9
8
E
E
&
%
$ETAIL!
E
2EFERENCE
7AFERBACKSIDE
EEE
1. Drawing is not to scale.
"UMP
:
8
CCC-
DDD-
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Doc ID 5798 Rev 15 45/49
Page 46
Package mechanical data M95128-W M95128-R M95128-DF
Table 25. M95128-DFCS6TP/K, WLCSP 8-bump wafer-level chip scale package
mechanical data
millimeters inches
Symbol
Typ Min Max Typ Min Max
A 0.540 0.500 0.580 0.0213 0.0197 0.0228
A1 0.190 0.0075
A2 0.350 0.0138
b 0.270 0.0106
D 1.271 0.0500
E 1.081 0.0425
e 0.800 0.0315
e1 0.693 0.0273
e2 0.400 0.0157
e3 0.400 0.0157
F 0.184 0.0072
G 0.236 0.0093
H 0.194 0.0076
N (number of terminals) 8 8
(1)
aaa 0.110 0.0043
bbb 0.110 0.0043
ccc 0.110 0.0043
ddd 0.060 0.0024
eee 0.060 0.0024
1. Values in inches are converted from mm and rounded to four decimal digits.
46/49 Doc ID 5798 Rev 15
Page 47
M95128-W M95128-R M95128-DF Part numbering
11 Part numbering
Table 26. Ordering information scheme
Example: M95128-D W MN 6 T P /K
Device type
M95 = SPI serial access EEPROM
Device function
128 = 128 Kbit (16384 x 8)
Device family
Blank = Without Identification page
D = With additional Identification page
Operating voltage
W = V
R = V
F = V
= 2.5 to 5.5 V
CC
= 1.8 to 5.5 V
CC
= 1.7 to 5.5 V
CC
Package
MN = SO8 (150 mil width)
DW = TSSOP8 (169 mil width)
MC = UFDFPN8 (MLP8)
CS = WLCSP
Device grade
6 = Industrial temperature range, –40 to 85 °C.
Device tested with standard test flow
Option
blank = Standard packing
T = Tape and reel packing
Plating technology
G or P = RoHS compliant and halogen-free
(ECOPACK®)
Process
(1)
/K= Manufacturing technology code
1. The process letters apply to WLCSP devices only. The process letters appear on the device package
(marking) and on the shipment box. Please contact your nearest ST Sales Office for further information.
Doc ID 5798 Rev 15 47/49
Page 48
Revision history M95128-W M95128-R M95128-DF
12 Revision history
Table 27. Document revision history
Date Revision Changes
Section 3.8: Supply voltage (V
CC
(WRSR) updated.
Note added to Section 5.6: Write to Memory Array (WRITE).
modified in Table 12: DC characteristics (M95128, device grade 3).
I
CC
added to DC characteristics tables 12, 20, 14 and 23.
V
17-Feb-2009 11
RES
Note added to Table 36: AC characteristics (M95080-R, M95080-DR
device grade 6).
Note added below Figure 20: UFDFPN8, 8-lead ultra thin fine pitch dual
flat package no lead 2 x 3 mm, outline.
Small text changes.
Section 5.6.1: ECC (error correction code) and write cycling modified
(applies to all devices).
, IOL and IOH added to Table 6: Absolute maximum ratings.
T
LEAD
12-Jan-2010 12
Note added to Table 23: DC characteristics (current and new M95080-R
and M95080-DR products).
Process modified in Table 45: Ordering information scheme.
All packages are ECOPACK2 compliant.
Section 5.6.1: ECC (error correction code) and write cycling and Ta bl e 2 4:
02-Mar-2010 13
Available M95128x products (package, voltage range, temperature grade)
updated.
03-Jan-2012 14 Updated UFDFPN8 package data.
Datasheet revision 14 split into:
- M95128-125 datasheet for automotive products (range 3),
- M95128-W M95128-R M95128-DF (this datasheet) for standard
products (range 6).
Updated:
06-Aug-2012 15
– Cycling: 4 million cycles
– Data retention: 200 years
– Max clock frequency: 5 MHz@1.7 V, 10 MHz@2.5 V, 20 MHz@4.5 V.
Added:
– Identification page (for M95128-D devices)
– 1.7 V/5.5 V range (F suffix)
) and Section 5.4: Write Status Register
48/49 Doc ID 5798 Rev 15
Page 49
M95128-W M95128-R M95128-DF
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Doc ID 5798 Rev 15 49/49
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