Datasheet M95040, M95020-W, M95020-R, M95020, M95010-W Datasheet (SGS Thomson Microelectronics)

4/2/1 Kbit Serial SPI Bus EEPROM

■ Compatible with SPI Bus Serial Interface

(Positive Clock SPI Modes)

■ Single Supply Voltage:

– 4.5V to 5.5V for M950x0
– 2.5V to 5.5V for M950x0-W
– 1.8V to 3.6V for M950x0-R

■ 5 MHz Clock Rate (maximum)

■ Status Register

■ BYTE and PAGE WRITE (up to 16 Bytes)

■ Self-Tim ed P ro gr a m ming Cycle

■ Adjustable Size Read-Only EEPR OM Area

■ Enhanced ESD Protection

■ More than 1,000,000 Erase/Write Cycles

■ More than 40 Year Data Retention

DESCRIPTION

These SPI-compatible electrically erasable
programmable memory (EEPROM) devices are
organized as 512 x 8 bits, 256 x 8 bits and 128 x 8
bits (M95040, M95020, M95010). They operate
down to 2.5 V (for the -W version of each device),
and down to 1.8 V (for the -R version of each
device).

M95020, M95010

With High Speed Clock

8

1

PSDIP8 (BN)

0.25 mm frame

8

SO8 (MN)

150 mil width

Figure 1. Logic Diagram

M95040

PRELIMINARY DATA

8

1

TSSOP8 (DW)

169 mil width

1

V

CC

Table 1. Signal Names

C Serial Clock
D Serial Data Input
Q Serial Data Output

S

W

Write Protect

Hold

HOLD
V

CC

V

SS

May 2000

This is preliminary information on a new product now in development or undergoing evaluation. Details are subject to change without notice.

Chip Select

Supply Voltage
Ground

W

HOLD

D
C
S

M95xxx

V

SS

Q

AI01789C

1/19

M95040, M95020, M95010

Figure 2A. DIP Connections

M95xxx

1

SV

2
3

W

4

SS

8
7
6
5

AI01790C

CC

HOLDQ
C
DV

The M95040 and M95020, M95010 are available
in Plastic Dual-in-Line, Plastic Small Out line and
Thin Shrink Small Outline packages.

Each memory device is accessed by a simple
serial interface that is SPI-compatible. The bus
signals are C, D and Q, as shown in Table 1 and
Figure 3.

The device is selected when t he chip s elect input

) is held low. Communications with the chip can

(S
be interrupted using the hold input (HOLD

). Write
operations are disabled by the w rite protect input
(W

).

Figure 2B. SO and TSSOP Connections

M95xxx

1

SV

2
3

W

SS

4

8
7
6
5

AI01791C

CC

HOLDQ
C
DV

SIGNAL DESCRIPTION
Seria l O utput ( Q )

The output pin is used to transfer data serially out
of the Memory. Data is shifted out on the falling
edge of the serial clock.

Serial Inpu t ( D )

The input pin is used to transfer data serially into
the device. Instructions, addresses, and the data
to be written, are each received t his way. Input is
latched on the rising edge of the serial clock.

Serial Clock (C)

The serial clock provides the timing for the serial
interface (as shown in Figure 4). Instructions,
addresses, or data are latched, from the input pin,

Table 2. Absolute Maximum Ratings

Symbol Parameter Value Unit

T

A

T

STG

T

LEAD

V

O

V

I

V

CC

V

ESD

Note: 1. Exc ept for the rating “Operating Temperature Ra nge”, stres ses above those listed in the Table “Absolute Maximum Ratings” may

2/19

cause permanent damage to the device. These are stress ratings only, and operation of the device at these or any other conditions
above those indi cated in t he Operating sect i ons of thi s specifi cation i s not impl i ed. Exposure to Absolute M aximum Rating c ondi­tions for extended periods may affect device reliability. Refer also to the ST SURE Program and other relevant quality documents.

2. MIL -STD-883C, 3015.7 (1 00 pF, 1500 Ω)

3. EIA J I C-121 (Condition C) (200pF, 0W).

Ambient Operating Temperature -40 to 125 °C
Storage Temperature -65 to 150 °C

Lead Temperature during Soldering

Output Voltage Range
Input Voltage Range -0.3 to 6.5 V
Supply Voltage Range -0.3 to 6.5 V

Electrostatic Discharge Voltage (Human Body model)
Electrostatic Discharge Voltage (Machine model)

1

PSDIP8: 10 sec
SO8: 40 sec
TSSOP8: t.b.c.

2

3

260
215

t.b.c.

-0.3 to V

+0.6

CC

4000 V

400 V

°C

V

Figure 3. Microcontroller and Memor y Devices on the SPI Bus

M95040, M95020, M95010

SPI Interface with
(CPOL, CPHA) =
('0', '0') or ('1', '1')

Master

(ST6, ST7, ST9,

ST10, Others)

CS3 CS2 CS1

SDO

SDI

SCK

CQD

M95xxx

S

on the rising edge of the clock input. The output
data on the Q pin chang es state after the falling
edge of the clock input.

Chip Select (S

When S

is high, the memory device is deselected,

)

and the Q output pin is held in its high impe dance
state. Unless an internal write operation is
underway, the memory device is placed in its
stand-by power mode.

After power-on, a high-to-low transition on S

is

required prior to the start of any operation.

Write Protect (W

)

This pin is for hardware write protection. When W
is low, writes to the device are disabled, but all
other operations remain enabled. When W
write operations are enabled. If W

goes low at any

is high,

time before the last bit, D0, of the data stream, the
write enable latch is reset, thus preventing the
write from taking e ffect. No action on W

or on the
write enable latch can interrupt a write cycle which
has commenced, though.

Hold (HOLD

The HOLD

)

pin is used to pause the serial
communications between the SPI memory and
controller, without losing bits that have already
been decoded in the serial sequence. For a hold
condition to occur, the memory device must
already have been selected (S
condition starts when the HOLD

= 0). The hold

pin is held low
while the clock pin (C) is also low (as shown in
Figure 14).

CQD

M95xxx

S

CQD

M95xxx

S

AI01958C

During the hold condition, the Q output pin i s held
in its high impedance sta te, and the level s on the
input pins (D and C) are ignored by the memory
device.

It is possible to deselect the device whe n it is still
in the hold state, thereby resetting whatever
transfer had been in progress. The memory
remains in the hold state as long as the HOLD

pin
is low. To restart communication with the device, it
is necessary both to remove the hold condition (by
takin g HO LD
taking S

high) and to select the memory (by

low).

The Memory can be driven by a microcontroller
with its SPI periphe ral running in ei the r of the two

following modes: (CPOL, CPHA) = (’0’,’0’) or
(CPOL,CPHA) = (’1’,’1’).

For these two modes , input data is latched in by
the low to high transition of clock C, and output
data is available from the h igh to low t ransition of
Clock (C).

The difference between (CPOL, CPHA) = (0, 0)
and (CPOL, CPHA) = (1, 1) is the stand-by
polarity: C remains at ’0’ for (CPOL, CPHA) = (0,

0) and C remains at ’1’ for (CPOL, CPHA) = (1, 1)
when there is no data transfer.

OPERATIONS

All instructions, addresses and data are shifted
serially in and out of the chip. The most significant
bit is presented first, with the data input (D)
sampled on the first rising edge of the clock (C)
after the chip select (S

) goes low.

3/19

M95040, M95020, M95010

Figure 4. Dat a and Clock Timi ng

CPOL

CPHA

0

1

0

1

C

C

D or Q

MSB LSB

Every instruction starts with a single-byte code, as
summarized in Table 3. This code is entered via
the data input (D), and latched on the rising edge
of the clock input (C). To enter an instruction code,
the product must have been previously selected (S
held low). If an invalid i nstruction is sent (one not
contained in Table 3), the chip automatically
deselects itself.

Write Enable (WREN) and Write Disable (WRDI)

The write enable latch, inside the memory device,
must be set prior to each WRITE and WRSR
operation. The WREN instruction (write enable)
sets this latch, and the WRDI instruction (write
disable) resets it.

Table 3. Instruction Set

Instruc

tion

WREN Set Write Enable Latch 0000 X110
WRDI Reset Write Enable Latch 0000 X100
RDSR Read Status Register 0000 X101
WRSR Write Status Register 0000 X001

READ

WRITE Write Data to Memory Array

Note: 1 . A8 = 1 for the uppe r p age on th e M95 04 0, and 0 for the

Read Data from Memory
Array

lower page, and is Don’ t Care for othe r devices.

2. X = Don’t Care.

Description

Instruction

Format

8

8

011

010

0000 A

0000 A

Table 4. Status Register Format

b7 b0

1 1 1 1 BP1 BP0 WEL WIP

Note: 1. BP1 and BP0 are rea d and write bits.

2. WEL and WIP are read only bits.

3. b7 to b4 are read onl y bits.

AI01438

The latch becomes reset by any of the following
events:

– Power on
– WRDI instruction completion
– WRSR in s t ru ctio n completio n
– WRITE instruct ion c ompletion
– the W

pin is held low.

As soon as the WREN or WRDI instruction is
received, the memory device first executes the
instruction, then enters a wait mode until the
device is deselected.

Read Status Register (RDSR)

The RDSR instruction allows the status register to
be read, and can be sent at any time, even during
a Write operation. Indeed, when a Write is in
progress, it is recommended th at the value of t he
Write-In-Progress (WIP) bit be checked. The value
in the WIP bit (whose position in the status register
is shown in Table 4) can be polled, before sending
a new WRITE instruction.

The Write-In-Process (WIP) bit is read-only, and
indicates whether the memory is busy with a Write
operation. A ’1’ indicates that a write is in progress,
and a ’0’ that no write is in progress.

The Write Enable Latch (WEL) bit indicates the
status of the write enable latch. It, too, is read-only.
Its value can only be changed by one of the events
listed in the previous paragraph, or as a result of
executing WREN or WRDI instruction. It cannot be
changed using a WRSR instruction. A ’1’ indicates
that the latch is set (the forthcoming Write
instruction will be executed), and a ’0’ that it is
reset (and any forthcoming Write instructions will
be ignored).

The Block Protect (BP0 and BP1) bits indicate the
amount of the memory that is to be write­protected. These two bits are non-volatile. They
are set using a WRSR instruction.

4/19

Figure 5. RDSR: Read Status Register Sequence

S

21 3456789101112131415

0

C

INSTRUCTION

D

M95040, M95020, M95010

Q

Figure 6. Block Diagram

HOLD

W

S

C

D

Q

Control Logic

Address Register

and Counter

HIGH IMPEDANCE

I/O Shift Register

STATUS REG. OUT

7 6543210

MSB

High Voltage

Generator

Data

Register

AI01444

Status

Register

Size of the
Read only
EEPROM
area

Y Decoder

16 Bytes

X Decoder

AI01272B

5/19

M95040, M95020, M95010

Table 5. Write Protected Block Size

Status Register Bits

Protected Block

BP1 BP0 M95040 M95020 M95010

0 0 none none none none
0 1 Upper quarter 180h - 1FFh C0h - FFh 060h - 7Fh
1 0 Upper half 100h - 1FFh 80h - FFh 040h - 7Fh
1 1 Whole memory 000h - 1FFh 00h - FFh 000h - 7Fh

Array Addresses Protected

During a Write operation (whether it be to the
memory area or to the status register), all bits of
the status register remain valid, and can be read
using the RDSR instruction. However, during a
Write operation, the values of the no n-vo latile bits
(BP0, BP1) become frozen at a constant value.
The updated value of these bits becomes
available when a new RDSR instruction is
executed, after completion of t he write cycle. On
the other hand, the two read-only bits (WEL, WIP)
are dynamically updated during internal write
cycles. U sing th is fac ility, it is possib le to p oll the
WIP bit to detect the end of the internal write cycle.

Write Status Register (WRSR)

The format of the WRSR instruction is shown in
Figure 7. After the instruction and the eigh t bits of
the status register have been latched-in, the
internal Write cycle is trigg ered by t he rising edge
of the S line. This must occur after the falling edge
of the 16
of the 17

th

clock pulse, and before the rising edge

th

clock (as indicated in Figure 7),
otherwise the internal write sequence is not
performed.

The WRSR instruction is used to select the size of
memory area that is to be write-protected.

The BP1 and BP0 bi ts of the st atus register have
the appropriate value (see Table 5) written into
them after the contents of the protected area of the
EEPROM have been written.

The initial delivery state of the BP1 and BP0 bits is
00, indicating a write-protection size of 0.

Read Operation

The chip is first selected by holding S

low. The
serial one byte read instruction is followed by a
one byte address (A7-A0), each bit being latched­in during the rising edge of the clock (C). The most
significant bit, A8, of the address is incorporated
as bit b3 of the instruction byte, as shown in Table

3.
The data stored in the memory, at the selected

address, is shifted out on the Q output pin. Eac h
bit is shifted out during the falling edge of the clock
(C) as shown in Figure 8. The internal address
counter is automatically increment ed to the next
higher address after ea ch byte of data has b een
shifted out. The data stored i n t he m em ory, at t he
next address, can be read by successive clock
pulses. When the highest addres s is reached, the

address counter rolls over to “0000h”, allowing the
read cycle to be continued indefini tely. The read
operation is terminated by deselecting the chip.

Figure 7. WRSR: Write Status Register Sequence

S

21 3456789101112131415

0

C

INSTRUCTION STATUS REG.

D

HIGH IMPEDANCE

Q

6/19

AI01445

Figure 8. Rea d EEPRO M Arr a y Oper a t ion Sequence

S

21 345678910111213141516171819

0

C

INSTRUCTION BYTE ADDRESS

A7

D

A6 A5 A4 A3 A2 A1 A0A8

M95040, M95020, M95010

20 21 22 23

HIGH IMPEDANCE

Q

Note: 1. Depending on the memory size, as shown in Table 6, the most significant address bits are Don’t Care.

Table 6. Address Range Bits

Device M95040 M95020 M95010

Address Bits A8-A0 A7-A0 A6-A0

soon as the memory device is deselected, the self­timed internal write cycle is initiated. While the
write is in progress, the status register may be
read to check the s tatus of the BP1, B P0, WEL

DATA OUT

76543

and WIP bits. In particular, WIP contains a ‘1’
during the self-timed write cycle, and a ‘0’ when

The chip can be deselected at any time during
data output. If a read instruction is received during
a write cycle, it is rejected, and the memory device
deselects itself.

Byte Write Operat ion

Before any write can take place, the WEL bit must
be set, using the WREN instruction. The write
state is entered by selecting the c hip, issuing two
bytes of instruction and address, and one byte of
data. Chip Select (S

) must remain low t hroughout
the operation, as shown in Figure 10. The product
must be deselected just after t he eighth b it of the
data byte has been latched in, as shown in Figure
10, otherwise the write process is cancelled. As

the cycle is complete, (at which point the write
enable latch is also reset).

Page Write Operation

A maximum of 16 bytes of data can be written
during one Write time, t

, provided that they are all

W

to the same page (see Figure 6). The Page Write
operation is the same as the Byte Write operation,
except that instead of deselecting the device after
the first byte of data, up to 15 additional bytes can
be shifted in (and t hen the device is deselected
after the last byte).

Any address of the memory can be chosen as the
first address to be wri tten. If the addres s counter
reaches the end of the page (an add ress of the

2

1

0

AI01440

Figure 9. Write Enable Latch Sequen ce

S

C

D

Q

21 34567

0

HIGH IMPEDANCE

AI01441

7/19

M95040, M95020, M95010

Figure 10. Byte Write Operation Sequence

S

21 345678910111213141516171819

0

C

20 21 22 23

INSTRUCTION BYTE ADDRESS

A7

D

HIGH IMPEDANCE

Q

Note: 1. Depending on the memory size, as shown in Table 6, the most significant address bits are Don’t Care.

A6 A5 A4 A3 A2 A1 A0A8

DATA BYTE

765432 0

Figure 11. Page Write Operation Sequence

S

21 34567891011121314151617181920 21 22 23

0

C

INSTRUCTION BYTE ADDRESS

DATA BYTE 1

1

AI01442

D

S

2625 27 28 29 30 31

24

C

DATA BYTE 2

54

D

Note: 1. Depending on th e m em ory size, as shown in Table 6, the mo st si gnifica nt a ddress bits are Don’t Care.

76 3210

A7 A6 A5 A4 A3 A2 A1 A0A8 765432 0

8+8N

9+8N

10+8N

11+8N

12+8N

13+8N

14+8N

15+8N

136

137

138

139

140

DATA BYTE N

76543210765432 0

DATA BYTE 16

8/19

141

1

1

142

7

143

AI01443

M95040, M95020, M95010

form xxxx 1111) and the clock continues, the
counter rolls over to the first address of the same
page (xxxx 0000) and over-writes any previously
written data.

As before, the Write cycle only starts if the S
transition occurs just after the eighth bit of the last
data byte has been received, as shown in Figure

11.

DATA PROTECTION AND PROTOCOL SAFETY

To protect the data in the memory from inadvertent
corruption, the memory device only responds to
correctly formulated commands. The main
security measures can be summarized as follows:

– The WEL bit is reset at power-up.

must rise after the eighth clock count (or

–S

multiple thereof) in ord er to start a non-volatile
write cycle (in the memory array or in the status
register).

– Accesses to the memory array are ignored

during the non-volatile pr ogrammin g cycle, and
the programming cycle continues unaffected.

– After execution of a WREN, WRDI, or RDSR

instruction, the chip enters a wait state, and
waits to be deselected.

– Inva lid S

and HOLD transitions are ignored.

POWE R O N STATE

After power-on, the memory device is in the
following state:

– low power stand-by state
– deselected (after power-on, a high-to-low

transition is required on the S

input before any

operations can be started).
– not in the hold condition
– the WEL bit is reset
– the BP1 and BP0 bits of the status regist er are

unchanged from the previous power-down (they

are non-volatile bits).

INITIAL DELIVERY STATE

The device is delivered with the memory array in a
fully erased state (all data set at all 1s or FFh). The
status register bits are initialized to 00h, as shown
in Table 7.

Table 7. Initial Status Register Format

b7 b0

1 1110000

Table 8. Input Parameters1 (TA = 25 °C, f = 5 MHz)

Symbol Parameter Test Condition Min. Max. Unit

C

OUT

C

IN

Note: 1. Sampled only, not 100% tested.

Output Capacitance (Q) 8 pF
Input Capacitance (D) 8 pF
Input Capacitance (other pins) 6 pF

9/19

M95040, M95020, M95010

Table 9. DC Characteristics

(T

= –40 to 85 °C or –40 to 125 °C; VCC = 4.5 to 5.5 V)

A

(T

= –40 to 85 °C; VCC = 2.5 to 5.5 V)

A

= –20 to 85 °C; VCC = 1.8 to 3.6 V)

(T

A

Symbol Parameter

Input Leakage

I

LI

Current

Voltage

Range

all all ± 2 µA

Temp.

Range

Test Condition Min. Max. Unit

I

LO

I

CC

I

CC1

V

IL

V

IH

1

V

OL

Output Leakage
Current

Supply Current

Supply Current
(Stand-by)

Input Low
Voltage

Input High
Voltage

Output Low
Voltage

all all ± 2 µA

4.5-5.5 6

4.5-5.5 3

2.5-5.5 6

1.8-3.6 5

4.5-5.5 6

4.5-5.5 3

2.5-5.5 6

1.8-3.6 5 S

C = 0.1V

C = 0.1V

C = 0.1V

C = 0.1V

S

= VCC, V

S

= VCC, V

S

= VCC, V
= VCC, V

all all – 0.3

all all

4.5-5.5 6 I

4.5-5.5 3

2.5-5.5 6 I

1.8-3.6 5

OL

I

OL

4.5-5.5 6 I

/0.9VCC , at 5 MHz,

CC

= 5 V, Q = open

V

CC

/0.9VCC , at 2 MHz,

CC

V

= 5 V, Q = open

CC

/0.9VCC , at 2 MHz,

CC

= 2.5 V, Q= open

V

CC

/0.9VCC , at 1 MHz,

CC

= 1.8 V, Q= open

V

CC

= VSS or V

IN

= VSS or V

IN

= VSS or V

IN

= VSS or V

IN

= 2 mA, VCC = 5 V 0.4 V

OL

I

= 2 mA, VCC = 5 V

OL

CC

CC

, V

CC

CC

= 5 V

CC

, V

= 5 V

CC

, V

= 2.5 V

CC

, V

= 1.8 V 2 µA

CC

0.7 V

CC

5mA

5mA

2mA

2mA

10 µA
10 µA

2µA

0.3 V

CC

VCC+1

0.4 V

= 1.5 mA, VCC = 2.5 V 0.4 V

= 0.15 mA, VCC = 1.8 V

= –2 mA, VCC = 5 V 0.8 V

OH

CC

0.3

V

V

V
V

Output High

1

V

OH

Voltage

4.5-5.5 3

2.5-5.5 6

1.8-3.6 5

Note: 1. For all 5V range devi ces, the devi ce meets th e out put requi rem ents for b ot h TT L and CMOS standards.

I

= –2 mA, VCC = 5 V

OH

I

= –0.4 mA, VCC = 2.5V 0.8 V

OH

I

= –0.1 mA, VCC = 1.8V 0.8 V

OH

0.8 V

10/19

CC

CC

CC

V
V

V

Table 10A. AC Characteristics

Symbol Alt. Parameter

M95040, M95020, M95010

M95040, M95020, M95010

V

=4.5 to 5.5 V

CC

T

=–40 to 85°C

A

Min Max Min Max

=4.5 to 5.5 V

V

CC

T

=–40 to 125°C

A

Unit

f

C

t

SLCH

t

SHCH

t

SHSL

t

CHSH

t

CHSL

t

CH

1

t

CL

t

CLCH

t

CHCL

t

DVCH

t

CHDX

t

DLDH

t

DHDL

t

HHCH

t

HLCH

t

CLHL

t

CLHH

t

SHQZ

t

CLQV

t

CLQX

t

QLQH

t

QHQL

t

HHQX

t

HLQZ

t

W

Note: 1. tCH + tCL ≥ 1 / fC.

2. Val ue guarantee d by characterization, not 100% tes ted in product i on.

f

t

CSS1

t

CSS2

t

Clock Frequency D.C. 5 D.C. 2 MHz

SCK

S Active Setup Time 90 200 ns
S Not Active Setup Time 90 200 ns

t

S Deselect Time 100 200 ns

CS

S Active Hold Time 90 200 ns

CSH

S Not Active Hold Time 90 200 ns

1

t
t

2

2

t

2

2

Clock High Time 90 200 ns

CLH

Clock Low Time 90 200 ns

CLL

t

Clock Rise Time 1 1 µs

RC

t

Clock Fall Time 1 1 µs

FC

Data In Setup Time 20 40 ns

DSU

t

Data In Hold Time 30 50 ns

DH

t

Data In Rise Time 1 1 µs

RI

t

Data In Fall Time 1 1 µs

FI

t

Clock Low Hold Time after HOLD not Active 70 140 ns

CD

Clock Low Hold Time after HOLD Active 40 90 ns
Clock Low Set-up Time before HOLD Active 0 0 ns
Clock Low Set-up Time before HOLD not Active 0 0 ns

2

t

2

2

2

2

t

Output Disable Time 100 250 ns

DIS

t

Clock Low to Output Valid 60 150 ns

V

t

Output Hold Time 0 0 ns

HO

t

Output Rise Time 50 100 ns

RO

t

Output Fall Time 50 100 ns

FO

t

HOLD High to Output Low-Z 50 100 ns

LZ

t

HOLD Low to Output High-Z 100 250 ns

HZ

Write Time 10 10 ms

WC

11/19

M95040, M95020, M95010

Table 10B. AC Characteristics

Symbol Alt. Parameter

f

C

t

SLCH

t

SHCH

t

SHSL

t

CHSH

t

CHSL

1

t

CH

1

t

CL

t

CLCH

t

CHCL

t

DVCH

t

CHDX

t

DLDH

t

DHDL

t

HHCH

t

HLCH

t

CLHL

t

CLHH

t

SHQZ

t

CLQV

t

CLQX

t

QLQH

t

QHQL

t

HHQX

t

HLQZ

t

W

Note: 1. tCH + tCL ≥ 1 / fC.

2. Val ue guarantee d by characterization, not 100% tes ted in product i on.

f

SCK

t

CSS1

t

CSS2

t

t

CSH

Clock Frequency D.C. 2 D.C. 1 MHz
S Active Setup Time 200 400 ns
S Not Active Setup Time 200 400 ns
S Deselect Time 200 300 ns

CS

S Active Hold Time 200 400 ns
S Not Active Hold Time 200 400 ns

t

CLH

t

CLL

2

t

2

t

t

DSU

t

2

t

2

t

Clock High Time 200 400 ns
Clock Low Time 200 400 ns
Clock Rise Time 1 1 µs

RC

Clock Fall Time 1 1 µs

FC

Data In Setup Time 40 60 ns
Data In Hold Time 50 100 ns

DH

Data In Rise Time 1 1 µs

RI

t

Data In Fall Time 1 1 µs

FI

Clock Low Hold Time after HOLD not Active 140 350 ns

CD

Clock Low Hold Time after HOLD Active 90 200 ns
Clock Low Set-up Time before HOLD Active 0 0 ns
Clock Low Set-up Time before HOLD not Active 0 0 ns

2

t

t

2

t

2

t

2

t

2

t

t

Output Disable Time 250 500 ns

DIS

t

Clock Low to Output Valid 150 380 ns

V

Output Hold Time 0 0 ns

HO

Output Rise Time 100 200 ns

RO

Output Fall Time 100 200 ns

FO

HOLD High to Output Low-Z 100 250 ns

LZ

HOLD Low to Output High-Z 250 500 ns

HZ

Write Time 10 10 ms

WC

M950x0-W M950x0-R

V

=2.5 to 5.5 V

CC

T

=–40 to 85°C

A

=1.8 to 3.6 V

V

CC

T

=–20 to 85°C

A

Min Max Min Max

Unit

12/19

M95040, M95020, M95010

Table 11. AC Measurement Conditions

Input Rise and Fall Times
Input Pulse Voltages
Input and Output Timing

Reference Voltages
Output Load

Note: 1. Output Hi-Z is defined as the point where data is no long-

er driven.

0.2V

0.3V

50 ns

≤

to 0.8V

CC

to 0.7V

CC

C

= 100 pF

L

CC

CC

Figure 13. Serial Input Timing

S

tSLCH

C

tDVCH

tCHDX

D

Q

MSB IN

HIGH IMPEDANCE

Figure 12. AC Testing Input Output Waveforms

0.8V

0.2V

tDLDH
tDHDL

CC

CC

tCHSHtCHSL

tCLCH

tSHSL

tSHCH

tCHCL

LSB IN

AI01447

0.7V

0.3V

AI00825

CC

CC

Figure 14. Hol d Timing

S

C

Q

D

HOLD

tCLHL

tHLCH

tHHCH

tCLHH

tHHQXtHLQZ

AI01448

13/19

M95040, M95020, M95010

Figure 15. Output Timing

S

C

tCLQX

tCLQV

tCH

tCL

tSHQZ

Q

ADDR.LSB IN

D

tQLQH
tQHQL

LSB OUT

AI01449B

ORDERING INFORMATION

The notation used for the device number is as show n in Table 12. For a list of available option s (speed,
package, etc.) or for further information on any aspect of this device, please contact t he ST Sales Office
nearest to you.

Table 12. Ordering Information Scheme

Example: M95040 – W MN 6 TR

Memory Capacity

3

040 4 Kbit (512 x 8) with positive clock strobe TR Tape and Reel Packing
020 2 Kbit (256 x 8) with positive clock strobe
010 1 Kbit (128 x 8) with positive clock strobe Temperature Range

5 –20 °C to 85 °C
6 –40 °C to 85 °C

1

3

Option

–40 °C to 125 °C

Operating Voltage Package

blank 4.5 V to 5.5 V BN PSDIP8 (0.25 mm frame)
W 2.5 V to 5.5 V MN SO8 (150 mil width)

2

1.8 V to 3.6 V

R

Note: 1. Temperature range avail abl e only on re quest, in VCC range 4.5 V t o 5. 5 V only.

2. The -R version (V

3. All devices use a positive clock strobe: Data In is strobed on the rising edge of the clock (C) and Data Out is synchronized from the
falling ed ge of the clock.

range 1.8 V t o 3. 6 V) only avail able in temperature ra nge 5.

CC

TSSOP8 (169 mil width)

DW

14/19

Table 13. PSDIP8 - 8 pin Plastic Skinny DIP, 0.25mm lead frame

mm inches

Symb.

Typ. Min. Max. Typ. Min. Max.

A 3.90 5.90 0.154 0.232

A1 0.49 – 0.019 –

A2 3.30 5.30 0.130 0.209

B 0.36 0.56 0.014 0.022

B1 1.15 1.65 0.045 0.065

C 0.20 0.36 0.008 0.014
D 9.20 9.90 0.362 0.390

E 7.62 – – 0.300 – –
E1 6.00 6.70 0.236 0.264
e1 2 .54 – – 0.100 – –
eA 7.80 – 0.307 –
eB 10.00 0.394

L 3 .00 3.80 0.118 0.150

N8 8

M95040, M95020, M95010

Figure 16. PSDIP8 (BN)

Note: 1. Drawing is not to scale.

A2

A1AL

B

N

1

e1

B1

D

E1 E

eA
eB

C

PSDIP-a

15/19

M95040, M95020, M95010

Table 14. SO8 - 8 lead Plastic Small Outline, 150 mils body width

Symb.

Typ. Min. Max. Typ. Min. Max.

A 1.35 1.75 0.053 0.069
A1 0.10 0.25 0.004 0.010

B 0.33 0.51 0.013 0.020

C 0.19 0.25 0.007 0.010

D 4.80 5.00 0.189 0.197

E 3.80 4.00 0.150 0.157

e 1.27 – – 0.050 – –

H 5.80 6.20 0.228 0.244

h 0 .25 0.50 0.010 0.020

L 0 .40 0.90 0.016 0.035

α

N8 8

CP 0.10 0.004

mm inches

0° 8° 0° 8°

Figure 17. SO8 narrow (MN)

B

SO-a

Note: 1. Drawing is not to scale.

h x 45˚

A

e

D

N

1

CP

E

H

C

LA1 α

16/19

Table 15. TSSOP8 - 8 lead Thin Shrink Small Outline

Symb.

Typ. Min. Max. Typ. Min. Max.

A 1.10 0.043
A1 0.05 0.15 0.002 0.006
A2 0.85 0.95 0.033 0.037

B 0.19 0.30 0.007 0.012

C 0.09 0.20 0.004 0.008

D 2.90 3.10 0.114 0.122

E 6.25 6.50 0.246 0.256
E1 4.30 4.50 0.169 0.177

e 0.65 – – 0.026 – –

L 0.50 0.70 0.020 0.028

α

N8 8

CP 0.08 0.003

mm inches

0° 8° 0° 8°

M95040, M95020, M95010

Figure 18. TSSOP8 (DW)

CP

Note: 1. Drawing is not to scale.

D

A1

DIE

C

α

L

TSSOP

N

EE1

1

N/2

A2A

eB

17/19

M95040, M95020, M95010

Table 16. Revision History

Date Description of Revision

10-May-2000 s/issuing three bytes/issuing two bytes/ in the 2nd sentence of the Byte Write Operation

18/19

M95040, M95020, M95010

Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences
of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted
by implic ation or otherwise under any patent or p atent rights of STMi croelectr oni cs. Spec i fications mentioned i n this publicatio n are subject
to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not
authorized for use as cri tical comp onents in life support dev i ces or systems wi t hout expres s written approval of STMi croelectr o nics.

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19/19