Page 1
MC74VHC1GT50
Noninverting Buffer /
CMOS Logic Level Shifter
TTL−Compatible Inputs
The MC74VHC1GT50 is a single gate noninverting buffer
fabricated with silicon gate CMOS technology. It achieves high speed
operation similar to equivalent Bipolar Schottky TTL while
maintaining CMOS low power dissipation.
The internal circuit is composed of three stages, including a buffer
output which provides high noise immunity and stable output.
The device input is compatible with TTL−type input thresholds and
the output has a full 5 V C MOS level output swing. T he input p rotection
circuitry on this device allows overvoltage tolerance on the input,
allowing the device to be used as a logic−level translator from 3 V
CMOS logic to 5 V CMOS Logic or from 1.8 V CMOS logic to 3 V
CMOS Logic while operating at the high−voltage power supply.
The MC74VHC1GT50 input structure provides protection when
voltages up to 7 V are applied, regardless of the supply voltage. This
allows the MC74VHC1GT50 to be used to interface high voltage to
low voltage circuits. The output structures also provide protection
when V
device destruction caused by supply voltage − input/output voltage
mismatch, battery backup, hot insertion, etc.
Features
• Designed for 1.65 V to 5.5 V
• High Speed: t
• Low Power Dissipation: I
• TTL−Compatible Inputs: V
• CMOS−Compatible Outputs: V
• Power Down Protection Provided on Inputs and Outputs
• Balanced Propagation Delays
• Pin and Function Compatible with Other Standard Logic Families
• Chip Complexity: FETs = 104; Equivalent Gates = 26
• NLV Prefix for Automotive and Other Applications Requiring
Unique Site and Control Change Requirements; AEC−Q100
Qualified and PPAP Capable
• These Devices are Pb−Free and are RoHS Compliant
= 0 V. These input and output structures help prevent
CC
Operation
CC
= 3.5 ns (Typ) at VCC = 5 V
PD
= 1 mA (Max) at TA = 25°C
CC
= 0.8 V; VIH = 2.0 V, VCC = 5 V
IL
> 0.8 VCC; VOL < 0.1 VCC @Load
OH
5
NC
1
V
CC
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www.
MARKING
DIAGRAMS
5
1
SC−88A / SOT−353 / SC−70
DF SUFFIX
CASE 419A
5
1
TSOP−5 / SOT−23 / SC−59
DT SUFFIX
CASE 483
VL = Device Code
M = Date Code*
G = Pb−Free Package
(Note: Microdot may be in either location)
*Date Code orientation and/or position may vary
depending upon manufacturing location.
PIN ASSIGNMENT
1
2
3 GND
4
5V
NC
IN A
OUT Y
CC
5
1
5
1
M
VL M G
VL M G
G
G
2
IN A
34
Figure 1. Pinout (Top View)
IN A
Figure 2. Logic Symbol
© Semiconductor Components Industries, LLC, 2015
October, 2015 − Rev. 16
1
OUT YGND
OUT Y
FUNCTION TABLE
A Input Y Output
L
H
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 4 of this data sheet.
1 Publication Order Number:
L
H
MC74VHC1GT50/D
Page 2
MC74VHC1GT50
MAXIMUM RATINGS
Symbol Characteristics Value Unit
V
V
V
I
I
OUT
I
q
T
V
I
Latchup
Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality
should not be assumed, damage may occur and reliability may be affected.
1. Tested to EIA/JESD22−A114−A
2. Tested to EIA/JESD22−A115−A
3. Tested to JESD22−C101−A
4. Tested to EIA/JESD78
DC Supply Voltage −0.5 to +7.0 V
CC
DC Input Voltage −0.5 to +7.0 V
IN
DC Output Voltage VCC = 0
OUT
I
Input Diode Current −20 mA
IK
Output Diode Current V
OK
High or Low State
< GND; V
OUT
OUT
> V
CC
−0.5 to 7.0
−0.5 to V
CC
+20 mA
DC Output Current, per Pin +25 mA
DC Supply Current, VCC and GND +50 mA
CC
P
Power dissipation in still air SC−88A, TSOP−5 200 mW
D
Thermal resistance SC−88A, TSOP−5 333 °C/W
JA
T
Lead temperature, 1 mm from case for 10 secs 260 °C
L
T
Junction temperature under bias +150 °C
J
Storage temperature −65 to +150 °C
stg
ESD Withstand Voltage Human Body Model (Note 1)
ESD
Machine Model (Note 2)
Charged Device Model (Note 3)
> 2000
> 200
N/A
Latchup Performance Above VCC and Below GND at 125°C (Note 4) ±500 mA
+ 0.5
V
V
RECOMMENDED OPERATING CONDITIONS
Symbol Characteristics Min Max Unit
V
V
V
t
DC Supply Voltage 1.65 5.5 V
CC
DC Input Voltage 0.0 5.5 V
IN
DC Output Voltage VCC = 0
OUT
T
Operating Temperature Range −55 +125 °C
A
, tfInput Rise and Fall Time VCC = 3.3 V ± 0.3 V
r
High or Low State
VCC = 5.0 V ± 0.5 V
0.0
0.0
0
0
5.5
V
100
20
CC
ns/V
Device Junction Temperature versus
Time to 0.1% Bond Failures
Junction
Temperature °C
Time, Hours Time, Years
80 1,032,200 117.8
90 419,300 47.9
100 178,700 20.4
110 79,600 9.4
120 37,000 4.2
130 17,800 2.0
140 8,900 1.0
Figure 3. Failure Rate vs. Time Junction Temperature
FAILURE RATE OF PLASTIC = CERAMIC
UNTIL INTERMETALLICS OCCUR
= 130 C°
J
T
J
J
T
T
= 110 C°
= 120 C°
1
NORMALIZED FAILURE RATE
1 10 100
TIME, YEARS
C°
C°
= 80
= 90
= 100 C°
J
T
J
J
T
T
1000
V
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Page 3
MC74VHC1GT50
l
DC ELECTRICAL CHARACTERISTICS
V
CC
Symbol Parameter Test Conditions (V) Min Typ Max Min Max Min Max Unit
V
IH
Minimum
High−Level
Input Voltage
1.65 to 2.29
2.3 to 2.99
3.0
4.5
5.5
V
IL
Maximum
Low−Level
Input Voltage
1.65 to 2.29
2.3 to 2.99
3.0
4.5
5.5
I
OH
OL
IN
Minimum
High−Level
Output
Voltage
Maximum
Low−Level
Output
Voltage
Maximum
Input
Leakage
V
= V
IN
IH
IOH = −50 mA
1.65 to 2.99
3.0
4.5
V
= VIH
IN
I
= −4 mA
OH
= −8 mA
I
OH
VIN = V
IL
IOL = 50 mA
3.0
4.5
1.65 to 2.99
3.0
4.5
V
= V
IN
IL
IOL = 4 mA
= 8 mA
I
OL
3.0
4.5
VIN = 5.5 V or GND 0 to
5.5
V
V
Current
Maximum
I
CC
Quiescent
VIN = VCC or GND 5.5 1.0 20 40
Supply
Current
I
CCT
Quiescent
Supply
Input: VIN = 3.4 V 5.5 1.35 1.50 1.65 mA
Current
I
OPD
Output
Leakage
V
= 5.5 V 0.0 0.5 5.0 10
OUT
Current
TA = 25°C TA ≤ 85°C −55 ≤ TA ≤ 125°C
0.50 V
CC
0.45 V
CC
1.4
2.0
2.0
VCC − 0.1
2.9
4.4
2.58
3.94
3.0
4.5
0.0
0.0
0.10 V
0.15 V
0.53
0.8
0.8
0.1
0.1
0.1
0.36
0.36
CC
CC
0.50 V
CC
0.45 V
CC
1.4
2.0
2.0
VCC − 0.1
2.9
4.4
2.48
3.80
0.10 V
0.15 V
0.53
0.8
0.8
0.1
0.1
0.1
0.44
0.44
CC
CC
VCC − 0.1
$0.1 $1.0 $1.0
0.50 V
0.45 V
1.4
2.0
2.0
2.9
4.4
2.34
3.66
CC
CC
0.10 V
0.15 V
0.53
0.8
0.8
0.1
0.1
0.1
0.52
0.52
CC
CC
V
V
V
V
V
V
mA
mA
mA
= 50 pF
= 50 pF
= 50 pF
= 3.0 ns
f
Min
TA = 25°C
Typ
4.5
6.3
3.5
4.3
Max
13.3
19.5
10.0
13.5
6.7
7.7
TA ≤ 85°C
Min
−55 ≤ TA ≤ 125°C
Max
14.5
22.0
11.0
15.0
7.5
8.5
Min
Max
17.5
25.5
13.0
17.5
8.5
9.5
5 10 10 10 pF
Unit
ns
ns
AC ELECTRICAL CHARACTERISTICS C
Symbo
t
PLH
t
PHL
C
IN
,
Parameter
Maximum
Propagation
Delay, Input A to Y
Maximum Input
Capacitance
Test Conditions
VCC = 1.8 ± 0.15 V CL = 15 pF 16.6 18.0 22.0 ns
VCC = 2.5 ± 0.2 V CL = 15 pF
VCC = 3.3 ± 0.3 V CL = 15 pF
VCC = 5.0 ± 0.5 V CL = 15 pF
= 50 pF, Input tr = t
load
C
C
C
L
L
L
Typical @ 25°C, VCC = 5.0 V
C
Power Dissipation Capacitance (Note 5)
PD
12
pF
5. CPD is defined as the value of the internal equivalent capacitance which is calculated from the operating current consumption without load.
Average operating current can be obtained by the equation: I
power consumption; P
= CPD V
D
2
fin + ICC VCC.
CC
= CPD VCC fin + ICC. CPD is used to determine the no−load dynamic
)
CC(OPR
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3
Page 4
MC74VHC1GT50
A
50%
t
PLH
Y
Figure 4. Switching Waveforms
DEVICE
UNDER
TEST
50% V
CC
TEST POINT
OUTPUT
t
PHL
CL*
V
CC
GND
V
OH
V
OL
*Includes all probe and jig capacitance
Figure 5. Test Circuit
ORDERING INFORMATION
Device Package Shipping
M74VHC1GT50DFT1G
NLVVHC1GT50DFT1G*
M74VHC1GT50DFT2G
SC−88A / SOT−353 / SC−70
(Pb−Free)
3000 / Tape & Reel
NLVVHC1GT50DFT2G*
M74VHC1GT50DTT1G
NLV74VHC1GT50DTT1G*
TSOP−5 / SOT−23 / SC−59
(Pb−Free)
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
*NLV Prefix for Automotive and Other Applications Requiring Unique Site and Control Change Requirements; AEC−Q100 Qualified and PPAP
Capable.
†
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Page 5
MC74VHC1GT50
PACKAGE DIMENSIONS
SC−88A (SC−70−5/SOT−353)
CASE 419A−02
ISSUE L
A
G
45
D
5 PL
−B−
MM
B0.2 (0.008)
S
12 3
N
NOTES:
1. DIMENSIONING AND TOLERANCING
PER ANSI Y14.5M, 1982.
2. CONTROLLING DIMENSION: INCH.
3. 419A−01 OBSOLETE. NEW STANDARD
419A−02.
4. DIMENSIONS A AND B DO NOT INCLUDE
MOLD FLASH, PROTRUSIONS, OR GATE
BURRS.
INCHES
DIMAMIN MAX MIN MAX
B 1.15 1.350.045 0.053
C 0.80 1.100.031 0.043
D 0.10 0.300.004 0.012
G 0.65 BSC0.026 BSC
H --- 0.10---0.004
J 0.10 0.250.004 0.010
K 0.10 0.300.004 0.012
N 0.20 REF0.008 REF
S 2.00 2.200.079 0.087
MILLIMETERS
1.80 2.200.071 0.087
J
C
H
K
SOLDER FOOTPRINT
0.50
0.0197
0.40
0.0157
1.9
0.0748
SCALE 20:1
0.65
0.025
0.65
0.025
mm
ǒ
inches
Ǔ
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5
Page 6
MC74VHC1GT50
TSOP−5
P
al
PACKAGE DIMENSIONS
CASE 483−02
ISSUE L
NOTES:
1. DIMENSIONING AND TOLERANCING PER ASME
NOTE 5
2X
2X
T0.10
B
A
54
B
123
G
A
T0.20
D
0.205XC AB
M
S
K
DETAIL Z
TOP VIEW
J
DETAIL Z
C
0.05
H
SIDE VIEW
C
SEATING
PLANE
END VIEW
SOLDERING FOOTPRINT*
0.037
0.95
1.9
0.074
Y14.5M, 1994.
2. CONTROLLING DIMENSION: MILLIMETERS.
3. MAXIMUM LEAD THICKNESS INCLUDES LEAD FINISH
THICKNESS. MINIMUM LEAD THICKNESS IS THE
MINIMUM THICKNESS OF BASE MATERIAL.
4. DIMENSIONS A AND B DO NOT INCLUDE MOLD
FLASH, PROTRUSIONS, OR GATE BURRS. MOLD
FLASH, PROTRUSIONS, OR GATE BURRS SHALL NOT
EXCEED 0.15 PER SIDE. DIMENSION A.
5. OPTIONAL CONSTRUCTION: AN ADDITIONAL
TRIMMED LEAD IS ALLOWED IN THIS LOCATION.
TRIMMED LEAD NOT TO EXTEND MORE THAN 0.2
FROM BODY.
MILLIMETERS
DIM MIN MAX
A 3.00 BSC
B 1.50 BSC
C 0.90 1.10
D 0.25 0.50
G 0.95 BSC
H 0.01 0.10
J 0.10 0.26
K 0.20 0.60
M 0 10
__
S 2.50 3.00
2.4
0.094
1.0
0.039
0.7
0.028
SCALE 10:1
ǒ
inches
mm
Ǔ
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
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6
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