The M74HCT75 is an high spe ed CMOS 4 BIT D
TYPE LATCH fabricated with silicon gate C
2
MOS
technology.
It contains two groups of 2 bit latches controlled by
an enable input (G1
•2 or G3•4). These two latch
groups can be used in different circuits. Each latch
has Q and Q
outputs (1Q - 4Q and 1Q - 4Q). The
data applied to the data input is transferred to the
Q and Q
outputs when the enable input is taken
high and the outputs will follow the data input as
long as the enable input is kept high. When the
TSSOPDIPSOP
ORDER CODES
PACKAGETUBET & R
DIPM74HCT75B1R
SOPM74HCT75M1RM74HCT75RM13TR
TSSOPM74HCT75TTR
enable input is taken low, the information data
applied to the data input is retained at the outputs.
The M74HCT75 is designed to directly interface
2
HSC
MOS systems with TTL and NMOS
components.
All inputs are equipped with protection circuits
against static discharge and transient excess
voltage.
PIN CONNECTION AND IEC LOGIC SYMBOLS
1/9September 2001
Page 2
M74HCT75
IINPUT AND OUTPUT EQUIVALENT CIRCUIT PIN DESCRIPTION
PIN NoSYMBOLNAME AND FUNCTION
1, 4, 11, 8 1Q
2, 3, 6, 71D to 4DData Inputs
4G3 • 4
13G1 • 2
16, 15, 10, 91Q to 4QLatch Outputs
12GNDGround (0V)
5
TRUTH TABLE
to 4Q
V
CC
Complementary Latch
Outputs
Latch Enable Input,
latches 3 and 4
Latch Enable Input,
latches 1 and 2
Positive Supply Voltage
LOGIC DIAGRAM
INPUTSOUTPUTS
DGQQ
LHLH
HHHL
XLQnQ
nLATCH
FUNCTION
2/9
Page 3
M74HCT75
ABSOLUTE MAXIMUM RATINGS
SymbolParameterValueUnit
V
V
V
I
I
OK
I
I
or I
CC
P
T
T
Absolute Maximum Ratings are those values beyond which damage to the device may occur. Functional operation under these conditions is
not implied
(*) 500mW at 65
RECOMMENDED OPERATING CONDITIONS
SymbolParameterValueUnit
V
V
V
T
t
r
Supply Voltage
CC
DC Input Voltage-0.5 to VCC + 0.5
I
DC Output Voltage-0.5 to VCC + 0.5
O
DC Input Diode Current
IK
DC Output Diode Current
DC Output Current
O
DC VCC or Ground Current
GND
Power Dissipation
D
Storage Temperature
stg
Lead Temperature (10 sec)
L
°C; derate to 300mW by 10mW/°C from 65°C to 85°C
Supply Voltage
CC
Input Voltage0 to V
I
Output Voltage0 to V
O
Operating Temperature
op
, t
Input Rise and Fall Time (VCC = 4.5 to 5.5V)
f
-0.5 to +7V
± 20mA
± 20mA
± 25mA
± 50mA
500(*)mW
-65 to +150°C
300°C
4.5 to 5.5V
CC
CC
-55 to 125°C
0 to 500ns
V
V
V
V
3/9
Page 4
M74HCT75
DC SPECIFICATIONS
SymbolParameter
V
V
V
V
I
∆ I
High Level Input
IH
Voltage
Low Level Input
IL
Voltage
High Level Output
OH
Voltage
Low Level Output
OL
Voltage
I
Input Leakage
I
Current
Quiescent Supply
CC
Current
Additional Worst
CC
Case Supply
Current
Test ConditionValue
T
= 25°C
V
CC
(V)
A
Min.Typ. Max.Min.Max. Min. Max.
4.5
to
2.02.02.0V
5.5
4.5
to
0.80.80.8V
5.5
4.5
4.5
5.5
5.5
IO=-20 µA
I
=-4.0 mA
O
IO=20 µA
I
=4.0 mA
O
= VCC or GND
V
I
= VCC or GND
V
I
5.5Per Input pin
V
= 0.5V or
I
V
= 2.4V
I
4.44.54.44.4
4.184.314.134.10
0.00.10.10.1
0.170.260.330.40
± 0.1± 1± 1µA
2.02.93.0mA
Other Inputs at
V
or GND
CC
I
= 0
O
-40 to 85°C -55 to 125°C
Unit
V
V
22040µA
AC ELECTRICAL CHARACTERISTICS (C
Test ConditionValue
SymbolParameter
t
TLH tTHL
t
PLH tPHL
t
PLH tPHL
t
W(H)
Output Transition
Time
Propagation Delay
Time (DATA - Q)
Propagation Delay
Time (G - Q)
Minimum Pulse
Width (G)
Minimum Set-Up
t
s
Time
Minimum Hold
t
h
Time
V
CC
(V)
4.58151922ns
4.518283542ns
4.521334150ns
4.58151922ns
4.54101315ns
4.5558ns
= 50 pF, Input tr = tf = 6ns)
L
= 25°C
T
A
Min.Typ. Max.Min.Max. Min. Max.
-40 to 85°C -55 to 125°C
Unit
4/9
Page 5
M74HCT75
CAPACITIVE CHARACTERISTICS
Test ConditionValue
T
SymbolParameter
C
C
Input Capacitance
IN
Power Dissipation
PD
Capacitance (note
V
CC
(V)
= 25°C
A
Min.Typ. Max.Min.Max. Min. Max.
5101010pF
61pF
1)
1) CPD is defined as the value of the IC’s internal equivalent capacitance which is calculated from the operating current consumption without
load. (R ef er to Test Circ ui t ). Average operating cu rrent can be ob ta i ned by the following equat io n. I
TEST CIRCUIT
-40 to 85°C -55 to 125°C
= CPD x VCC x fIN + ICC
CC(opr)
Unit
CL = 50pF or equivalent (incl udes jig and p robe capacitance)
R
= Z
of pulse generator (typically 50Ω)
T
OUT
WAVEFORM : PROPAGATION DELAY TIMES, MINIMUM PULSE WIDTH, SETUP AND HOLD TIMES
(f=1MHz; 50% duty cycle)
5/9
Page 6
M74HCT75
Plastic DIP-16 (0.25) MECHANICAL DATA
mm.inch
DIM.
MIN.TYPMAX.MIN.TYP.MAX.
a10.510.020
B0.771.650.0300.065
b0.50.020
b10.250.010
D200.787
E8.50.335
e2.540.100
e317.780.700
F7.10.280
I5.10.201
L3.30.130
Z1.270.050
6/9
P001C
Page 7
SO-16 MECHANICAL DATA
M74HCT75
DIM.
A1.750.068
a10.10.20.0030.007
a21.650.064
b0.350.460.0130.018
b10.190.250.0070.010
C0.50.019
c145° (typ.)
D9.8100.3850.393
E5.86.20.2280.244
e1.270.050
e38.890.350
F3.84.00.1490.157
G4.65.30.1810.208
L0.51.270.0190.050
M0.620.024
S8° (max.)
MIN.TYPMAX.MIN.TYP.MAX.
mm.inch
PO13H
7/9
Page 8
M74HCT75
TSSOP16 MECHANICAL DATA
mm.inch
DIM.
MIN.TYPMAX.MIN.TYP.MAX.
A1.20.047
A10.050.150.0020.0040.006
A20.811.050.0310.0390.041
b0.190.300.0070.012
c0.090.200.0040.0089
D4.955.10.1930.1970.201
E6.26.46.60.2440.2520.260
E14.34.44.480.1690.1730.176
e0.65 BSC0.0256 BSC
K0°8°0°8°
L0.450.600.750.0180.0240.030
A2
A
A1
b
e
c
K
L
E
D
E1
PIN 1 IDENTIFICATION
8/9
1
0080338D
Page 9
M74HCT75
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consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from
its use. No li cense is granted by imp lica tion or otherwise under any patent or patent rig hts of STMicroelectronics. Specificat ions
mentioned in this publication ar e subject to change without notice. This publication supersedes and replaces all information
previously supplied. S TMicroelectronics products are not authorized for use as critica l components in life suppo rt devices or
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