Datasheet M74HCT533, M74HCT373 Datasheet (SGS Thomson Microelectronics)

Page 1
OCTAL D-TYPE LATCH WITH3 STATE OUTPUT
HCT373 NON INVERTING - HCT533INVERTING
.HIGH SPEED
tPD= 17 ns(TYP.) AT VCC=5V
.LOWPOWER DISSIPATION
ICC=4µA(MAX.) AT TA=25°C
.COMPATIBLE WITHTTL OUTPUTS
VIH= 2V(MIN.) VIL= 0.8V (MAX.)
.OUTPUT DRIVE CAPABILITY
15 LSTTLLOADS
.SYMMETRICALOUTPUT IMPEDANCE
IOL=IOH= 6 mA (MIN.)
.BALANCEDPROPAGATION DELAYS
t
PLH=tPHL
.PIN AND FUNCTION COMPATIBLE
WITH 54/74LS373/533
DESCRIPTION
M54/74HCT373
M54/74HCT533
B1R
(PlasticPackage)
M1R
(MicroPackage)
ORDER CODES :
F1R
(CeramicPackage)
C1R
(Chip Carrier)
The M54/74HCT373 and M54HCT533 are high speed CMOS OCTAL LATCH WITH 3-STATE OUTPUTS fabricated with in silicon gate C2MOS technology. These ICs achive the high speed operation similar to equivalent LSTTL while maintaning the CMOS low power dissipation. These8 bit D-Typelatchesare controlled bya latch enable input(LE) and a output enable input (OE). While the LE input is held at a high level, the Q outputs will follow the data input precisely or inversely. When the LE is taken low, the Q outputs willbelatchedpreciselyorinversely atthelogiclevel of D inputdata. While the OE inputis at low level, the eight outputs will be inanormallogic state(high
PIN CONNECTION (top view)
HCT373 HCT533 HCT373 HCT533
or low logiclevel) andwhile high level the outptswill be in a high impedance state. The application designer has a choise of combination of inverting and non inverting outputs. The three state output configuration and the wide choise of outline make bus organizedsystemsimple. These integrated circuits have input and output characteristics that are fully compatible with 54/74 LSTTL logic families. M54/74HCT devices are designed to directly interface HSC2MOS systems with TTL and NMOS components. They are also plug in replacements for LSTTL devices giving a reduction of power consumption. All inputs are equipped with protection circuits against discharge and transient excess voltage.
October 1993
1/13
Page 2
M54/M74HCT373/533
INPUT AND OUTPUT EQUIVALENT CIRCUIT
PIN DESCRIPTION (HCT373)
PIN No SYMBOL NAME AND FUNCTION
1 OE 3 State output Enable
Input (Active LOW)
2, 5, 6, 9,
12, 15, 16,
19
3, 4, 7, 8,
13, 14, 17,
18 11 LE Latch Enable Input 10 GND Ground (0V) 20 V
Q0 to Q7 3 State outputs
D0 to D7 Data Inputs
CC
Positive Supply Voltage
IEC LOGIC SYMBOLS
HCT373 HCT533
PIN DESCRIPTION (H C T533 )
PIN No SYMBOL NAME AND FUNCTION
1 OE 3 State output Enable
Input (Active LOW)
2, 5, 6, 9,
12, 15, 16,
19
3, 4, 7, 8,
13, 14, 17,
18 11 LE Latch Enable Input 10 GND Ground (0V) 20 V
Q0 to Q7 3 State outputs
D0 to D7 Data Inputs
CC
Positive Supply Voltage
2/13
Page 3
TRUTH TABLE
INPUTS OUTPUTS
OE LE D Q (HCT373) Q (HCT533)
HXXZZ
L L X NO CHANGE * NO CHANGE * LHLLH LHHHL
X: DON’T CARE Z: HIGH IMPEDANCE *: Q/Q OUTPUTS ARE LATCHED AT THE TIME WHEN THE LE INPUT IS TAKEN LOW LOGIC LEVEL.
LOGIC DIAGRAMS
HCT373
M54/M74HCT373/533
HCT533
3/13
Page 4
M54/M74HCT373/533
ABSOLU TE MAXIMU M RATINGS
Symbol Parameter Value Unit
V
CC
V
V
O
I
IK
I
OK
I
O
I
or I
CC
P
D
T
stg
T
AbsoluteMaximumRatingsarethosevaluesbeyondwhichdamage tothedevicemayoccur.Functionaloperationunder theseconditionisnotimplied. (*)500 mW: 65oC derateto300mW by 10mW/oC: 65oCto85oC
RECO MM ENDED O PERAT IN G CONDI TIONS
Symbol Parameter Value Unit
V
CC
V
I
V
O
T
op
t
r,tf
Supply Voltage -0.5 to +7 V DC Input Voltage -0.5 to VCC+ 0.5 V
I
DC Output Voltage -0.5 to VCC+ 0.5 V DC Input Diode Current ± 20 mA DC Output Diode Current ± 20 mA DC Output Source Sink Current Per Output Pin ± 35 mA DC VCCor Ground Current ± 70 mA
GND
Power Dissipation 500 (*) mW Storage Temperature -65 to +150 Lead Temperature (10sec) 300
L
Supply Voltage 4.5 to 5.5 V Input Voltage 0 to V Output Voltage 0 to V Operating Temperature: M54HC Series
M74HC Series
CC CC
-55 to +125
-40 to +85
Input Rise and Fall Time (VCC= 4.5 to 5.5V) 0 to 500 ns
o
C
o
C
V V
o
C
o
C
4/13
Page 5
DC SPECIFICA TIONS
Symbol Parameter
V
V
V
V
I
I
I
High Level Input
IH
Voltage
Low Level Input
IL
Voltage
High Level
OH
Output Voltage
Low Level Output
OL
Voltage
Input Leakage
I
I
Current 3 State Output
OZ
Off State Current Quiescent Supply
CC
Current Additional worst
CC
case supply current
M54/M74HCT373/533
Test Conditions Value
T
=25oC
V
(V)
4.5
CC
A
54HC and 74HC
Min. Typ. Max. Min. Max. Min. Max.
2.0 2.0 2.0 V
to
5.5
4.5 to
5.5
VI=
IO=-20 µA 4.4 4.5 4.4 4.4
V
IH
4.5
or
I
=-6.0 mA 4.18 4.31 4.13 4.10
O
V
IL
VI=
IO=20µA 0.0 0.1 0.1 0.1
V
IH
4.5
or
I
= 6.0 mA 0.17 0.26 0.33 0.4
O
V
IL
VI=VCCor GND ±0.1 ±1 ±1 µA
5.5
6.0 VI=VIHor V
IL
VO=VCCor GND
5.5 VI=VCCor GND 4 40 80 µA
5.5 Per Input pin
VI= 0.5V or
VI= 2.4V
Other Inputs at
V
or GND
CC
-40 to 85oC 74HC
-55 to 125oC 54HC
Unit
0.8 0.8 0.8 V
±0.5 ±5.0 ±10 µA
2.0 2.9 3.0 mA
V
V
5/13
Page 6
M54/M74HCT373/533
AC ELECTRICAL CHARACTERISTICS (Input tr=tf=6ns)
Test Conditions Value
T
=25oC
Symbol Parameter
t t
t t
TLH THL
PLH PHL
Output Transition Time
Propagation Delay Time (LE - Q)
t t
PLH PHL
Propagation Delay Time (D - Q)
t
t
PZL PZH
3 State Output Enable Time (OE - Q)
t
t
PLZ PHZ
3 State Output Disable Time
C
V
CC
(V)
L
(pF)
4.5 50 7 12 15 18 ns
4.5 50 20 30 38 45 ns
4.5 150 24 37 46 56 ns
4.5 50 19 30 38 45 ns
4.5 150 23 36 45 54 ns
4.5 50 RL=1K 20 30 38 45 ns
4.5 150 R
=1K 24 37 46 56 ns
L
4.5 50 RL=1K 20 30 38 45 ns
A
54HC and 74HC
Min. Typ. Max. Min. Max. Min. Max.
(OE - Q)
t
W(H)
Minimum Pulse
4.5 50 8 15 19 22 ns
Width (LE)
t
s
Minimum Set-up
4.5 50 4 10 13 15 ns
Time
t
h
Minimum Hold
4.5 50 5 5 8 ns
Time
C
C
PD
(*) CPDisdefined as the value of the IC’sinternal equivalentcapacitance which is calculated fromtheoperatingcurrent consumption withoutload. (Refer to TestCircuit).Average operting current can be obtained by the following equation. ICC(opr) = CPD• VCC•fIN+ICC/8(per Flip Flop) and the CPDwhenN pcs of FlipFlopoperate, can be gainedby followingequation: CPD(TOTAL)= 32 + 34x n[pF] (forHCT373); 30+ 22 x n [pF](forHCT533)
Input Capacitance 5 10 10 10 pF
IN
(*) Power Dissipation
Capacitance
HCT373 HCT533
66 52
-40 to 85oC 74HC
-55 to 125oC 54HC
Unit
pF
6/13
Page 7
SWITCHING CHARACTERISTICS TEST WAVEFORM
M54/M74HCT373/533
t
PLH,tPHL,ts,th,tw
t
PLZ,tPZL
The 1KΩ load resistors should be connected between outputs and VCCline and the 50pF load capacitors should be connected between outputsand GND line. All inputs except OE input should be connected to V
CC
line or GND line such that outputs will be in low logic level while OE input is held low.
f
MAX
t
PHZ,tPZH
The 1Kload resistors and the 50pF load capacitors should be connected between each output and GND line. All inputs except OE input should be connected to V
CC
or GND line such that output will be in high logic level while OE input is held low.
7/13
Page 8
M54/M74HCT373/533
TEST CIRCUIT ICC(Opr.)
8/13
Page 9
M54/M74HCT373/533
Plastic DIP20 (0.25) MECHANICAL DATA
DIM.
MIN. TYP. MAX. MIN. TYP. MAX.
a1 0.254 0.010
B 1.39 1.65 0.055 0.065
b 0.45 0.018
b1 0.25 0.010
D 25.4 1.000 E 8.5 0.335
e 2.54 0.100
e3 22.86 0.900
F 7.1 0.280
I 3.93 0.155
L 3.3 0.130
Z 1.34 0.053
mm inch
P001J
9/13
Page 10
M54/M74HCT373/533
Ceramic DIP20 MECHANICAL DATA
DIM.
MIN. TYP. MAX. MIN. TYP. MAX.
A 25 0.984 B 7.8 0.307 D 3.3 0.130 E 0.5 1.78 0.020 0.070
e3 22.86 0.900
F 2.29 2.79 0.090 0.110
G 0.4 0.55 0.016 0.022
I 1.27 1.52 0.050 0.060
L 0.22 0.31 0.009 0.012
M 0.51 1.27 0.020 0.050
N1 4° (min.), 15° (max.)
P 7.9 8.13 0.311 0.320
Q 5.71 0.225
mm inch
10/13
P057H
Page 11
SO20 MECHANICAL DATA
M54/M74HCT373/533
DIM.
MIN. TYP. MAX. MIN. TYP. MAX.
A 2.65 0.104 a1 0.10 0.20 0.004 0.007 a2 2.45 0.096
b 0.35 0.49 0.013 0.019
b1 0.23 0.32 0.009 0.012
C 0.50 0.020 c1 45° (typ.)
D 12.60 13.00 0.496 0.512
E 10.00 10.65 0.393 0.419
e 1.27 0.050
e3 11.43 0.450
F 7.40 7.60 0.291 0.299
L 0.50 1.27 0.19 0.050
M 0.75 0.029
S8°(max.)
mm inch
P013L
11/13
Page 12
M54/M74HCT373/533
PLCC20 MECHANICAL DATA
DIM.
MIN. TYP. MAX. MIN. TYP. MAX.
A 9.78 10.03 0.385 0.395
B 8.89 9.04 0.350 0.356
D 4.2 4.57 0.165 0.180 d1 2.54 0.100 d2 0.56 0.022
E 7.37 8.38 0.290 0.330
e 1.27 0.050
e3 5.08 0.200
F 0.38 0.015
G 0.101 0.004 M 1.27 0.050
M1 1.14 0.045
mm inch
12/13
P027A
Page 13
M54/M74HCT373/533
Information furnished is believed to be accurate and reliable.However, SGS-THOMSON Microelectronics assumes no responsability for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may results from its use. No license is granted byimplication or otherwise under any patent or patent rights ofSGS-THOMSON Microelectronics. Specificationsmentioned in this publication are subject to change without notice.This publication supersedes and replaces all information previously supplied. SGS-THOMSON Microelectronicsproducts are not authorized foruse ascritical componentsin life support devices orsystems without express written approval of SGS-THOMSON Microelectonics.
1994 SGS-THOMSON Microelectronics - All Rights Reserved
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13/13
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