The M74HCT374 is an high speed CMOS OCTAL
D-TYPE FLIP FLOP WITH 3-STATE OUTPUTS
NON INVERTING fabricated with silicon gate
2
C
MOS technology.
This 8 bit D-TYPE FLIP FLOP is con trolled by a
clock input (CK) and an o utpu t enable input (OE
On the positive transition of the clock, the Q
outputs will be set to the logic state that were
setup at the D inputs.
While the OE
input is at low level, the eight outputs
will be in a norm al logic state (high or low logic
level) and while OE
is at high level the outputs will
be in a high impedance state.
ORDER CODES
PACKAGETUBET & R
DIPM74HCT374B1R
SOPM74HCT374M1R M74HCT374RM13TR
TSSOPM74HCT374TTR
The output control does not affect the internal
operation of flip-flops; that is, the old data can be
retained or the new data can be entered even
).
while the outputs are off.
The M74HCT374 is designed to directly interface
2
HSC
MOS systems with TTL and NMOS
components.
All inputs are equipped with protection circuits
against static discharge and transient excess
voltage.
TSSOPDIPSOP
PIN CONNECTION AND IEC LOGIC SYMBOLS
1/11July 2001
Page 2
M74HCT374
INPUT AND OUTPUT EQUIVALENT CIRCUIT PIN DESCRIPTION
PIN NoSYMBOLNAME AND FUNCTION
1OE
2, 5, 6, 9, 12,
15, 16, 19
3, 4, 7, 8, 13,
14, 17, 18
11CKClock Input (LOW to
10GNDGround (0V)
20V
TRUTH TABLE
INPUTSOUTPUT
Q0 to Q73 State Outputs
D0 to D7Data Inputs
CC
3 State Output Enable
Input (Active LOW)
HIGH, edge triggered)
Positive Supply Voltage
OE
HXXZ
LXNO CHANGE
LLL
LHH
X: Don’t Care
Z: High Impedance
LOGIC DIAGRAM
CKDQ
This log i c diagram has not be used to e st i m ate propagation dela ys
2/11
Page 3
M74HCT374
ABSOLUTE MAXIMUM RATINGS
SymbolParameterValueUnit
V
V
V
I
I
OK
I
I
or I
CC
P
T
T
Absolute Maximum Ratings are those values beyond which damage to the device may occur. Functional operation under these conditions is
not implied
(*) 500mW at 65
RECOMMENDED OPERATING CONDITIONS
SymbolParameterValueUnit
V
V
V
T
t
r
Supply Voltage
CC
DC Input Voltage-0.5 to VCC + 0.5
I
DC Output Voltage-0.5 to VCC + 0.5
O
DC Input Diode Current
IK
DC Output Diode Current
DC Output Current
O
DC VCC or Ground Current
GND
Power Dissipation
D
Storage Temperature
stg
Lead Temperature (10 sec)
L
°C; derate to 300mW by 10mW/°C from 65° C to 85°C
Supply Voltage
CC
Input Voltage0 to V
I
Output Voltage0 to V
O
Operating Temperature
op
, t
Input Rise and Fall Time (VCC = 4.5 to 5.5V)
f
-0.5 to +7V
± 20mA
± 20mA
± 35mA
± 70mA
500(*)mW
-65 to +150°C
300°C
4.5 to 5.5V
CC
CC
-55 to 125°C
0 to 500ns
V
V
V
V
3/11
Page 4
M74HCT374
DC SPECIFICATION
SymbolParameter
V
V
V
V
I
I
∆ I
High Level Input
IH
Voltage
Low Level Input
IL
Voltage
High Level Output
OH
Voltage
Low Level Output
OL
Voltage
I
Input Leakage
I
Current
High Impedance
OZ
Output Leakage
Current
Quiescent Supply
CC
Current
Additional Worst
CC
Case Supply
Current
Test ConditionValue
T
= 25°C
V
CC
(V)
A
Min.Typ. Max.Min.Max. Min. Max.
4.5
to
2.02.02.0V
5.5
4.5
to
0.80.80.8V
5.5
4.5
4.5
5.5
5.5
5.5
IO=-20 µA
I
=-6.0 mA
O
IO=20 µA
I
=6.0 mA
O
= VCC or GND
V
I
= VIH or V
V
I
VO = VCC or GND
= VCC or GND
V
I
5.5Per Input pin
= 0.5V or
V
I
V
= 2.4V
I
4.44.54.44.4
4.184.314.134.10
0.00.10.10.1
0.170.260.330.40
± 0.1± 1± 1µA
IL
± 0.5± 5± 10µA
2.02.93.0mA
Other Inputs at
V
or GND
CC
I
= 0
O
-40 to 85°C -55 to 125°C
Unit
V
V
44080µA
AC ELECTRICAL CHARACTERISTICS (C
Test ConditionValue
SymbolParameter
t
TLH tTHL
t
PLH tPHL
t
PZL tPZH
t
PLZ tPHZ
f
MAX
t
W(L)
t
W(H)
Output Transition
Time
Propagation Delay
Time (CLOCK-Q,Q
Output Enable
Time
Output Disable
Time
Maximum Clock
Frequency
Minimum Pulse
Width (CLOCK)
t
Minimum Set-Up
s
Time
Minimum Hold
t
h
Time
)
C
(pF)
L
V
CC
(V)
4.5507121518ns
4.55020303845
4.515025384857
4.550
4.515025384857
4.550
4.55031502521MHz
4.550151923ns
4.550151923ns
4.550000ns
= 50 pF, Input tr = tf = 6ns)
L
= 25°C
T
A
Min.Typ. Max.Min.Max. Min. Max.
= 1 KΩ
R
L
= 1 KΩ
R
L
17303845
16283542ns
-40 to 85°C -55 to 125°C
Unit
ns
ns
4/11
Page 5
M74HCT374
CAPACITIVE CHARACTERISTICS
Test ConditionValue
T
SymbolParameter
C
C
C
Input Capacitance
IN
Output
OUT
Capacitance
Power Dissipation
PD
Capacitance (note
V
CC
(V)
= 25°C
A
Min.Typ. Max.Min.Max. Min. Max.
5101010pF
10pF
48pF
1)
1) CPD is defined as the value of the IC’s internal equivalent capacitance which is calculated from the operating current consumption without
load. (Refer to Test Circuit). Average operating current can be obtained by the following equation. I
Flop) and the C
when n pcs of F lip Flop operate, can be gai ned by the fo l l owing equati on: C
PD
TEST CIRCUIT
-40 to 85°C -55 to 125°C
= CPD x VCC x fIN + ICC/8 (per Flip
CC(opr)
PD(TOTAL)
= 30 + 18 x n (pF)
Unit
TESTSWITCH
t
, t
PLH
PHL
, t
t
PZL
PLZ
t
, t
PZH
PHZ
CL = 50pF/150p F or equivalent (includes jig and probe capacitance)
R
= 1KΩ or equivalent
1
= Z
R
of pulse generator (typically 50Ω)
T
OUT
Open
V
CC
GND
5/11
Page 6
M74HCT374
WAVEFORM 1: CK TO Qn PROPAGATION DELAYS, MAXIMUM CK FREQUENCY, Dn TO CK
SETUP AND HOLD TIMES (f =1MHz; 50% duty cycl e)
6/11
Page 7
WAVEFORM 2: OUTPUT ENABLE AND DISABLE TIMES (f=1MHz; 50% duty cycl e )
Information furnished is bel ieved to be accurate and reliable. However, STMicroe lectronics assumes no responsibility for the
consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from
its use. No li cense is granted by i mp lica tion or otherwise under a n y patent or patent rig hts of STMicroelectronics. Spec ific at ions
mentioned in this publication ar e subject to change without notice. This publication supersedes and replaces all information
previously supplied. S TMicroelectronics products are not authorized for use as critica l components in life suppo rt devices or
systems without express written approval of STMicroelectronics.
Australi a - Brazil - C hi na - Finlan d - F rance - Germ any - Hong Kon g - I ndi a - Italy - Japan - Malaysia - Malta - Morocco