The M74HCT273 is an high speed CMOS OCTAL
D TYPE FLIP FLOP WITH CLEAR fabricated with
silicon gate C
2
MOS technology.
Information signals applied to D inputs are
transferred to the Q output s on the positive-goi ng
edge of the clock pulse.
TSSOPDIPSOP
ORDER CODES
PACKAGETUBET & R
DIPM74HCT273B1R
SOPM74HCT273M1R M74HCT273RM13TR
TSSOPM74HCT273TTR
When the CLEAR
input is held low, the Q output
are in the low logic level independent of the other
inputs.
All inputs are equipped with protection circuits
against static discharge and transient excess
voltage.
PIN CONNECTION AND IEC LOGIC SYMBOLS
1/10August 2001
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M74HCT273
INPUT AND OUTPUT EQUIVALENT CIRCUIT PIN DESCRIPTION
PIN NoSYMBOLNAME AND FUNCTION
1CLEAR
2, 5, 6, 9, 12,
15, 16, 19
3, 4, 7, 8, 13,
14, 17, 18
11CLOCK
10GNDGround (0V)
20VccPositive Supply Voltage
TRUTH TABLE
Q0 to Q7Flip Flop Outputs
D0 to D7Data Inputs
Master Reset Input
(Active LOW)
Clock Input (LOW to
HIGH, Edge Triggered)
CLEAR
LXXLCLEAR
HLL
HHH
HXQnNO CHANGE
X : Don’t Care
LOGIC DIAGRAM
INPUTSOUTPUTS
FUNCTION
CLOCKDQ
This log i c diagram has not be used to esti m ate propagation delays
2/10
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M74HCT273
ABSOLUTE MAXIMUM RATINGS
SymbolParameterValueUnit
V
V
V
I
I
OK
I
I
or I
CC
P
T
T
Absolute Maximum Ratings are those values beyond which damage to the device may occur. Functional operation under these conditions is
not implied
(*) 500mW at 65
1) CPD is defined as the value of the IC’s internal equivalent capacitance which is calculated from the operating current consumption without
load. (Refer to Test Circuit). Average operating current can be obtained by the following equation. I
FLOP), and the total CP D when n pcs of FL IP FLOP oper at e can be gaine d by the following equations: CPD (total) = 32 + 11 x n
Input Capacitance
IN
Power Dissipation
PD
Capacitance (note 1)5.029pF
5.05101010pF
T
A
Min.Typ. Max.Min.Max. Min. Max.
-40 to 85°C -55 to 125°C
= CPD x VCC x fIN + ICC/8 (per FL IP
CC(opr)
Unit
4/10
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M74HCT273
TEST CIRCUIT
CL = 50pF or equivalent (in cludes jig and probe capaci tance)
R
= Z
of pulse generator (typically 50Ω)
T
OUT
WAVEFORM 1: PROPAGATION DELAY TIME, MINIMUM PULSE WIDTH (CLOCK), SETUP AND
HOLD TIME (nD TO CLOCK), CLOCK MAXIMUM FREQUENCY (f=1MHz; 50% duty cycle)
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M74HCT273
WAVEFORM 2 :PROPAGATION DELAY TIME ( f= 1 MHz; 50% duty cycl e )
WAVEFORM 3 : MINIMUM PULSE WIDTH (CLEAR), MINIMUM REMOVAL TIME (C LEAR TO
CLOCK)(f=1MHz; 50% duty cycle)
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M74HCT273
Plastic DIP-20 (0.25) MECHANICAL DATA
mm.inch
DIM.
MIN.TYPMAX.MIN.TYP.MAX.
a10.2540.010
B1.391.650.0550.065
b0.450.018
b10.250.010
D25.41.000
E8.50.335
e2.540.100
e322.860.900
F7.10.280
I3.930.155
L3.30.130
Z1.340.053
P001J
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M74HCT273
SO-20 MECHANICAL DATA
DIM.
MIN.TYPMAX.MIN.TYP.MAX.
A2.650.104
a10.10.20.0040.008
a22.450.096
b0.350.490.0140.019
b10.230.320.0090.012
C0.50.020
c145° (typ.)
D12.6013.000.4960.512
E10.0010.650.3930.419
e1.270.050
e311.430.450
F7.407.600.2910.300
L0.501.270.0200.050
M0.750.029
S8° (max.)
mm.inch
8/10
PO13L
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M74HCT273
TSSOP20 MECHANICAL DATA
mm.inch
DIM.
MIN.TYPMAX.MIN.TYP.MAX.
A1.20.047
A10.050.150.0020.0040.006
A20.811.050.0310.0390.041
b0.190.300.0070.012
c0.090.200.0040.0089
D6.46.56.60.2520.2560.260
E6.26.46.60.2440.2520.260
E14.34.44.480.1690.1730.176
e0.65 BSC0.0256 BSC
K0°8°0°8°
L0.450.600.750.0180.0240.030
A2
A
A1
b
e
K
c
L
E
D
E1
PIN 1 IDENTIFICATION
1
0087225C
9/10
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M74HCT273
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mentioned in this publication ar e subject to change without notice. This publication supersedes and replaces all information
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