The M74HC74 is an high speed CMOS DUAL D
TYPE FLIP FLOP WITH CLEAR fabricated with
silicon gate C
2
MOS technology.
A signal on the D INPU T is transferred on the Q
OUTPUT during the positive going transition of the
clock pulse. CLEAR and PRESET are
TSSOPDIPSOP
ORDER CODES
PACKAGETUBET & R
DIPM74HC74B1R
SOPM74HC74M1RM74HC74RM13TR
TSSOPM74HC74TTR
independent of t he clock and accomplis hed by a
low on the appropriate input.
All inputs are equipped with protection circuits
against static discharge and transient excess
voltage.
PIN CONNECTION AND IEC LOGIC SYMBOLS
1/12July 2001
Page 2
M74HC74
INPUT AND OUTPUT EQUIVALENT CIRCUIT PIN DESCRIPTION
PIN NoSYMBOLNAME AND FUNCTION
1,131CLR
2, 121D, 2DData Inputs
3, 111CK, 2CK
4, 101PR
5, 91Q, 2QTrue Flip-Flop Outputs
6, 81Q
7GNDGround (0V)
14VccPositive Supply Voltage
TRUTH TABLE
, 2CLR
, 2PR
, 2Q
Asynchronous Reset Direct Input
Clock Input
(LOW-to-HIGH,
Edge-Triggered)
Asynchronous Set - Direct
Input
Complement Flip-Flop
Outputs
INPUTSOUTPUTS
CLR
LHXXLHCLEAR
HLXXHLPRESET
LLXXHH----
HHLLH---HHHHL---HHX
X : Don’t Care
PRDCKQ Q
Q
n
Q
n
LOGIC DIAGRAM
FUNCTION
NO CHANGE
This log i c diagram has not be used to est i m at e propagation delays
2/12
Page 3
M74HC74
ABSOLUTE MAXIMUM RATINGS
SymbolParameterValueUnit
V
V
V
I
I
OK
I
I
or I
CC
P
T
T
Absolute Maximum Ratings are those values beyond which damage to the device may occur. Functional operation under these conditions is
not implied
(*) 500mW at 65
1) CPD is defined as the value of the IC’s internal equivalent capacitance which is calculated from the operating current consumption without
load. (Refer to Test Circuit). Average operating current can be obtained by the following equation. I
FLOP)
Input Capacitance
IN
Power Dissipation
PD
Capacitance (note 1)5.034pF
5.05101010pF
T
A
-40 to 85°C -55 to 125°C
Min.Typ. Max.Min.Max. Min. Max.
= CPD x VCC x fIN + ICC/2 (per FLIP/
CC(opr)
Unit
5/12
Page 6
M74HC74
TEST CIRCUIT
CL = 50pF or equivalent (includes jig and p robe capacit ance)
= Z
R
WAVEFORM 1: nCK TO nQ,nQ PROPAGATION DELAY TIMES,nD TO nCK SETUP AND HOLD
TIMES, nCK MINIMUM PULSE WIDTH, MAXIMUM nCK FREQUENCY (f=1MHz; 50% duty cycle)
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