The M74HC564 is an high speed CMOS OCTAL
D-TYPE FLIP FLOP WITH 3-STATE OUTPUTS
INVER TING fabric ated with silicon g ate C
2
MOS
technology.
This 8 bit D-TYPE FLIP FLOP is con trolled by a
clock input (CK) and an o utpu t enable input (OE
On the positive transition of the clock, the Q
outputs will be set to the logic state that were
setup at the D inputs.
While the OE
input is at low level, the eight outputs
will be in a norm al logic state (high or low logic
ORDER CODES
PACKAGETUBET & R
DIPM74HC564B1R
SOPM74HC564M1RM74HC564RM13TR
TSSOPM74HC564TTR
level) and while high le vel the outpu ts will be in a
high impedance state.
The output control does not affect the internal
operation of flip-flops; that is, the old data can be
retained or the new data can be entered even
).
while the outputs are off.
All inputs are equipped with protection circuits
against static discharge and transient excess
voltage.
TSSOPDIPSOP
PIN CONNECTION AND IEC LOGIC SYMBOLS
1/11August 2001
Page 2
M74HC564
INPUT AND OUTPUT EQUIVALENT CIRCUIT PIN DESCRIPTION
PIN NoSYMBOLNAME AND FUNCTION
1OE
2, 3, 4, 5, 6,
7, 8, 9, 10
12, 13, 14,
15, 16, 17,
18, 19
11CLOCKClock Input (LOW to
10GNDGround (0V)
20V
TRUTH TABLE
INPUTSOUTPUT
to D7Data Inputs
D0
Q0
to Q73 State Outputs
CC
3 State Output Enable
Input (Active LOW)
HIGH, edge triggered)
Positive Supply Voltage
OE
HXXZ
LXNO CHANGE
LLH
LHL
X: Don’t Care
Z: High Impedance
LOGIC DIAGRAM
CKDQ
This log i c diagram has not be used to esti m ate propagation delays
2/11
Page 3
M74HC564
ABSOLUTE MAXIMUM RATINGS
SymbolParameterValueUnit
V
V
V
I
I
OK
I
I
or I
CC
P
T
T
Absolute Maximum Ratings are those values beyond which damage to the device may occur. Functional operation under these conditions is
not implied
(*) 500mW at 65
1) CPD is defined as the value of the IC’s internal equivalent capacitance which is calculated from the operating current consumption without
load. (R ef er to Test Circ ui t). Averag e operatin g current can be obtained by t he following equation. I
flip-fllop)
-40 to 85°C -55 to 125°C
= CPD x VCC x fIN + ICC/8(per
CC(opr)
Unit
5/11
Page 6
M74HC564
TEST CIRCUIT
TESTSWITCH
t
, t
PLH
PHL
, t
t
PZL
PLZ
t
, t
PZH
PHZ
CL = 50pF/150pF or equivalent (includes jig and probe capacitance)
= 1KΩ or equivalent
R
1
R
= Z
of pulse generator (t ypically 50Ω)
T
OUT
Open
V
CC
GND
WAVEFORM 1: CK TO Qn PROPAGATION DELAYS, Dn TO CK SETUP AND HOLD TIMES, CK
MAXIMUM FREQUENCY (f=1MHz; 50% duty cycle)
6/11
Page 7
WAVEFORM 2: OUTPUT ENABLE AND DISABLE TIMES (f=1MHz; 50% duty cycl e )
M74HC564
WAVEFORM 3: CK MINIMUM PULSE WIDTH (f=1MHz; 50% duty cycle)
7/11
Page 8
M74HC564
Plastic DIP-20 (0.25) MECHANICAL DATA
mm.inch
DIM.
MIN.TYPMAX.MIN.TYP.MAX.
a10.2540.010
B1.391.650.0550.065
b0.450.018
b10.250.010
D25.41.000
E8.50.335
e2.540.100
e322.860.900
F7.10.280
I3.930.155
L3.30.130
Z1.340.053
8/11
P001J
Page 9
SO-20 MECHANICAL DATA
M74HC564
DIM.
MIN.TYPMAX.MIN.TYP.M AX.
A2.650.104
a10.10.20.0040.008
a22.450.096
b0.350.490.0140.019
b10.230.320.0090.012
C0.50.020
c145° (typ.)
D12.6013.000.4960.512
E10.0010.650.3930.419
e1.270.050
e311.430.450
F7.407.600.2910.300
L0.501.270.0200.050
M0.750.029
S8° (max.)
mm.inch
PO13L
9/11
Page 10
M74HC564
TSSOP20 MECHANICAL DATA
mm.inch
DIM.
MIN.TYPMAX.MIN.TYP.M AX.
A1.20.047
A10.050.150.0020.0040.006
A20.811.050.0310.0390.041
b0.190.300.0070.012
c0.090.200.0040.0089
D6.46.56.60.2520.2560.260
E6.26.46.60.2440.2520.260
E14.34.44.480.1690.1730.176
e0.65 BSC0.0256 BSC
K0°8°0°8°
L0.450.600.750.0180.0240.030
A2
A
A1
b
e
K
c
L
E
D
E1
PIN 1 IDENTIFICATION
10/11
1
0087225C
Page 11
M74HC564
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mentioned in this publication ar e subject to change without notice. This publication supersedes and replaces all information
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