The M74HC4520 is an h igh speed CMOS DUAL
BINARY COUNTER fabricated with silicon gate
2
C
MOS technology.
It consists of t wo identical internally synchronous
4-stage counters. The counter stages are D-TYPE
flip-flops having interchangeable CLOCK and
ENABLE inputs for incrementing on either the
positive-going or negative-going transition.
For single-unit operation the ENABLE input is
maintained "high" and the counter advances on
TSSOPDIPSOP
ORDER CODES
PACKAGETUBET & R
DIPM74HC4520B1R
SOPM74HC4520M1R M74HC4520RM13TR
TSSOPM74HC4520TTR
each positive-going t ransition of the CLOCK. T he
counters are cleared by high levels on their clear
lines.
The counter can be cascaded in the ripple mode
by connecting Q4 to the enable input of the
subsequent counter while the clock input of the
latter is held permanently low.
All inputs are equipped with protection circuits
against static discharge and transient excess
voltage.
PIN CONNECTION AND IEC LOGIC SYMBOLS
1/12July 2001
Page 2
M74HC4520
INPUT AND OUTPUT EQUIVALENT CIRCUIT PIN DESCRIPTION
PIN NoSYMBOLNAME AND FUNCTION
1, 9
2, 101CE, 2CEClock Enable Inputs
3, 4, 5, 61Q0 to 1Q3 Data Outputs
7, 15
11, 12, 13,
14
8GNDGround (0V)
16VccPositive Supply Voltage
TRUTH TABLE
1CLOCK,
2CLOCK
1CLEAR,
2CLEAR
2Q0 tO 2Q3 Data Outputs
Clock Inputs (LOW to
HIGH, Edge-Triggered)
Asynchronous Reset
Inputs (Active LOW)
CLOCKCLOCK ENABLECLEAR
LLINCREMENT COUNTER
XLNO CHANGE
HLNO CHANGE
XXHQ0 THRU Q3=L
X : Don’t Care
Z : High Impedance
INPUTS
FUNCTION
HLINCREMENT COUNTER
XLNO CHANGE
LLNO CHANGE
2/12
Page 3
LOGIC DIAGRAM
M74HC4520
This log i c diagram has not be used to est i m at e propagation delays
TIMING CHART
3/12
Page 4
M74HC4520
ABSOLUTE MAXIMUM RATINGS
SymbolParameterValueUnit
V
V
V
I
I
OK
I
I
or I
CC
P
T
T
Absolute Maximum Ratings are those values beyond which damage to the device may occur. Functional operation under these conditions is
not implied
(*) 500mW at 65
1) CPD is defined as the value of the IC’s internal equivalent capacitance which is calculated from the operating current consumption without
load. (R ef er to Test Circui t). Averag e operating current can be obtained by the following equation. I
COUNTER)
-40 to 85°C -55 to 125°C
= CPD x VCC x fIN + ICC/2 (per
CC(opr)
Unit
6/12
Page 7
M74HC4520
TEST CIRCUIT
CL = 50pF or equivalent (includes jig and p robe capacit ance)
R
= Z
of pulse generator (typically 50Ω)
T
OUT
WAVEFORM 1: PROPAGATION DELAY, MINIMUM PULSE WIDTH AND REMOVAL TIMES (CLEAR)
(f=1MHz; 50% duty cycle)
7/12
Page 8
M74HC4520
WAVEFORM 2 :PROPAGATION DELAY, MINIMUM PULSE WIDTH AND REMOVAL TIMES (CLOCK
AND CE) (f=1MHz; 50% duty cycle)
8/12
Page 9
M74HC4520
Plastic DIP-16 (0.25) MECHANICAL DATA
mm.inch
DIM.
MIN.TYPMAX.MIN.TYP.MAX.
a10.510.020
B0.771.650.0300.065
b0.50.020
b10.250.010
D200.787
E8.50.335
e2.540.100
e317.780.700
F7.10.280
I5.10.201
L3.30.130
Z1.270.050
P001C
9/12
Page 10
M74HC4520
SO-16 MECHANICAL DATA
DIM.
A1.750.068
a10.10.20.0030.007
a21.650.064
b0.350.460.0130.018
b10.190.250.0070.010
C0.50.019
c145° (typ.)
D9.8100.3850.393
E5.86.20.2280.244
e1.270.050
e38.890.350
F3.84.00.1490.157
G4.65.30.1810.208
L0.51.270.0190.050
M0.620.024
S8° (max.)
MIN.TYPMAX.MIN.TYP.MAX.
mm.inch
10/12
PO13H
Page 11
M74HC4520
TSSOP16 MECHANICAL DATA
mm.inch
DIM.
MIN.TYPMAX.MIN.TYP.MAX.
A1.20.047
A10.050.150.0020.0040.006
A20.811.050.0310.0390.041
b0.190.300.0070.012
c0.090.200.0040.0089
D4.955.10.1930.1970.201
E6.26.46.60.2440.2520.260
E14.34.44.480.1690.1730.176
e0.65 BSC0.0256 BSC
K0°8°0°8°
L0.450.600.750.0180.0240.030
A2
A
A1
b
e
c
K
L
E
D
E1
PIN 1 IDENTIFICATION
1
0080338D
11/12
Page 12
M74HC4520
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