The M74HC4518 is an h igh speed CMOS DUAL
BINARY COUNTER fabricated with silicon gate
2
C
MOS technology.
It consist of two identical internally synchronous
4-stage counters. The counter stages are D-TYPE
flip-flops having interchangeable CLOCK and
ENABLE inputs for incrementing on either the
positive-going or negative-going transition.
For single-unit operation the ENABLE input is
maintained "high" and the counter advances on
TSSOPDIPSOP
ORDER CODES
PACKAGETUBET & R
DIPM74HC4518B1R
SOPM74HC4518M1R M74HC4518RM13TR
TSSOPM74HC4518TTR
each positive-going t ransition of the CLOCK. T he
counters are cleared by high levels on their clear
lines.
The counter can be cascaded in the ripple mode
by connecting Q4 to the enable input of the
subsequent counter while the clock input of the
latter is held permanently low.
All inputs are equipped with protection circuits
against static discharge and transient excess
voltage.
PIN CONNECTION AND IEC LOGIC SYMBOLS
1/11July 2001
Page 2
M74HC4518
INPUT AND OUTPUT EQUIVALENT CIRCUIT PIN DESCRIPTION
PIN NoSYMBOLNAME AND FUNCTION
1, 9
2, 10
3, 4, 5, 61Q0 to 1Q3 Data Outputs
7, 15
11, 12, 13,
14
8GNDGround (0V)
16VccPositive Supply Voltage
TRUTH TABLE
1CLOCK,
2CLOCK
1ENABLE,
2ENABLE
1CLEAR,
2CLEAR
2Q0 tO 2Q3 Data Outputs
Clock Inputs (LOW to
HIGH, Edge-Triggered)
Clock Enable Inputs
Asynchronous Reset
Inputs (Active LOW)
CLOCKENABLECLEAR
LLINCREMENT COUNTER
XLNO CHANGE
HLNO CHANGE
XXHQ0 THRU Q3=L
X : Don’t Care
Z : High Impedance
LOGIC DIAGRAM
INPUTS
FUNCTION
HLINCREMENT COUNTER
XLNO CHANGE
LLNO CHANGE
This log i c diagram has not be used to est i m at e propagation delays
2/11
Page 3
TIMING CHART
M74HC4518
ABSOLUTE MAXIMUM RATINGS
SymbolParameterValueUnit
V
V
V
I
I
OK
I
I
or I
CC
P
T
T
Absolute Maximum Ratings are those values beyond which damage to the device may occur. Functional operation under these conditions is
not implied
(*) 500mW at 65
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