The M74HC4020 is an high speed CMOS 14
STAGE BINARY COUNTER fabricated with
silicon gate C
2
MOS technology.
A clear input is used to reset the counter to the all
low level state. A high level on CLEAR
accomplishes the reset function. A negative
transition on the CLOCK
input increments the
counter by one.
TSSOPDIPSOP
ORDER CODES
PACKAGETUBET & R
DIPM74HC4020B1R
SOPM74HC4020M1R M74HC4020RM13TR
TSSOPM74HC4020TTR
For M74HC4020 twelve kind of divided output are
provided; 1st and 4th stage to 14th stage.
The maximum division available at last stage is
1/16384 x f
at clock.
IN
All inputs are equipped with protection circuits
against static discharge and transient excess
voltage.
PIN CONNECTION AND IEC LOGIC SYMBOLS
1/11July 2001
Page 2
M74HC4020
INPUT AND OUTPUT EQUIVALENT CIRCUIT PIN DESCRIPTION
PIN NoSYMBOLNAME AND FUNCTION
9, 7, 6, 5, 3,
2, 4, 13, 12,
14, 15, 1
10CLOCK
11CLEARReset Inputs
8GNDGround (0V)
16VccPositive Supply Voltage
TRUTH TABLE
CLOCKCLEAROUTPUT STATE
XHALL OUTPUTS = "L"
LNO CHANGE
LADVANCE TO NEXT STATE
LOGIC DIAGRAM
Q1, Q4 to
Q14
Parallel Outputs
Clock Input (LOW to
HIGH, Edge Triggered)
This log i c diagram has not be used to est i m at e propagation delays
2/11
Page 3
M74HC4020
ABSOLUTE MAXIMUM RATINGS
SymbolParameterValueUnit
V
V
V
I
I
OK
I
I
or I
CC
P
T
T
Absolute Maximum Ratings are those values beyond which damage to the device may occur. Functional operation under these conditions is
not implied
(*) 500mW at 65
1) CPD is defined as the value of the IC’s internal equivalent capacitance which is calculated from the operating current consumption without
load. (Refer to Test Circuit). Average operating current can be obtained by the following equation. I
FLOP)
Input Capacitance
IN
Power Dissipation
PD
Capacitance (note 1)5.034pF
5.05101010pF
= 25°C
A
Min.Typ. Max.Min.Max. Min. Max.
-40 to 85°C -55 to 125°C
= CPD x VCC x fIN + ICC/2 (per FLIP/
CC(opr)
Unit
5/11
Page 6
M74HC4020
TEST CIRCUIT
CL = 50pF or equivalent (includes jig and p robe capacit ance)
R
= Z
of pulse generator (typically 50Ω)
T
OUT
WAVEFORM 1: MINIMUM PULSE WIDTH (CLEAR) AND REMOVAL TIME (CLEAR TO CLOCK)
(f=1MHz; 50% duty cycle)
6/11
Page 7
WAVEFORM 2 : PROPAGATION DELAY TIME (f=1MHz; 50% duty cycle)
M74HC4020
WAVEFORM 3 : PROPAGATION DELAY TIME, MINIMUM PULSE WIDTH (CLOCK
duty cycle)
)(f=1MHz; 50%
7/11
Page 8
M74HC4020
Plastic DIP-16 (0.25) MECHANICAL DATA
mm.inch
DIM.
MIN.TYPMAX.MIN.TYP.MAX.
a10.510.020
B0.771.650.0300.065
b0.50.020
b10.250.010
D200.787
E8.50.335
e2.540.100
e317.780.700
F7.10.280
I5.10.201
L3.30.130
Z1.270.050
8/11
P001C
Page 9
SO-16 MECHANICAL DATA
M74HC4020
DIM.
A1.750.068
a10.10.20.0030.007
a21.650.064
b0.350.460.0130.018
b10.190.250.0070.010
C0.50.019
c145° (typ.)
D9.8100.3850.393
E5.86.20.2280.244
e1.270.050
e38.890.350
F3.84.00.1490.157
G4.65.30.1810.208
L0.51.270.0190.050
M0.620.024
S8° (max.)
MIN.TYPMAX.MIN.TYP.MAX.
mm.inch
PO13H
9/11
Page 10
M74HC4020
TSSOP16 MECHANICAL DATA
mm.inch
DIM.
MIN.TYPMAX.MIN.TYP.MAX.
A1.20.047
A10.050.150.0020.0040.006
A20.811.050.0310.0390.041
b0.190.300.0070.012
c0.090.200.0040.0089
D4.955.10.1930.1970.201
E6.26.46.60.2440.2520.260
E14.34.44.480.1690.1730.176
e0.65 BSC0.0256 BSC
K0°8°0°8°
L0.450.600.750.0180.0240.030
A2
A
A1
b
e
c
K
L
E
D
E1
PIN 1 IDENTIFICATION
10/11
1
0080338D
Page 11
M74HC4020
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consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from
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mentioned in this publication ar e subject to change without notice. This publication supersedes and replaces all information
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