The M74HC374 is an high speed CMOS OCTAL
D-TYPE FLIP FLOP WITH 3-STATE OUTPUTS
NON INVERTING fabricated with sub-micron
silicon gate C
2
MOS technology.
This 8 bit D-TYPE FLIP FLOP is con trolled by a
clock input (CK) and an o utpu t enable input (OE
On the positive transition of the clock, the Q
outputs will be set to the logic state that were
setup at the D inputs.
While the OE
input is at low level, the eight outputs
will be in a norm al logic state (high or low logic
ORDER CODES
PACKAGETUBET & R
DIPM74HC374B1R
SOPM74HC374M1RM74HC374RM13TR
TSSOPM74HC374TTR
level) and while OE
is high the outputs will be in
a high impedance state.
The output control does not affect the internal
operation of flip-flops; that is, the old data can be
retained or the new data can be entered even
).
while the outputs are off.
All inputs are equipped with protection circuits
against static discharge and transient excess
voltage.
TSSOPDIPSOP
PIN CONNECTION AND IEC LOGIC SYMBOLS
1/11July 2001
Page 2
M74HC374
INPUT AND OUTPUT EQUIVALENT CIRCUIT PIN DESCRIPTION
PIN NoSYMBOLNAME AND FUNCTION
1OE
2, 5, 6, 9, 12,
15, 16, 19
3, 4, 7, 8, 13,
14, 17, 18
11CKClock Input (LOW to
10GNDGround (0V)
20V
TRUTH TABLE
INPUTSOUTPUT
Q0 to Q73 State Outputs
D0 to D7Data Inputs
CC
3 State Output Enable
Input (Active LOW)
HIGH, edge triggered)
Positive Supply Voltage
OE
HXXZ
LXNO CHANGE
LLL
LHH
X: Don’t Care
Z: High Impedance
LOGIC DIAGRAM
CKDQ
This log i c diagram has not be used to est i m at e propagation delays
2/11
Page 3
M74HC374
ABSOLUTE MAXIMUM RATINGS
SymbolParameterValueUnit
V
V
V
I
I
OK
I
I
or I
CC
P
T
T
Absolute Maximum Ratings are those values beyond which damage to the device may occur. Functional operation under these conditions is
not implied
(*) 500mW at 65
Information furnished is bel ieved to be accurate and reliable. However, STMicroe lectronics assumes no responsibility for the
consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from
its use. No li cense is granted by imp lication or otherwise under a ny patent or patent rig hts of STMicroelectronics. Spec ific at ions
mentioned in this publication ar e subject to change without notice. This publication supersedes and replaces all information
previously supplied. S TMicroelectronics products are not authorized for use as critica l components in life suppo rt devices or
systems without express written approval of STMicroelectronics.
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